2 * SAS structures and definitions header file
4 * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
5 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
7 * This file is licensed under GPLv2.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 #include <linux/types.h>
30 #include <asm/byteorder.h>
32 #define SAS_ADDR_SIZE 8
33 #define HASHED_SAS_ADDR_SIZE 3
34 #define SAS_ADDR(_sa) ((unsigned long long) be64_to_cpu(*(__be64 *)(_sa)))
36 #define SMP_REQUEST 0x40
37 #define SMP_RESPONSE 0x41
40 #define SSP_XFER_RDY 0x05
41 #define SSP_COMMAND 0x06
42 #define SSP_RESPONSE 0x07
45 #define SMP_REPORT_GENERAL 0x00
46 #define SMP_REPORT_MANUF_INFO 0x01
47 #define SMP_READ_GPIO_REG 0x02
48 #define SMP_DISCOVER 0x10
49 #define SMP_REPORT_PHY_ERR_LOG 0x11
50 #define SMP_REPORT_PHY_SATA 0x12
51 #define SMP_REPORT_ROUTE_INFO 0x13
52 #define SMP_WRITE_GPIO_REG 0x82
53 #define SMP_CONF_ROUTE_INFO 0x90
54 #define SMP_PHY_CONTROL 0x91
55 #define SMP_PHY_TEST_FUNCTION 0x92
57 #define SMP_RESP_FUNC_ACC 0x00
58 #define SMP_RESP_FUNC_UNK 0x01
59 #define SMP_RESP_FUNC_FAILED 0x02
60 #define SMP_RESP_INV_FRM_LEN 0x03
61 #define SMP_RESP_NO_PHY 0x10
62 #define SMP_RESP_NO_INDEX 0x11
63 #define SMP_RESP_PHY_NO_SATA 0x12
64 #define SMP_RESP_PHY_UNK_OP 0x13
65 #define SMP_RESP_PHY_UNK_TESTF 0x14
66 #define SMP_RESP_PHY_TEST_INPROG 0x15
67 #define SMP_RESP_PHY_VACANT 0x16
70 #define TMF_ABORT_TASK 0x01
71 #define TMF_ABORT_TASK_SET 0x02
72 #define TMF_CLEAR_TASK_SET 0x04
73 #define TMF_LU_RESET 0x08
74 #define TMF_CLEAR_ACA 0x40
75 #define TMF_QUERY_TASK 0x80
77 /* SAS TMF responses */
78 #define TMF_RESP_FUNC_COMPLETE 0x00
79 #define TMF_RESP_INVALID_FRAME 0x02
80 #define TMF_RESP_FUNC_ESUPP 0x04
81 #define TMF_RESP_FUNC_FAILED 0x05
82 #define TMF_RESP_FUNC_SUCC 0x08
83 #define TMF_RESP_NO_LUN 0x09
84 #define TMF_RESP_OVERLAPPED_TAG 0x0A
92 /* See sas_discover.c if you plan on changing these.
95 NO_DEVICE
= 0, /* protocol */
96 SAS_END_DEV
= 1, /* protocol */
97 EDGE_DEV
= 2, /* protocol */
98 FANOUT_DEV
= 3, /* protocol */
106 SAS_PROTOCOL_SATA
= 0x01,
107 SAS_PROTOCOL_SMP
= 0x02,
108 SAS_PROTOCOL_STP
= 0x04,
109 SAS_PROTOCOL_SSP
= 0x08,
110 SAS_PROTOCOL_ALL
= 0x0E,
113 /* From the spec; local phys only */
116 PHY_FUNC_LINK_RESET
, /* Enables the phy */
119 PHY_FUNC_CLEAR_ERROR_LOG
= 5,
120 PHY_FUNC_CLEAR_AFFIL
,
121 PHY_FUNC_TX_SATA_PS_SIGNAL
,
122 PHY_FUNC_RELEASE_SPINUP_HOLD
= 0x10, /* LOCAL PORT ONLY! */
123 PHY_FUNC_SET_LINK_RATE
,
126 /* SAS LLDD would need to report only _very_few_ of those, like BROADCAST.
127 * Most of those are here for completeness.
130 SAS_PRIM_AIP_NORMAL
= 1,
137 SAS_PRIM_AIP_RWP
= 8,
140 SAS_PRIM_BC_RCH0
= 10,
141 SAS_PRIM_BC_RCH1
= 11,
148 SAS_PRIM_NOTIFY_ENSP
= 17,
149 SAS_PRIM_NOTIFY_R0
= 18,
150 SAS_PRIM_NOTIFY_R1
= 19,
151 SAS_PRIM_NOTIFY_R2
= 20,
153 SAS_PRIM_CLOSE_CLAF
= 21,
154 SAS_PRIM_CLOSE_NORM
= 22,
155 SAS_PRIM_CLOSE_R0
= 23,
156 SAS_PRIM_CLOSE_R1
= 24,
158 SAS_PRIM_OPEN_RTRY
= 25,
159 SAS_PRIM_OPEN_RJCT
= 26,
160 SAS_PRIM_OPEN_ACPT
= 27,
166 SATA_PRIM_PMNAK
= 34,
167 SATA_PRIM_PMACK
= 35,
168 SATA_PRIM_PMREQ_S
= 36,
169 SATA_PRIM_PMREQ_P
= 37,
170 SATA_SATA_R_ERR
= 38,
173 enum sas_open_rej_reason
{
175 SAS_OREJ_UNKNOWN
= 0,
176 SAS_OREJ_BAD_DEST
= 1,
177 SAS_OREJ_CONN_RATE
= 2,
179 SAS_OREJ_RESV_AB0
= 4,
180 SAS_OREJ_RESV_AB1
= 5,
181 SAS_OREJ_RESV_AB2
= 6,
182 SAS_OREJ_RESV_AB3
= 7,
183 SAS_OREJ_WRONG_DEST
= 8,
184 SAS_OREJ_STP_NORES
= 9,
187 SAS_OREJ_NO_DEST
= 10,
188 SAS_OREJ_PATH_BLOCKED
= 11,
189 SAS_OREJ_RSVD_CONT0
= 12,
190 SAS_OREJ_RSVD_CONT1
= 13,
191 SAS_OREJ_RSVD_INIT0
= 14,
192 SAS_OREJ_RSVD_INIT1
= 15,
193 SAS_OREJ_RSVD_STOP0
= 16,
194 SAS_OREJ_RSVD_STOP1
= 17,
195 SAS_OREJ_RSVD_RETRY
= 18,
198 enum sas_gpio_reg_type
{
199 SAS_GPIO_REG_CFG
= 0,
201 SAS_GPIO_REG_RX_GP
= 2,
203 SAS_GPIO_REG_TX_GP
= 4,
206 struct dev_to_host_fis
{
207 u8 fis_type
; /* 0x34 */
213 union { u8 lbam
; u8 byte_count_low
; };
214 union { u8 lbah
; u8 byte_count_high
; };
222 union { u8 sector_count
; u8 interrupt_reason
; };
228 } __attribute__ ((packed
));
230 struct host_to_dev_fis
{
231 u8 fis_type
; /* 0x27 */
237 union { u8 lbam
; u8 byte_count_low
; };
238 union { u8 lbah
; u8 byte_count_high
; };
246 union { u8 sector_count
; u8 interrupt_reason
; };
252 } __attribute__ ((packed
));
254 /* Prefer to have code clarity over header file clarity.
256 #ifdef __LITTLE_ENDIAN_BITFIELD
257 struct sas_identify_frame
{
294 u8 sas_addr
[SAS_ADDR_SIZE
];
302 } __attribute__ ((packed
));
304 struct ssp_frame_hdr
{
306 u8 hashed_dest_addr
[HASHED_SAS_ADDR_SIZE
];
308 u8 hashed_src_addr
[HASHED_SAS_ADDR_SIZE
];
311 u8 changing_data_ptr
:1;
313 u8 retry_data_frames
:1;
323 } __attribute__ ((packed
));
325 struct ssp_response_iu
{
335 __be32 sense_data_len
;
336 __be32 response_data_len
;
340 } __attribute__ ((packed
));
342 /* ---------- SMP ---------- */
344 struct report_general_resp
{
346 __be16 route_indexes
;
350 u8 conf_route_table
:1;
353 u8 orej_retry_supp
:1;
361 u8 enclosure_logical_id
[8];
364 } __attribute__ ((packed
));
366 struct discover_resp
{
373 u8 attached_dev_type
:3;
379 u8 attached_sata_host
:1;
383 u8 attached_sata_dev
:1;
386 u8 attached_sata_ps
:1;
389 u8 attached_sas_addr
[8];
413 } __attribute__ ((packed
));
415 struct report_phy_sata_resp
{
429 struct dev_to_host_fis fis
;
433 u8 affil_stp_ini_addr
[8];
436 } __attribute__ ((packed
));
444 struct report_general_resp rg
;
445 struct discover_resp disc
;
446 struct report_phy_sata_resp rps
;
448 } __attribute__ ((packed
));
450 #elif defined(__BIG_ENDIAN_BITFIELD)
451 struct sas_identify_frame
{
488 u8 sas_addr
[SAS_ADDR_SIZE
];
496 } __attribute__ ((packed
));
498 struct ssp_frame_hdr
{
500 u8 hashed_dest_addr
[HASHED_SAS_ADDR_SIZE
];
502 u8 hashed_src_addr
[HASHED_SAS_ADDR_SIZE
];
506 u8 retry_data_frames
:1;
508 u8 changing_data_ptr
:1;
517 } __attribute__ ((packed
));
519 struct ssp_response_iu
{
529 __be32 sense_data_len
;
530 __be32 response_data_len
;
534 } __attribute__ ((packed
));
536 /* ---------- SMP ---------- */
538 struct report_general_resp
{
540 __be16 route_indexes
;
548 u8 orej_retry_supp
:1;
551 u8 conf_route_table
:1;
555 u8 enclosure_logical_id
[8];
558 } __attribute__ ((packed
));
560 struct discover_resp
{
567 u8 attached_dev_type
:3;
575 u8 attached_sata_host
:1;
577 u8 attached_sata_ps
:1;
580 u8 attached_sata_dev
:1;
583 u8 attached_sas_addr
[8];
607 } __attribute__ ((packed
));
609 struct report_phy_sata_resp
{
623 struct dev_to_host_fis fis
;
627 u8 affil_stp_ini_addr
[8];
630 } __attribute__ ((packed
));
638 struct report_general_resp rg
;
639 struct discover_resp disc
;
640 struct report_phy_sata_resp rps
;
642 } __attribute__ ((packed
));
645 #error "Bitfield order not defined!"