include/soc/tegra/pmc.h

   1 /*
   2  * Copyright (c) 2010 Google, Inc
   3  * Copyright (c) 2014 NVIDIA Corporation
   4  *
   5  * Author:
   6  *      Colin Cross <ccross@google.com>
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #ifndef __SOC_TEGRA_PMC_H__
  20 #define __SOC_TEGRA_PMC_H__
  21
  22 #include <linux/reboot.h>
  23
  24 #include <soc/tegra/pm.h>
  25
  26 struct clk;
  27 struct reset_control;
  28
  29 #ifdef CONFIG_PM_SLEEP
  30 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
  31 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
  32 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
  33 #endif /* CONFIG_PM_SLEEP */
  34
  35 #ifdef CONFIG_SMP
  36 bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
  37 int tegra_pmc_cpu_power_on(unsigned int cpuid);
  38 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
  39 #endif /* CONFIG_SMP */
  40
  41 /*
  42  * powergate and I/O rail APIs
  43  */
  44
  45 #define TEGRA_POWERGATE_CPU     0
  46 #define TEGRA_POWERGATE_3D      1
  47 #define TEGRA_POWERGATE_VENC    2
  48 #define TEGRA_POWERGATE_PCIE    3
  49 #define TEGRA_POWERGATE_VDEC    4
  50 #define TEGRA_POWERGATE_L2      5
  51 #define TEGRA_POWERGATE_MPE     6
  52 #define TEGRA_POWERGATE_HEG     7
  53 #define TEGRA_POWERGATE_SATA    8
  54 #define TEGRA_POWERGATE_CPU1    9
  55 #define TEGRA_POWERGATE_CPU2    10
  56 #define TEGRA_POWERGATE_CPU3    11
  57 #define TEGRA_POWERGATE_CELP    12
  58 #define TEGRA_POWERGATE_3D1     13
  59 #define TEGRA_POWERGATE_CPU0    14
  60 #define TEGRA_POWERGATE_C0NC    15
  61 #define TEGRA_POWERGATE_C1NC    16
  62 #define TEGRA_POWERGATE_SOR     17
  63 #define TEGRA_POWERGATE_DIS     18
  64 #define TEGRA_POWERGATE_DISB    19
  65 #define TEGRA_POWERGATE_XUSBA   20
  66 #define TEGRA_POWERGATE_XUSBB   21
  67 #define TEGRA_POWERGATE_XUSBC   22
  68 #define TEGRA_POWERGATE_VIC     23
  69 #define TEGRA_POWERGATE_IRAM    24
  70 #define TEGRA_POWERGATE_NVDEC   25
  71 #define TEGRA_POWERGATE_NVJPG   26
  72 #define TEGRA_POWERGATE_AUD     27
  73 #define TEGRA_POWERGATE_DFD     28
  74 #define TEGRA_POWERGATE_VE2     29
  75 #define TEGRA_POWERGATE_MAX     TEGRA_POWERGATE_VE2
  76
  77 #define TEGRA_POWERGATE_3D0     TEGRA_POWERGATE_3D
  78
  79 #define TEGRA_IO_RAIL_CSIA      0
  80 #define TEGRA_IO_RAIL_CSIB      1
  81 #define TEGRA_IO_RAIL_DSI       2
  82 #define TEGRA_IO_RAIL_MIPI_BIAS 3
  83 #define TEGRA_IO_RAIL_PEX_BIAS  4
  84 #define TEGRA_IO_RAIL_PEX_CLK1  5
  85 #define TEGRA_IO_RAIL_PEX_CLK2  6
  86 #define TEGRA_IO_RAIL_USB0      9
  87 #define TEGRA_IO_RAIL_USB1      10
  88 #define TEGRA_IO_RAIL_USB2      11
  89 #define TEGRA_IO_RAIL_USB_BIAS  12
  90 #define TEGRA_IO_RAIL_NAND      13
  91 #define TEGRA_IO_RAIL_UART      14
  92 #define TEGRA_IO_RAIL_BB        15
  93 #define TEGRA_IO_RAIL_AUDIO     17
  94 #define TEGRA_IO_RAIL_HSIC      19
  95 #define TEGRA_IO_RAIL_COMP      22
  96 #define TEGRA_IO_RAIL_HDMI      28
  97 #define TEGRA_IO_RAIL_PEX_CNTRL 32
  98 #define TEGRA_IO_RAIL_SDMMC1    33
  99 #define TEGRA_IO_RAIL_SDMMC3    34
 100 #define TEGRA_IO_RAIL_SDMMC4    35
 101 #define TEGRA_IO_RAIL_CAM       36
 102 #define TEGRA_IO_RAIL_RES       37
 103 #define TEGRA_IO_RAIL_HV        38
 104 #define TEGRA_IO_RAIL_DSIB      39
 105 #define TEGRA_IO_RAIL_DSIC      40
 106 #define TEGRA_IO_RAIL_DSID      41
 107 #define TEGRA_IO_RAIL_CSIE      44
 108 #define TEGRA_IO_RAIL_LVDS      57
 109 #define TEGRA_IO_RAIL_SYS_DDC   58
 110
 111 #ifdef CONFIG_ARCH_TEGRA
 112 int tegra_powergate_is_powered(unsigned int id);
 113 int tegra_powergate_power_on(unsigned int id);
 114 int tegra_powergate_power_off(unsigned int id);
 115 int tegra_powergate_remove_clamping(unsigned int id);
 116
 117 /* Must be called with clk disabled, and returns with clk enabled */
 118 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
 119                                       struct reset_control *rst);
 120
 121 int tegra_io_rail_power_on(unsigned int id);
 122 int tegra_io_rail_power_off(unsigned int id);
 123 #else
 124 static inline int tegra_powergate_is_powered(unsigned int id)
 125 {
 126         return -ENOSYS;
 127 }
 128
 129 static inline int tegra_powergate_power_on(unsigned int id)
 130 {
 131         return -ENOSYS;
 132 }
 133
 134 static inline int tegra_powergate_power_off(unsigned int id)
 135 {
 136         return -ENOSYS;
 137 }
 138
 139 static inline int tegra_powergate_remove_clamping(unsigned int id)
 140 {
 141         return -ENOSYS;
 142 }
 143
 144 static inline int tegra_powergate_sequence_power_up(unsigned int id,
 145                                                     struct clk *clk,
 146                                                     struct reset_control *rst)
 147 {
 148         return -ENOSYS;
 149 }
 150
 151 static inline int tegra_io_rail_power_on(unsigned int id)
 152 {
 153         return -ENOSYS;
 154 }
 155
 156 static inline int tegra_io_rail_power_off(unsigned int id)
 157 {
 158         return -ENOSYS;
 159 }
 160 #endif /* CONFIG_ARCH_TEGRA */
 161
 162 #endif /* __SOC_TEGRA_PMC_H__ */