include/uapi/drm/amdgpu_drm.h

   1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * Copyright 2014 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24  * OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32 #ifndef __AMDGPU_DRM_H__
  33 #define __AMDGPU_DRM_H__
  34
  35 #include "drm.h"
  36
  37 #if defined(__cplusplus)
  38 extern "C" {
  39 #endif
  40
  41 #define DRM_AMDGPU_GEM_CREATE           0x00
  42 #define DRM_AMDGPU_GEM_MMAP             0x01
  43 #define DRM_AMDGPU_CTX                  0x02
  44 #define DRM_AMDGPU_BO_LIST              0x03
  45 #define DRM_AMDGPU_CS                   0x04
  46 #define DRM_AMDGPU_INFO                 0x05
  47 #define DRM_AMDGPU_GEM_METADATA         0x06
  48 #define DRM_AMDGPU_GEM_WAIT_IDLE        0x07
  49 #define DRM_AMDGPU_GEM_VA               0x08
  50 #define DRM_AMDGPU_WAIT_CS              0x09
  51 #define DRM_AMDGPU_GEM_OP               0x10
  52 #define DRM_AMDGPU_GEM_USERPTR          0x11
  53
  54 #define DRM_IOCTL_AMDGPU_GEM_CREATE     DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
  55 #define DRM_IOCTL_AMDGPU_GEM_MMAP       DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
  56 #define DRM_IOCTL_AMDGPU_CTX            DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
  57 #define DRM_IOCTL_AMDGPU_BO_LIST        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
  58 #define DRM_IOCTL_AMDGPU_CS             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
  59 #define DRM_IOCTL_AMDGPU_INFO           DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
  60 #define DRM_IOCTL_AMDGPU_GEM_METADATA   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
  61 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
  62 #define DRM_IOCTL_AMDGPU_GEM_VA         DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
  63 #define DRM_IOCTL_AMDGPU_WAIT_CS        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
  64 #define DRM_IOCTL_AMDGPU_GEM_OP         DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
  65 #define DRM_IOCTL_AMDGPU_GEM_USERPTR    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
  66
  67 #define AMDGPU_GEM_DOMAIN_CPU           0x1
  68 #define AMDGPU_GEM_DOMAIN_GTT           0x2
  69 #define AMDGPU_GEM_DOMAIN_VRAM          0x4
  70 #define AMDGPU_GEM_DOMAIN_GDS           0x8
  71 #define AMDGPU_GEM_DOMAIN_GWS           0x10
  72 #define AMDGPU_GEM_DOMAIN_OA            0x20
  73
  74 /* Flag that CPU access will be required for the case of VRAM domain */
  75 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED   (1 << 0)
  76 /* Flag that CPU access will not work, this VRAM domain is invisible */
  77 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS         (1 << 1)
  78 /* Flag that USWC attributes should be used for GTT */
  79 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC          (1 << 2)
  80
  81 struct drm_amdgpu_gem_create_in  {
  82         /** the requested memory size */
  83         __u64 bo_size;
  84         /** physical start_addr alignment in bytes for some HW requirements */
  85         __u64 alignment;
  86         /** the requested memory domains */
  87         __u64 domains;
  88         /** allocation flags */
  89         __u64 domain_flags;
  90 };
  91
  92 struct drm_amdgpu_gem_create_out  {
  93         /** returned GEM object handle */
  94         __u32 handle;
  95         __u32 _pad;
  96 };
  97
  98 union drm_amdgpu_gem_create {
  99         struct drm_amdgpu_gem_create_in         in;
 100         struct drm_amdgpu_gem_create_out        out;
 101 };
 102
 103 /** Opcode to create new residency list.  */
 104 #define AMDGPU_BO_LIST_OP_CREATE        0
 105 /** Opcode to destroy previously created residency list */
 106 #define AMDGPU_BO_LIST_OP_DESTROY       1
 107 /** Opcode to update resource information in the list */
 108 #define AMDGPU_BO_LIST_OP_UPDATE        2
 109
 110 struct drm_amdgpu_bo_list_in {
 111         /** Type of operation */
 112         __u32 operation;
 113         /** Handle of list or 0 if we want to create one */
 114         __u32 list_handle;
 115         /** Number of BOs in list  */
 116         __u32 bo_number;
 117         /** Size of each element describing BO */
 118         __u32 bo_info_size;
 119         /** Pointer to array describing BOs */
 120         __u64 bo_info_ptr;
 121 };
 122
 123 struct drm_amdgpu_bo_list_entry {
 124         /** Handle of BO */
 125         __u32 bo_handle;
 126         /** New (if specified) BO priority to be used during migration */
 127         __u32 bo_priority;
 128 };
 129
 130 struct drm_amdgpu_bo_list_out {
 131         /** Handle of resource list  */
 132         __u32 list_handle;
 133         __u32 _pad;
 134 };
 135
 136 union drm_amdgpu_bo_list {
 137         struct drm_amdgpu_bo_list_in in;
 138         struct drm_amdgpu_bo_list_out out;
 139 };
 140
 141 /* context related */
 142 #define AMDGPU_CTX_OP_ALLOC_CTX 1
 143 #define AMDGPU_CTX_OP_FREE_CTX  2
 144 #define AMDGPU_CTX_OP_QUERY_STATE       3
 145
 146 /* GPU reset status */
 147 #define AMDGPU_CTX_NO_RESET             0
 148 /* this the context caused it */
 149 #define AMDGPU_CTX_GUILTY_RESET         1
 150 /* some other context caused it */
 151 #define AMDGPU_CTX_INNOCENT_RESET       2
 152 /* unknown cause */
 153 #define AMDGPU_CTX_UNKNOWN_RESET        3
 154
 155 struct drm_amdgpu_ctx_in {
 156         /** AMDGPU_CTX_OP_* */
 157         __u32   op;
 158         /** For future use, no flags defined so far */
 159         __u32   flags;
 160         __u32   ctx_id;
 161         __u32   _pad;
 162 };
 163
 164 union drm_amdgpu_ctx_out {
 165                 struct {
 166                         __u32   ctx_id;
 167                         __u32   _pad;
 168                 } alloc;
 169
 170                 struct {
 171                         /** For future use, no flags defined so far */
 172                         __u64   flags;
 173                         /** Number of resets caused by this context so far. */
 174                         __u32   hangs;
 175                         /** Reset status since the last call of the ioctl. */
 176                         __u32   reset_status;
 177                 } state;
 178 };
 179
 180 union drm_amdgpu_ctx {
 181         struct drm_amdgpu_ctx_in in;
 182         union drm_amdgpu_ctx_out out;
 183 };
 184
 185 /*
 186  * This is not a reliable API and you should expect it to fail for any
 187  * number of reasons and have fallback path that do not use userptr to
 188  * perform any operation.
 189  */
 190 #define AMDGPU_GEM_USERPTR_READONLY     (1 << 0)
 191 #define AMDGPU_GEM_USERPTR_ANONONLY     (1 << 1)
 192 #define AMDGPU_GEM_USERPTR_VALIDATE     (1 << 2)
 193 #define AMDGPU_GEM_USERPTR_REGISTER     (1 << 3)
 194
 195 struct drm_amdgpu_gem_userptr {
 196         __u64           addr;
 197         __u64           size;
 198         /* AMDGPU_GEM_USERPTR_* */
 199         __u32           flags;
 200         /* Resulting GEM handle */
 201         __u32           handle;
 202 };
 203
 204 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
 205 #define AMDGPU_TILING_ARRAY_MODE_SHIFT                  0
 206 #define AMDGPU_TILING_ARRAY_MODE_MASK                   0xf
 207 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT                 4
 208 #define AMDGPU_TILING_PIPE_CONFIG_MASK                  0x1f
 209 #define AMDGPU_TILING_TILE_SPLIT_SHIFT                  9
 210 #define AMDGPU_TILING_TILE_SPLIT_MASK                   0x7
 211 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT             12
 212 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK              0x7
 213 #define AMDGPU_TILING_BANK_WIDTH_SHIFT                  15
 214 #define AMDGPU_TILING_BANK_WIDTH_MASK                   0x3
 215 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT                 17
 216 #define AMDGPU_TILING_BANK_HEIGHT_MASK                  0x3
 217 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT           19
 218 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK            0x3
 219 #define AMDGPU_TILING_NUM_BANKS_SHIFT                   21
 220 #define AMDGPU_TILING_NUM_BANKS_MASK                    0x3
 221
 222 #define AMDGPU_TILING_SET(field, value) \
 223         (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 224 #define AMDGPU_TILING_GET(value, field) \
 225         (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 226
 227 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 228 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 229
 230 /** The same structure is shared for input/output */
 231 struct drm_amdgpu_gem_metadata {
 232         /** GEM Object handle */
 233         __u32   handle;
 234         /** Do we want get or set metadata */
 235         __u32   op;
 236         struct {
 237                 /** For future use, no flags defined so far */
 238                 __u64   flags;
 239                 /** family specific tiling info */
 240                 __u64   tiling_info;
 241                 __u32   data_size_bytes;
 242                 __u32   data[64];
 243         } data;
 244 };
 245
 246 struct drm_amdgpu_gem_mmap_in {
 247         /** the GEM object handle */
 248         __u32 handle;
 249         __u32 _pad;
 250 };
 251
 252 struct drm_amdgpu_gem_mmap_out {
 253         /** mmap offset from the vma offset manager */
 254         __u64 addr_ptr;
 255 };
 256
 257 union drm_amdgpu_gem_mmap {
 258         struct drm_amdgpu_gem_mmap_in   in;
 259         struct drm_amdgpu_gem_mmap_out out;
 260 };
 261
 262 struct drm_amdgpu_gem_wait_idle_in {
 263         /** GEM object handle */
 264         __u32 handle;
 265         /** For future use, no flags defined so far */
 266         __u32 flags;
 267         /** Absolute timeout to wait */
 268         __u64 timeout;
 269 };
 270
 271 struct drm_amdgpu_gem_wait_idle_out {
 272         /** BO status:  0 - BO is idle, 1 - BO is busy */
 273         __u32 status;
 274         /** Returned current memory domain */
 275         __u32 domain;
 276 };
 277
 278 union drm_amdgpu_gem_wait_idle {
 279         struct drm_amdgpu_gem_wait_idle_in  in;
 280         struct drm_amdgpu_gem_wait_idle_out out;
 281 };
 282
 283 struct drm_amdgpu_wait_cs_in {
 284         /** Command submission handle */
 285         __u64 handle;
 286         /** Absolute timeout to wait */
 287         __u64 timeout;
 288         __u32 ip_type;
 289         __u32 ip_instance;
 290         __u32 ring;
 291         __u32 ctx_id;
 292 };
 293
 294 struct drm_amdgpu_wait_cs_out {
 295         /** CS status:  0 - CS completed, 1 - CS still busy */
 296         __u64 status;
 297 };
 298
 299 union drm_amdgpu_wait_cs {
 300         struct drm_amdgpu_wait_cs_in in;
 301         struct drm_amdgpu_wait_cs_out out;
 302 };
 303
 304 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO       0
 305 #define AMDGPU_GEM_OP_SET_PLACEMENT             1
 306
 307 /* Sets or returns a value associated with a buffer. */
 308 struct drm_amdgpu_gem_op {
 309         /** GEM object handle */
 310         __u32   handle;
 311         /** AMDGPU_GEM_OP_* */
 312         __u32   op;
 313         /** Input or return value */
 314         __u64   value;
 315 };
 316
 317 #define AMDGPU_VA_OP_MAP                        1
 318 #define AMDGPU_VA_OP_UNMAP                      2
 319
 320 /* Delay the page table update till the next CS */
 321 #define AMDGPU_VM_DELAY_UPDATE          (1 << 0)
 322
 323 /* Mapping flags */
 324 /* readable mapping */
 325 #define AMDGPU_VM_PAGE_READABLE         (1 << 1)
 326 /* writable mapping */
 327 #define AMDGPU_VM_PAGE_WRITEABLE        (1 << 2)
 328 /* executable mapping, new for VI */
 329 #define AMDGPU_VM_PAGE_EXECUTABLE       (1 << 3)
 330
 331 struct drm_amdgpu_gem_va {
 332         /** GEM object handle */
 333         __u32 handle;
 334         __u32 _pad;
 335         /** AMDGPU_VA_OP_* */
 336         __u32 operation;
 337         /** AMDGPU_VM_PAGE_* */
 338         __u32 flags;
 339         /** va address to assign . Must be correctly aligned.*/
 340         __u64 va_address;
 341         /** Specify offset inside of BO to assign. Must be correctly aligned.*/
 342         __u64 offset_in_bo;
 343         /** Specify mapping size. Must be correctly aligned. */
 344         __u64 map_size;
 345 };
 346
 347 #define AMDGPU_HW_IP_GFX          0
 348 #define AMDGPU_HW_IP_COMPUTE      1
 349 #define AMDGPU_HW_IP_DMA          2
 350 #define AMDGPU_HW_IP_UVD          3
 351 #define AMDGPU_HW_IP_VCE          4
 352 #define AMDGPU_HW_IP_NUM          5
 353
 354 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 355
 356 #define AMDGPU_CHUNK_ID_IB              0x01
 357 #define AMDGPU_CHUNK_ID_FENCE           0x02
 358 #define AMDGPU_CHUNK_ID_DEPENDENCIES    0x03
 359
 360 struct drm_amdgpu_cs_chunk {
 361         __u32           chunk_id;
 362         __u32           length_dw;
 363         __u64           chunk_data;
 364 };
 365
 366 struct drm_amdgpu_cs_in {
 367         /** Rendering context id */
 368         __u32           ctx_id;
 369         /**  Handle of resource list associated with CS */
 370         __u32           bo_list_handle;
 371         __u32           num_chunks;
 372         __u32           _pad;
 373         /** this points to __u64 * which point to cs chunks */
 374         __u64           chunks;
 375 };
 376
 377 struct drm_amdgpu_cs_out {
 378         __u64 handle;
 379 };
 380
 381 union drm_amdgpu_cs {
 382         struct drm_amdgpu_cs_in in;
 383         struct drm_amdgpu_cs_out out;
 384 };
 385
 386 /* Specify flags to be used for IB */
 387
 388 /* This IB should be submitted to CE */
 389 #define AMDGPU_IB_FLAG_CE       (1<<0)
 390
 391 /* CE Preamble */
 392 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 393
 394 struct drm_amdgpu_cs_chunk_ib {
 395         __u32 _pad;
 396         /** AMDGPU_IB_FLAG_* */
 397         __u32 flags;
 398         /** Virtual address to begin IB execution */
 399         __u64 va_start;
 400         /** Size of submission */
 401         __u32 ib_bytes;
 402         /** HW IP to submit to */
 403         __u32 ip_type;
 404         /** HW IP index of the same type to submit to  */
 405         __u32 ip_instance;
 406         /** Ring index to submit to */
 407         __u32 ring;
 408 };
 409
 410 struct drm_amdgpu_cs_chunk_dep {
 411         __u32 ip_type;
 412         __u32 ip_instance;
 413         __u32 ring;
 414         __u32 ctx_id;
 415         __u64 handle;
 416 };
 417
 418 struct drm_amdgpu_cs_chunk_fence {
 419         __u32 handle;
 420         __u32 offset;
 421 };
 422
 423 struct drm_amdgpu_cs_chunk_data {
 424         union {
 425                 struct drm_amdgpu_cs_chunk_ib           ib_data;
 426                 struct drm_amdgpu_cs_chunk_fence        fence_data;
 427         };
 428 };
 429
 430 /**
 431  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
 432  *
 433  */
 434 #define AMDGPU_IDS_FLAGS_FUSION         0x1
 435
 436 /* indicate if acceleration can be working */
 437 #define AMDGPU_INFO_ACCEL_WORKING               0x00
 438 /* get the crtc_id from the mode object id? */
 439 #define AMDGPU_INFO_CRTC_FROM_ID                0x01
 440 /* query hw IP info */
 441 #define AMDGPU_INFO_HW_IP_INFO                  0x02
 442 /* query hw IP instance count for the specified type */
 443 #define AMDGPU_INFO_HW_IP_COUNT                 0x03
 444 /* timestamp for GL_ARB_timer_query */
 445 #define AMDGPU_INFO_TIMESTAMP                   0x05
 446 /* Query the firmware version */
 447 #define AMDGPU_INFO_FW_VERSION                  0x0e
 448         /* Subquery id: Query VCE firmware version */
 449         #define AMDGPU_INFO_FW_VCE              0x1
 450         /* Subquery id: Query UVD firmware version */
 451         #define AMDGPU_INFO_FW_UVD              0x2
 452         /* Subquery id: Query GMC firmware version */
 453         #define AMDGPU_INFO_FW_GMC              0x03
 454         /* Subquery id: Query GFX ME firmware version */
 455         #define AMDGPU_INFO_FW_GFX_ME           0x04
 456         /* Subquery id: Query GFX PFP firmware version */
 457         #define AMDGPU_INFO_FW_GFX_PFP          0x05
 458         /* Subquery id: Query GFX CE firmware version */
 459         #define AMDGPU_INFO_FW_GFX_CE           0x06
 460         /* Subquery id: Query GFX RLC firmware version */
 461         #define AMDGPU_INFO_FW_GFX_RLC          0x07
 462         /* Subquery id: Query GFX MEC firmware version */
 463         #define AMDGPU_INFO_FW_GFX_MEC          0x08
 464         /* Subquery id: Query SMC firmware version */
 465         #define AMDGPU_INFO_FW_SMC              0x0a
 466         /* Subquery id: Query SDMA firmware version */
 467         #define AMDGPU_INFO_FW_SDMA             0x0b
 468 /* number of bytes moved for TTM migration */
 469 #define AMDGPU_INFO_NUM_BYTES_MOVED             0x0f
 470 /* the used VRAM size */
 471 #define AMDGPU_INFO_VRAM_USAGE                  0x10
 472 /* the used GTT size */
 473 #define AMDGPU_INFO_GTT_USAGE                   0x11
 474 /* Information about GDS, etc. resource configuration */
 475 #define AMDGPU_INFO_GDS_CONFIG                  0x13
 476 /* Query information about VRAM and GTT domains */
 477 #define AMDGPU_INFO_VRAM_GTT                    0x14
 478 /* Query information about register in MMR address space*/
 479 #define AMDGPU_INFO_READ_MMR_REG                0x15
 480 /* Query information about device: rev id, family, etc. */
 481 #define AMDGPU_INFO_DEV_INFO                    0x16
 482 /* visible vram usage */
 483 #define AMDGPU_INFO_VIS_VRAM_USAGE              0x17
 484
 485 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT  0
 486 #define AMDGPU_INFO_MMR_SE_INDEX_MASK   0xff
 487 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT  8
 488 #define AMDGPU_INFO_MMR_SH_INDEX_MASK   0xff
 489
 490 struct drm_amdgpu_query_fw {
 491         /** AMDGPU_INFO_FW_* */
 492         __u32 fw_type;
 493         /**
 494          * Index of the IP if there are more IPs of
 495          * the same type.
 496          */
 497         __u32 ip_instance;
 498         /**
 499          * Index of the engine. Whether this is used depends
 500          * on the firmware type. (e.g. MEC, SDMA)
 501          */
 502         __u32 index;
 503         __u32 _pad;
 504 };
 505
 506 /* Input structure for the INFO ioctl */
 507 struct drm_amdgpu_info {
 508         /* Where the return value will be stored */
 509         __u64 return_pointer;
 510         /* The size of the return value. Just like "size" in "snprintf",
 511          * it limits how many bytes the kernel can write. */
 512         __u32 return_size;
 513         /* The query request id. */
 514         __u32 query;
 515
 516         union {
 517                 struct {
 518                         __u32 id;
 519                         __u32 _pad;
 520                 } mode_crtc;
 521
 522                 struct {
 523                         /** AMDGPU_HW_IP_* */
 524                         __u32 type;
 525                         /**
 526                          * Index of the IP if there are more IPs of the same
 527                          * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
 528                          */
 529                         __u32 ip_instance;
 530                 } query_hw_ip;
 531
 532                 struct {
 533                         __u32 dword_offset;
 534                         /** number of registers to read */
 535                         __u32 count;
 536                         __u32 instance;
 537                         /** For future use, no flags defined so far */
 538                         __u32 flags;
 539                 } read_mmr_reg;
 540
 541                 struct drm_amdgpu_query_fw query_fw;
 542         };
 543 };
 544
 545 struct drm_amdgpu_info_gds {
 546         /** GDS GFX partition size */
 547         __u32 gds_gfx_partition_size;
 548         /** GDS compute partition size */
 549         __u32 compute_partition_size;
 550         /** total GDS memory size */
 551         __u32 gds_total_size;
 552         /** GWS size per GFX partition */
 553         __u32 gws_per_gfx_partition;
 554         /** GSW size per compute partition */
 555         __u32 gws_per_compute_partition;
 556         /** OA size per GFX partition */
 557         __u32 oa_per_gfx_partition;
 558         /** OA size per compute partition */
 559         __u32 oa_per_compute_partition;
 560         __u32 _pad;
 561 };
 562
 563 struct drm_amdgpu_info_vram_gtt {
 564         __u64 vram_size;
 565         __u64 vram_cpu_accessible_size;
 566         __u64 gtt_size;
 567 };
 568
 569 struct drm_amdgpu_info_firmware {
 570         __u32 ver;
 571         __u32 feature;
 572 };
 573
 574 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
 575 #define AMDGPU_VRAM_TYPE_GDDR1 1
 576 #define AMDGPU_VRAM_TYPE_DDR2  2
 577 #define AMDGPU_VRAM_TYPE_GDDR3 3
 578 #define AMDGPU_VRAM_TYPE_GDDR4 4
 579 #define AMDGPU_VRAM_TYPE_GDDR5 5
 580 #define AMDGPU_VRAM_TYPE_HBM   6
 581 #define AMDGPU_VRAM_TYPE_DDR3  7
 582
 583 struct drm_amdgpu_info_device {
 584         /** PCI Device ID */
 585         __u32 device_id;
 586         /** Internal chip revision: A0, A1, etc.) */
 587         __u32 chip_rev;
 588         __u32 external_rev;
 589         /** Revision id in PCI Config space */
 590         __u32 pci_rev;
 591         __u32 family;
 592         __u32 num_shader_engines;
 593         __u32 num_shader_arrays_per_engine;
 594         /* in KHz */
 595         __u32 gpu_counter_freq;
 596         __u64 max_engine_clock;
 597         __u64 max_memory_clock;
 598         /* cu information */
 599         __u32 cu_active_number;
 600         __u32 cu_ao_mask;
 601         __u32 cu_bitmap[4][4];
 602         /** Render backend pipe mask. One render backend is CB+DB. */
 603         __u32 enabled_rb_pipes_mask;
 604         __u32 num_rb_pipes;
 605         __u32 num_hw_gfx_contexts;
 606         __u32 _pad;
 607         __u64 ids_flags;
 608         /** Starting virtual address for UMDs. */
 609         __u64 virtual_address_offset;
 610         /** The maximum virtual address */
 611         __u64 virtual_address_max;
 612         /** Required alignment of virtual addresses. */
 613         __u32 virtual_address_alignment;
 614         /** Page table entry - fragment size */
 615         __u32 pte_fragment_size;
 616         __u32 gart_page_size;
 617         /** constant engine ram size*/
 618         __u32 ce_ram_size;
 619         /** video memory type info*/
 620         __u32 vram_type;
 621         /** video memory bit width*/
 622         __u32 vram_bit_width;
 623         /* vce harvesting instance */
 624         __u32 vce_harvest_config;
 625 };
 626
 627 struct drm_amdgpu_info_hw_ip {
 628         /** Version of h/w IP */
 629         __u32  hw_ip_version_major;
 630         __u32  hw_ip_version_minor;
 631         /** Capabilities */
 632         __u64  capabilities_flags;
 633         /** command buffer address start alignment*/
 634         __u32  ib_start_alignment;
 635         /** command buffer size alignment*/
 636         __u32  ib_size_alignment;
 637         /** Bitmask of available rings. Bit 0 means ring 0, etc. */
 638         __u32  available_rings;
 639         __u32  _pad;
 640 };
 641
 642 /*
 643  * Supported GPU families
 644  */
 645 #define AMDGPU_FAMILY_UNKNOWN                   0
 646 #define AMDGPU_FAMILY_CI                        120 /* Bonaire, Hawaii */
 647 #define AMDGPU_FAMILY_KV                        125 /* Kaveri, Kabini, Mullins */
 648 #define AMDGPU_FAMILY_VI                        130 /* Iceland, Tonga */
 649 #define AMDGPU_FAMILY_CZ                        135 /* Carrizo, Stoney */
 650
 651 #if defined(__cplusplus)
 652 }
 653 #endif
 654
 655 #endif