drm/nouveau/gem: allow user-space to specify an object should be coherent
[deliverable/linux.git] / include / uapi / drm / nouveau_drm.h
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
27
28 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000
29
30 /* reserved object handles when using deprecated object APIs - these
31 * are here so that libdrm can allow interoperability with the new
32 * object APIs
33 */
34 #define NOUVEAU_ABI16_CLIENT 0xffffffff
35 #define NOUVEAU_ABI16_DEVICE 0xdddddddd
36 #define NOUVEAU_ABI16_CHAN(n) (0xcccc0000 | (n))
37
38 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
39 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
40 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
41 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
42 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
43
44 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
45 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
46 #define NOUVEAU_GEM_TILE_16BPP 0x00000001
47 #define NOUVEAU_GEM_TILE_32BPP 0x00000002
48 #define NOUVEAU_GEM_TILE_ZETA 0x00000004
49 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
50
51 struct drm_nouveau_gem_info {
52 uint32_t handle;
53 uint32_t domain;
54 uint64_t size;
55 uint64_t offset;
56 uint64_t map_handle;
57 uint32_t tile_mode;
58 uint32_t tile_flags;
59 };
60
61 struct drm_nouveau_gem_new {
62 struct drm_nouveau_gem_info info;
63 uint32_t channel_hint;
64 uint32_t align;
65 };
66
67 #define NOUVEAU_GEM_MAX_BUFFERS 1024
68 struct drm_nouveau_gem_pushbuf_bo_presumed {
69 uint32_t valid;
70 uint32_t domain;
71 uint64_t offset;
72 };
73
74 struct drm_nouveau_gem_pushbuf_bo {
75 uint64_t user_priv;
76 uint32_t handle;
77 uint32_t read_domains;
78 uint32_t write_domains;
79 uint32_t valid_domains;
80 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
81 };
82
83 #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
84 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
85 #define NOUVEAU_GEM_RELOC_OR (1 << 2)
86 #define NOUVEAU_GEM_MAX_RELOCS 1024
87 struct drm_nouveau_gem_pushbuf_reloc {
88 uint32_t reloc_bo_index;
89 uint32_t reloc_bo_offset;
90 uint32_t bo_index;
91 uint32_t flags;
92 uint32_t data;
93 uint32_t vor;
94 uint32_t tor;
95 };
96
97 #define NOUVEAU_GEM_MAX_PUSH 512
98 struct drm_nouveau_gem_pushbuf_push {
99 uint32_t bo_index;
100 uint32_t pad;
101 uint64_t offset;
102 uint64_t length;
103 };
104
105 struct drm_nouveau_gem_pushbuf {
106 uint32_t channel;
107 uint32_t nr_buffers;
108 uint64_t buffers;
109 uint32_t nr_relocs;
110 uint32_t nr_push;
111 uint64_t relocs;
112 uint64_t push;
113 uint32_t suffix0;
114 uint32_t suffix1;
115 uint64_t vram_available;
116 uint64_t gart_available;
117 };
118
119 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
120 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
121 struct drm_nouveau_gem_cpu_prep {
122 uint32_t handle;
123 uint32_t flags;
124 };
125
126 struct drm_nouveau_gem_cpu_fini {
127 uint32_t handle;
128 };
129
130 #define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
131 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
132 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
133 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
134 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
135 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
136 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
137 #define DRM_NOUVEAU_NVIF 0x07
138 #define DRM_NOUVEAU_GEM_NEW 0x40
139 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
140 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42
141 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43
142 #define DRM_NOUVEAU_GEM_INFO 0x44
143
144 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
145 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
146 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
147 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
148 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
149
150 #endif /* __NOUVEAU_DRM_H__ */
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