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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / include / video / omapdss.h
1 /*
2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
20
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
25
26 #include <video/videomode.h>
27
28 #define DISPC_IRQ_FRAMEDONE (1 << 0)
29 #define DISPC_IRQ_VSYNC (1 << 1)
30 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
31 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
32 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
33 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
34 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
35 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
36 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
37 #define DISPC_IRQ_OCP_ERR (1 << 9)
38 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
39 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
40 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
41 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
42 #define DISPC_IRQ_SYNC_LOST (1 << 14)
43 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
44 #define DISPC_IRQ_WAKEUP (1 << 16)
45 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
46 #define DISPC_IRQ_VSYNC2 (1 << 18)
47 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
48 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
49 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
50 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
51 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
52 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
53 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
54 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
55 #define DISPC_IRQ_VSYNC3 (1 << 28)
56 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
57 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
58
59 struct omap_dss_device;
60 struct omap_overlay_manager;
61 struct dss_lcd_mgr_config;
62 struct snd_aes_iec958;
63 struct snd_cea_861_aud_if;
64 struct hdmi_avi_infoframe;
65
66 enum omap_display_type {
67 OMAP_DISPLAY_TYPE_NONE = 0,
68 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
69 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
70 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
71 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
72 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
73 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
74 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
75 };
76
77 enum omap_plane {
78 OMAP_DSS_GFX = 0,
79 OMAP_DSS_VIDEO1 = 1,
80 OMAP_DSS_VIDEO2 = 2,
81 OMAP_DSS_VIDEO3 = 3,
82 OMAP_DSS_WB = 4,
83 };
84
85 enum omap_channel {
86 OMAP_DSS_CHANNEL_LCD = 0,
87 OMAP_DSS_CHANNEL_DIGIT = 1,
88 OMAP_DSS_CHANNEL_LCD2 = 2,
89 OMAP_DSS_CHANNEL_LCD3 = 3,
90 };
91
92 enum omap_color_mode {
93 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
94 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
95 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
96 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
97 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
98 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
99 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
100 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
101 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
102 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
103 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
104 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
105 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
106 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
107 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
108 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
109 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
110 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
111 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
112 };
113
114 enum omap_dss_load_mode {
115 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
116 OMAP_DSS_LOAD_CLUT_ONLY = 1,
117 OMAP_DSS_LOAD_FRAME_ONLY = 2,
118 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
119 };
120
121 enum omap_dss_trans_key_type {
122 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
123 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
124 };
125
126 enum omap_rfbi_te_mode {
127 OMAP_DSS_RFBI_TE_MODE_1 = 1,
128 OMAP_DSS_RFBI_TE_MODE_2 = 2,
129 };
130
131 enum omap_dss_signal_level {
132 OMAPDSS_SIG_ACTIVE_HIGH = 0,
133 OMAPDSS_SIG_ACTIVE_LOW = 1,
134 };
135
136 enum omap_dss_signal_edge {
137 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
138 OMAPDSS_DRIVE_SIG_RISING_EDGE,
139 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
140 };
141
142 enum omap_dss_venc_type {
143 OMAP_DSS_VENC_TYPE_COMPOSITE,
144 OMAP_DSS_VENC_TYPE_SVIDEO,
145 };
146
147 enum omap_dss_dsi_pixel_format {
148 OMAP_DSS_DSI_FMT_RGB888,
149 OMAP_DSS_DSI_FMT_RGB666,
150 OMAP_DSS_DSI_FMT_RGB666_PACKED,
151 OMAP_DSS_DSI_FMT_RGB565,
152 };
153
154 enum omap_dss_dsi_mode {
155 OMAP_DSS_DSI_CMD_MODE = 0,
156 OMAP_DSS_DSI_VIDEO_MODE,
157 };
158
159 enum omap_display_caps {
160 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
161 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
162 };
163
164 enum omap_dss_display_state {
165 OMAP_DSS_DISPLAY_DISABLED = 0,
166 OMAP_DSS_DISPLAY_ACTIVE,
167 };
168
169 struct omap_dss_audio {
170 struct snd_aes_iec958 *iec;
171 struct snd_cea_861_aud_if *cea;
172 };
173
174 enum omap_dss_rotation_type {
175 OMAP_DSS_ROT_DMA = 1 << 0,
176 OMAP_DSS_ROT_VRFB = 1 << 1,
177 OMAP_DSS_ROT_TILER = 1 << 2,
178 };
179
180 /* clockwise rotation angle */
181 enum omap_dss_rotation_angle {
182 OMAP_DSS_ROT_0 = 0,
183 OMAP_DSS_ROT_90 = 1,
184 OMAP_DSS_ROT_180 = 2,
185 OMAP_DSS_ROT_270 = 3,
186 };
187
188 enum omap_overlay_caps {
189 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
190 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
191 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
192 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
193 OMAP_DSS_OVL_CAP_POS = 1 << 4,
194 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
195 };
196
197 enum omap_overlay_manager_caps {
198 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
199 };
200
201 enum omap_dss_clk_source {
202 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
203 * OMAP4: DSS_FCLK */
204 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
205 * OMAP4: PLL1_CLK1 */
206 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
207 * OMAP4: PLL1_CLK2 */
208 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
209 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
210 };
211
212 enum omap_hdmi_flags {
213 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
214 };
215
216 enum omap_dss_output_id {
217 OMAP_DSS_OUTPUT_DPI = 1 << 0,
218 OMAP_DSS_OUTPUT_DBI = 1 << 1,
219 OMAP_DSS_OUTPUT_SDI = 1 << 2,
220 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
221 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
222 OMAP_DSS_OUTPUT_VENC = 1 << 5,
223 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
224 };
225
226 /* RFBI */
227
228 struct rfbi_timings {
229 int cs_on_time;
230 int cs_off_time;
231 int we_on_time;
232 int we_off_time;
233 int re_on_time;
234 int re_off_time;
235 int we_cycle_time;
236 int re_cycle_time;
237 int cs_pulse_width;
238 int access_time;
239
240 int clk_div;
241
242 u32 tim[5]; /* set by rfbi_convert_timings() */
243
244 int converted;
245 };
246
247 /* DSI */
248
249 enum omap_dss_dsi_trans_mode {
250 /* Sync Pulses: both sync start and end packets sent */
251 OMAP_DSS_DSI_PULSE_MODE,
252 /* Sync Events: only sync start packets sent */
253 OMAP_DSS_DSI_EVENT_MODE,
254 /* Burst: only sync start packets sent, pixels are time compressed */
255 OMAP_DSS_DSI_BURST_MODE,
256 };
257
258 struct omap_dss_dsi_videomode_timings {
259 unsigned long hsclk;
260
261 unsigned ndl;
262 unsigned bitspp;
263
264 /* pixels */
265 u16 hact;
266 /* lines */
267 u16 vact;
268
269 /* DSI video mode blanking data */
270 /* Unit: byte clock cycles */
271 u16 hss;
272 u16 hsa;
273 u16 hse;
274 u16 hfp;
275 u16 hbp;
276 /* Unit: line clocks */
277 u16 vsa;
278 u16 vfp;
279 u16 vbp;
280
281 /* DSI blanking modes */
282 int blanking_mode;
283 int hsa_blanking_mode;
284 int hbp_blanking_mode;
285 int hfp_blanking_mode;
286
287 enum omap_dss_dsi_trans_mode trans_mode;
288
289 bool ddr_clk_always_on;
290 int window_sync;
291 };
292
293 struct omap_dss_dsi_config {
294 enum omap_dss_dsi_mode mode;
295 enum omap_dss_dsi_pixel_format pixel_format;
296 const struct omap_video_timings *timings;
297
298 unsigned long hs_clk_min, hs_clk_max;
299 unsigned long lp_clk_min, lp_clk_max;
300
301 bool ddr_clk_always_on;
302 enum omap_dss_dsi_trans_mode trans_mode;
303 };
304
305 enum omapdss_version {
306 OMAPDSS_VER_UNKNOWN = 0,
307 OMAPDSS_VER_OMAP24xx,
308 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
309 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
310 OMAPDSS_VER_OMAP3630,
311 OMAPDSS_VER_AM35xx,
312 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
313 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
314 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
315 OMAPDSS_VER_OMAP5,
316 OMAPDSS_VER_AM43xx,
317 OMAPDSS_VER_DRA7xx,
318 };
319
320 /* Board specific data */
321 struct omap_dss_board_info {
322 int num_devices;
323 struct omap_dss_device **devices;
324 struct omap_dss_device *default_device;
325 const char *default_display_name;
326 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
327 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
328 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
329 enum omapdss_version version;
330 };
331
332 /* Init with the board info */
333 extern int omap_display_init(struct omap_dss_board_info *board_data);
334 /* HDMI mux init*/
335 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
336
337 struct omap_video_timings {
338 /* Unit: pixels */
339 u16 x_res;
340 /* Unit: pixels */
341 u16 y_res;
342 /* Unit: Hz */
343 u32 pixelclock;
344 /* Unit: pixel clocks */
345 u16 hsw; /* Horizontal synchronization pulse width */
346 /* Unit: pixel clocks */
347 u16 hfp; /* Horizontal front porch */
348 /* Unit: pixel clocks */
349 u16 hbp; /* Horizontal back porch */
350 /* Unit: line clocks */
351 u16 vsw; /* Vertical synchronization pulse width */
352 /* Unit: line clocks */
353 u16 vfp; /* Vertical front porch */
354 /* Unit: line clocks */
355 u16 vbp; /* Vertical back porch */
356
357 /* Vsync logic level */
358 enum omap_dss_signal_level vsync_level;
359 /* Hsync logic level */
360 enum omap_dss_signal_level hsync_level;
361 /* Interlaced or Progressive timings */
362 bool interlace;
363 /* Pixel clock edge to drive LCD data */
364 enum omap_dss_signal_edge data_pclk_edge;
365 /* Data enable logic level */
366 enum omap_dss_signal_level de_level;
367 /* Pixel clock edges to drive HSYNC and VSYNC signals */
368 enum omap_dss_signal_edge sync_pclk_edge;
369 };
370
371 #ifdef CONFIG_OMAP2_DSS_VENC
372 /* Hardcoded timings for tv modes. Venc only uses these to
373 * identify the mode, and does not actually use the configs
374 * itself. However, the configs should be something that
375 * a normal monitor can also show */
376 extern const struct omap_video_timings omap_dss_pal_timings;
377 extern const struct omap_video_timings omap_dss_ntsc_timings;
378 #endif
379
380 struct omap_dss_cpr_coefs {
381 s16 rr, rg, rb;
382 s16 gr, gg, gb;
383 s16 br, bg, bb;
384 };
385
386 struct omap_overlay_info {
387 dma_addr_t paddr;
388 dma_addr_t p_uv_addr; /* for NV12 format */
389 u16 screen_width;
390 u16 width;
391 u16 height;
392 enum omap_color_mode color_mode;
393 u8 rotation;
394 enum omap_dss_rotation_type rotation_type;
395 bool mirror;
396
397 u16 pos_x;
398 u16 pos_y;
399 u16 out_width; /* if 0, out_width == width */
400 u16 out_height; /* if 0, out_height == height */
401 u8 global_alpha;
402 u8 pre_mult_alpha;
403 u8 zorder;
404 };
405
406 struct omap_overlay {
407 struct kobject kobj;
408 struct list_head list;
409
410 /* static fields */
411 const char *name;
412 enum omap_plane id;
413 enum omap_color_mode supported_modes;
414 enum omap_overlay_caps caps;
415
416 /* dynamic fields */
417 struct omap_overlay_manager *manager;
418
419 /*
420 * The following functions do not block:
421 *
422 * is_enabled
423 * set_overlay_info
424 * get_overlay_info
425 *
426 * The rest of the functions may block and cannot be called from
427 * interrupt context
428 */
429
430 int (*enable)(struct omap_overlay *ovl);
431 int (*disable)(struct omap_overlay *ovl);
432 bool (*is_enabled)(struct omap_overlay *ovl);
433
434 int (*set_manager)(struct omap_overlay *ovl,
435 struct omap_overlay_manager *mgr);
436 int (*unset_manager)(struct omap_overlay *ovl);
437
438 int (*set_overlay_info)(struct omap_overlay *ovl,
439 struct omap_overlay_info *info);
440 void (*get_overlay_info)(struct omap_overlay *ovl,
441 struct omap_overlay_info *info);
442
443 int (*wait_for_go)(struct omap_overlay *ovl);
444
445 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
446 };
447
448 struct omap_overlay_manager_info {
449 u32 default_color;
450
451 enum omap_dss_trans_key_type trans_key_type;
452 u32 trans_key;
453 bool trans_enabled;
454
455 bool partial_alpha_enabled;
456
457 bool cpr_enable;
458 struct omap_dss_cpr_coefs cpr_coefs;
459 };
460
461 struct omap_overlay_manager {
462 struct kobject kobj;
463
464 /* static fields */
465 const char *name;
466 enum omap_channel id;
467 enum omap_overlay_manager_caps caps;
468 struct list_head overlays;
469 enum omap_display_type supported_displays;
470 enum omap_dss_output_id supported_outputs;
471
472 /* dynamic fields */
473 struct omap_dss_device *output;
474
475 /*
476 * The following functions do not block:
477 *
478 * set_manager_info
479 * get_manager_info
480 * apply
481 *
482 * The rest of the functions may block and cannot be called from
483 * interrupt context
484 */
485
486 int (*set_output)(struct omap_overlay_manager *mgr,
487 struct omap_dss_device *output);
488 int (*unset_output)(struct omap_overlay_manager *mgr);
489
490 int (*set_manager_info)(struct omap_overlay_manager *mgr,
491 struct omap_overlay_manager_info *info);
492 void (*get_manager_info)(struct omap_overlay_manager *mgr,
493 struct omap_overlay_manager_info *info);
494
495 int (*apply)(struct omap_overlay_manager *mgr);
496 int (*wait_for_go)(struct omap_overlay_manager *mgr);
497 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
498
499 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
500 };
501
502 /* 22 pins means 1 clk lane and 10 data lanes */
503 #define OMAP_DSS_MAX_DSI_PINS 22
504
505 struct omap_dsi_pin_config {
506 int num_pins;
507 /*
508 * pin numbers in the following order:
509 * clk+, clk-
510 * data1+, data1-
511 * data2+, data2-
512 * ...
513 */
514 int pins[OMAP_DSS_MAX_DSI_PINS];
515 };
516
517 struct omap_dss_writeback_info {
518 u32 paddr;
519 u32 p_uv_addr;
520 u16 buf_width;
521 u16 width;
522 u16 height;
523 enum omap_color_mode color_mode;
524 u8 rotation;
525 enum omap_dss_rotation_type rotation_type;
526 bool mirror;
527 u8 pre_mult_alpha;
528 };
529
530 struct omapdss_dpi_ops {
531 int (*connect)(struct omap_dss_device *dssdev,
532 struct omap_dss_device *dst);
533 void (*disconnect)(struct omap_dss_device *dssdev,
534 struct omap_dss_device *dst);
535
536 int (*enable)(struct omap_dss_device *dssdev);
537 void (*disable)(struct omap_dss_device *dssdev);
538
539 int (*check_timings)(struct omap_dss_device *dssdev,
540 struct omap_video_timings *timings);
541 void (*set_timings)(struct omap_dss_device *dssdev,
542 struct omap_video_timings *timings);
543 void (*get_timings)(struct omap_dss_device *dssdev,
544 struct omap_video_timings *timings);
545
546 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
547 };
548
549 struct omapdss_sdi_ops {
550 int (*connect)(struct omap_dss_device *dssdev,
551 struct omap_dss_device *dst);
552 void (*disconnect)(struct omap_dss_device *dssdev,
553 struct omap_dss_device *dst);
554
555 int (*enable)(struct omap_dss_device *dssdev);
556 void (*disable)(struct omap_dss_device *dssdev);
557
558 int (*check_timings)(struct omap_dss_device *dssdev,
559 struct omap_video_timings *timings);
560 void (*set_timings)(struct omap_dss_device *dssdev,
561 struct omap_video_timings *timings);
562 void (*get_timings)(struct omap_dss_device *dssdev,
563 struct omap_video_timings *timings);
564
565 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
566 };
567
568 struct omapdss_dvi_ops {
569 int (*connect)(struct omap_dss_device *dssdev,
570 struct omap_dss_device *dst);
571 void (*disconnect)(struct omap_dss_device *dssdev,
572 struct omap_dss_device *dst);
573
574 int (*enable)(struct omap_dss_device *dssdev);
575 void (*disable)(struct omap_dss_device *dssdev);
576
577 int (*check_timings)(struct omap_dss_device *dssdev,
578 struct omap_video_timings *timings);
579 void (*set_timings)(struct omap_dss_device *dssdev,
580 struct omap_video_timings *timings);
581 void (*get_timings)(struct omap_dss_device *dssdev,
582 struct omap_video_timings *timings);
583 };
584
585 struct omapdss_atv_ops {
586 int (*connect)(struct omap_dss_device *dssdev,
587 struct omap_dss_device *dst);
588 void (*disconnect)(struct omap_dss_device *dssdev,
589 struct omap_dss_device *dst);
590
591 int (*enable)(struct omap_dss_device *dssdev);
592 void (*disable)(struct omap_dss_device *dssdev);
593
594 int (*check_timings)(struct omap_dss_device *dssdev,
595 struct omap_video_timings *timings);
596 void (*set_timings)(struct omap_dss_device *dssdev,
597 struct omap_video_timings *timings);
598 void (*get_timings)(struct omap_dss_device *dssdev,
599 struct omap_video_timings *timings);
600
601 void (*set_type)(struct omap_dss_device *dssdev,
602 enum omap_dss_venc_type type);
603 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
604 bool invert_polarity);
605
606 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
607 u32 (*get_wss)(struct omap_dss_device *dssdev);
608 };
609
610 struct omapdss_hdmi_ops {
611 int (*connect)(struct omap_dss_device *dssdev,
612 struct omap_dss_device *dst);
613 void (*disconnect)(struct omap_dss_device *dssdev,
614 struct omap_dss_device *dst);
615
616 int (*enable)(struct omap_dss_device *dssdev);
617 void (*disable)(struct omap_dss_device *dssdev);
618
619 int (*check_timings)(struct omap_dss_device *dssdev,
620 struct omap_video_timings *timings);
621 void (*set_timings)(struct omap_dss_device *dssdev,
622 struct omap_video_timings *timings);
623 void (*get_timings)(struct omap_dss_device *dssdev,
624 struct omap_video_timings *timings);
625
626 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
627 bool (*detect)(struct omap_dss_device *dssdev);
628
629 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
630 int (*set_infoframe)(struct omap_dss_device *dssdev,
631 const struct hdmi_avi_infoframe *avi);
632 };
633
634 struct omapdss_dsi_ops {
635 int (*connect)(struct omap_dss_device *dssdev,
636 struct omap_dss_device *dst);
637 void (*disconnect)(struct omap_dss_device *dssdev,
638 struct omap_dss_device *dst);
639
640 int (*enable)(struct omap_dss_device *dssdev);
641 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
642 bool enter_ulps);
643
644 /* bus configuration */
645 int (*set_config)(struct omap_dss_device *dssdev,
646 const struct omap_dss_dsi_config *cfg);
647 int (*configure_pins)(struct omap_dss_device *dssdev,
648 const struct omap_dsi_pin_config *pin_cfg);
649
650 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
651 bool enable);
652 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
653
654 int (*update)(struct omap_dss_device *dssdev, int channel,
655 void (*callback)(int, void *), void *data);
656
657 void (*bus_lock)(struct omap_dss_device *dssdev);
658 void (*bus_unlock)(struct omap_dss_device *dssdev);
659
660 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
661 void (*disable_video_output)(struct omap_dss_device *dssdev,
662 int channel);
663
664 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
665 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
666 int vc_id);
667 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
668
669 /* data transfer */
670 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
671 u8 *data, int len);
672 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
673 u8 *data, int len);
674 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
675 u8 *data, int len);
676
677 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
678 u8 *data, int len);
679 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
680 u8 *data, int len);
681 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
682 u8 *reqdata, int reqlen,
683 u8 *data, int len);
684
685 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
686
687 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
688 int channel, u16 plen);
689 };
690
691 struct omap_dss_device {
692 struct kobject kobj;
693 struct device *dev;
694
695 struct module *owner;
696
697 struct list_head panel_list;
698
699 /* alias in the form of "display%d" */
700 char alias[16];
701
702 enum omap_display_type type;
703 enum omap_display_type output_type;
704
705 union {
706 struct {
707 u8 data_lines;
708 } dpi;
709
710 struct {
711 u8 channel;
712 u8 data_lines;
713 } rfbi;
714
715 struct {
716 u8 datapairs;
717 } sdi;
718
719 struct {
720 int module;
721 } dsi;
722
723 struct {
724 enum omap_dss_venc_type type;
725 bool invert_polarity;
726 } venc;
727 } phy;
728
729 struct {
730 struct omap_video_timings timings;
731
732 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
733 enum omap_dss_dsi_mode dsi_mode;
734 } panel;
735
736 struct {
737 u8 pixel_size;
738 struct rfbi_timings rfbi_timings;
739 } ctrl;
740
741 const char *name;
742
743 /* used to match device to driver */
744 const char *driver_name;
745
746 void *data;
747
748 struct omap_dss_driver *driver;
749
750 union {
751 const struct omapdss_dpi_ops *dpi;
752 const struct omapdss_sdi_ops *sdi;
753 const struct omapdss_dvi_ops *dvi;
754 const struct omapdss_hdmi_ops *hdmi;
755 const struct omapdss_atv_ops *atv;
756 const struct omapdss_dsi_ops *dsi;
757 } ops;
758
759 /* helper variable for driver suspend/resume */
760 bool activate_after_resume;
761
762 enum omap_display_caps caps;
763
764 struct omap_dss_device *src;
765
766 enum omap_dss_display_state state;
767
768 /* OMAP DSS output specific fields */
769
770 struct list_head list;
771
772 /* DISPC channel for this output */
773 enum omap_channel dispc_channel;
774
775 /* output instance */
776 enum omap_dss_output_id id;
777
778 /* the port number in the DT node */
779 int port_num;
780
781 /* dynamic fields */
782 struct omap_overlay_manager *manager;
783
784 struct omap_dss_device *dst;
785 };
786
787 struct omap_dss_hdmi_data
788 {
789 int ct_cp_hpd_gpio;
790 int ls_oe_gpio;
791 int hpd_gpio;
792 };
793
794 struct omap_dss_driver {
795 int (*probe)(struct omap_dss_device *);
796 void (*remove)(struct omap_dss_device *);
797
798 int (*connect)(struct omap_dss_device *dssdev);
799 void (*disconnect)(struct omap_dss_device *dssdev);
800
801 int (*enable)(struct omap_dss_device *display);
802 void (*disable)(struct omap_dss_device *display);
803 int (*run_test)(struct omap_dss_device *display, int test);
804
805 int (*update)(struct omap_dss_device *dssdev,
806 u16 x, u16 y, u16 w, u16 h);
807 int (*sync)(struct omap_dss_device *dssdev);
808
809 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
810 int (*get_te)(struct omap_dss_device *dssdev);
811
812 u8 (*get_rotate)(struct omap_dss_device *dssdev);
813 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
814
815 bool (*get_mirror)(struct omap_dss_device *dssdev);
816 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
817
818 int (*memory_read)(struct omap_dss_device *dssdev,
819 void *buf, size_t size,
820 u16 x, u16 y, u16 w, u16 h);
821
822 void (*get_resolution)(struct omap_dss_device *dssdev,
823 u16 *xres, u16 *yres);
824 void (*get_dimensions)(struct omap_dss_device *dssdev,
825 u32 *width, u32 *height);
826 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
827
828 int (*check_timings)(struct omap_dss_device *dssdev,
829 struct omap_video_timings *timings);
830 void (*set_timings)(struct omap_dss_device *dssdev,
831 struct omap_video_timings *timings);
832 void (*get_timings)(struct omap_dss_device *dssdev,
833 struct omap_video_timings *timings);
834
835 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
836 u32 (*get_wss)(struct omap_dss_device *dssdev);
837
838 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
839 bool (*detect)(struct omap_dss_device *dssdev);
840
841 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
842 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
843 const struct hdmi_avi_infoframe *avi);
844 };
845
846 enum omapdss_version omapdss_get_version(void);
847 bool omapdss_is_initialized(void);
848
849 int omap_dss_register_driver(struct omap_dss_driver *);
850 void omap_dss_unregister_driver(struct omap_dss_driver *);
851
852 int omapdss_register_display(struct omap_dss_device *dssdev);
853 void omapdss_unregister_display(struct omap_dss_device *dssdev);
854
855 struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
856 void omap_dss_put_device(struct omap_dss_device *dssdev);
857 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
858 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
859 struct omap_dss_device *omap_dss_find_device(void *data,
860 int (*match)(struct omap_dss_device *dssdev, void *data));
861 const char *omapdss_get_default_display_name(void);
862
863 void videomode_to_omap_video_timings(const struct videomode *vm,
864 struct omap_video_timings *ovt);
865 void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
866 struct videomode *vm);
867
868 int dss_feat_get_num_mgrs(void);
869 int dss_feat_get_num_ovls(void);
870 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
871 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
872 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
873
874
875
876 int omap_dss_get_num_overlay_managers(void);
877 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
878
879 int omap_dss_get_num_overlays(void);
880 struct omap_overlay *omap_dss_get_overlay(int num);
881
882 int omapdss_register_output(struct omap_dss_device *output);
883 void omapdss_unregister_output(struct omap_dss_device *output);
884 struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
885 struct omap_dss_device *omap_dss_find_output(const char *name);
886 struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
887 int omapdss_output_set_device(struct omap_dss_device *out,
888 struct omap_dss_device *dssdev);
889 int omapdss_output_unset_device(struct omap_dss_device *out);
890
891 struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
892 struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
893
894 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
895 u16 *xres, u16 *yres);
896 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
897 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
898 struct omap_video_timings *timings);
899
900 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
901 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
902 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
903
904 u32 dispc_read_irqstatus(void);
905 void dispc_clear_irqstatus(u32 mask);
906 u32 dispc_read_irqenable(void);
907 void dispc_write_irqenable(u32 mask);
908
909 int dispc_request_irq(irq_handler_t handler, void *dev_id);
910 void dispc_free_irq(void *dev_id);
911
912 int dispc_runtime_get(void);
913 void dispc_runtime_put(void);
914
915 void dispc_mgr_enable(enum omap_channel channel, bool enable);
916 bool dispc_mgr_is_enabled(enum omap_channel channel);
917 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
918 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
919 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
920 bool dispc_mgr_go_busy(enum omap_channel channel);
921 void dispc_mgr_go(enum omap_channel channel);
922 void dispc_mgr_set_lcd_config(enum omap_channel channel,
923 const struct dss_lcd_mgr_config *config);
924 void dispc_mgr_set_timings(enum omap_channel channel,
925 const struct omap_video_timings *timings);
926 void dispc_mgr_setup(enum omap_channel channel,
927 const struct omap_overlay_manager_info *info);
928
929 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
930 const struct omap_overlay_info *oi,
931 const struct omap_video_timings *timings,
932 int *x_predecim, int *y_predecim);
933
934 int dispc_ovl_enable(enum omap_plane plane, bool enable);
935 bool dispc_ovl_enabled(enum omap_plane plane);
936 void dispc_ovl_set_channel_out(enum omap_plane plane,
937 enum omap_channel channel);
938 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
939 bool replication, const struct omap_video_timings *mgr_timings,
940 bool mem_to_mem);
941
942 int omapdss_compat_init(void);
943 void omapdss_compat_uninit(void);
944
945 struct dss_mgr_ops {
946 int (*connect)(struct omap_overlay_manager *mgr,
947 struct omap_dss_device *dst);
948 void (*disconnect)(struct omap_overlay_manager *mgr,
949 struct omap_dss_device *dst);
950
951 void (*start_update)(struct omap_overlay_manager *mgr);
952 int (*enable)(struct omap_overlay_manager *mgr);
953 void (*disable)(struct omap_overlay_manager *mgr);
954 void (*set_timings)(struct omap_overlay_manager *mgr,
955 const struct omap_video_timings *timings);
956 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
957 const struct dss_lcd_mgr_config *config);
958 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
959 void (*handler)(void *), void *data);
960 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
961 void (*handler)(void *), void *data);
962 };
963
964 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
965 void dss_uninstall_mgr_ops(void);
966
967 int dss_mgr_connect(struct omap_overlay_manager *mgr,
968 struct omap_dss_device *dst);
969 void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
970 struct omap_dss_device *dst);
971 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
972 const struct omap_video_timings *timings);
973 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
974 const struct dss_lcd_mgr_config *config);
975 int dss_mgr_enable(struct omap_overlay_manager *mgr);
976 void dss_mgr_disable(struct omap_overlay_manager *mgr);
977 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
978 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
979 void (*handler)(void *), void *data);
980 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
981 void (*handler)(void *), void *data);
982
983 static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
984 {
985 return dssdev->src;
986 }
987
988 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
989 {
990 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
991 }
992
993 struct device_node *
994 omapdss_of_get_next_port(const struct device_node *parent,
995 struct device_node *prev);
996
997 struct device_node *
998 omapdss_of_get_next_endpoint(const struct device_node *parent,
999 struct device_node *prev);
1000
1001 struct device_node *
1002 omapdss_of_get_first_endpoint(const struct device_node *parent);
1003
1004 struct omap_dss_device *
1005 omapdss_of_find_source_for_first_ep(struct device_node *node);
1006
1007 #endif
Linux kernel - Deliverables
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