kernel/irq/generic-chip.c

   1 /*
   2  * Library implementing the most common irq chip callback functions
   3  *
   4  * Copyright (C) 2011, Thomas Gleixner
   5  */
   6 #include <linux/io.h>
   7 #include <linux/irq.h>
   8 #include <linux/slab.h>
   9 #include <linux/export.h>
  10 #include <linux/irqdomain.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/syscore_ops.h>
  14
  15 #include "internals.h"
  16
  17 static LIST_HEAD(gc_list);
  18 static DEFINE_RAW_SPINLOCK(gc_lock);
  19
  20 /**
  21  * irq_gc_noop - NOOP function
  22  * @d: irq_data
  23  */
  24 void irq_gc_noop(struct irq_data *d)
  25 {
  26 }
  27
  28 /**
  29  * irq_gc_mask_disable_reg - Mask chip via disable register
  30  * @d: irq_data
  31  *
  32  * Chip has separate enable/disable registers instead of a single mask
  33  * register.
  34  */
  35 void irq_gc_mask_disable_reg(struct irq_data *d)
  36 {
  37         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  38         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  39         u32 mask = d->mask;
  40
  41         irq_gc_lock(gc);
  42         irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
  43         *ct->mask_cache &= ~mask;
  44         irq_gc_unlock(gc);
  45 }
  46
  47 /**
  48  * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
  49  * @d: irq_data
  50  *
  51  * Chip has a single mask register. Values of this register are cached
  52  * and protected by gc->lock
  53  */
  54 void irq_gc_mask_set_bit(struct irq_data *d)
  55 {
  56         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  57         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  58         u32 mask = d->mask;
  59
  60         irq_gc_lock(gc);
  61         *ct->mask_cache |= mask;
  62         irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
  63         irq_gc_unlock(gc);
  64 }
  65
  66 /**
  67  * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
  68  * @d: irq_data
  69  *
  70  * Chip has a single mask register. Values of this register are cached
  71  * and protected by gc->lock
  72  */
  73 void irq_gc_mask_clr_bit(struct irq_data *d)
  74 {
  75         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  76         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  77         u32 mask = d->mask;
  78
  79         irq_gc_lock(gc);
  80         *ct->mask_cache &= ~mask;
  81         irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
  82         irq_gc_unlock(gc);
  83 }
  84
  85 /**
  86  * irq_gc_unmask_enable_reg - Unmask chip via enable register
  87  * @d: irq_data
  88  *
  89  * Chip has separate enable/disable registers instead of a single mask
  90  * register.
  91  */
  92 void irq_gc_unmask_enable_reg(struct irq_data *d)
  93 {
  94         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  95         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  96         u32 mask = d->mask;
  97
  98         irq_gc_lock(gc);
  99         irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
 100         *ct->mask_cache |= mask;
 101         irq_gc_unlock(gc);
 102 }
 103
 104 /**
 105  * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
 106  * @d: irq_data
 107  */
 108 void irq_gc_ack_set_bit(struct irq_data *d)
 109 {
 110         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 111         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 112         u32 mask = d->mask;
 113
 114         irq_gc_lock(gc);
 115         irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
 116         irq_gc_unlock(gc);
 117 }
 118
 119 /**
 120  * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
 121  * @d: irq_data
 122  */
 123 void irq_gc_ack_clr_bit(struct irq_data *d)
 124 {
 125         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 126         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 127         u32 mask = ~d->mask;
 128
 129         irq_gc_lock(gc);
 130         irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
 131         irq_gc_unlock(gc);
 132 }
 133
 134 /**
 135  * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
 136  * @d: irq_data
 137  */
 138 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
 139 {
 140         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 141         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 142         u32 mask = d->mask;
 143
 144         irq_gc_lock(gc);
 145         irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
 146         irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
 147         irq_gc_unlock(gc);
 148 }
 149
 150 /**
 151  * irq_gc_eoi - EOI interrupt
 152  * @d: irq_data
 153  */
 154 void irq_gc_eoi(struct irq_data *d)
 155 {
 156         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 157         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 158         u32 mask = d->mask;
 159
 160         irq_gc_lock(gc);
 161         irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
 162         irq_gc_unlock(gc);
 163 }
 164
 165 /**
 166  * irq_gc_set_wake - Set/clr wake bit for an interrupt
 167  * @d: irq_data
 168  *
 169  * For chips where the wake from suspend functionality is not
 170  * configured in a separate register and the wakeup active state is
 171  * just stored in a bitmask.
 172  */
 173 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
 174 {
 175         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 176         u32 mask = d->mask;
 177
 178         if (!(mask & gc->wake_enabled))
 179                 return -EINVAL;
 180
 181         irq_gc_lock(gc);
 182         if (on)
 183                 gc->wake_active |= mask;
 184         else
 185                 gc->wake_active &= ~mask;
 186         irq_gc_unlock(gc);
 187         return 0;
 188 }
 189
 190 static void
 191 irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
 192                       int num_ct, unsigned int irq_base,
 193                       void __iomem *reg_base, irq_flow_handler_t handler)
 194 {
 195         raw_spin_lock_init(&gc->lock);
 196         gc->num_ct = num_ct;
 197         gc->irq_base = irq_base;
 198         gc->reg_base = reg_base;
 199         gc->chip_types->chip.name = name;
 200         gc->chip_types->handler = handler;
 201 }
 202
 203 /**
 204  * irq_alloc_generic_chip - Allocate a generic chip and initialize it
 205  * @name:       Name of the irq chip
 206  * @num_ct:     Number of irq_chip_type instances associated with this
 207  * @irq_base:   Interrupt base nr for this chip
 208  * @reg_base:   Register base address (virtual)
 209  * @handler:    Default flow handler associated with this chip
 210  *
 211  * Returns an initialized irq_chip_generic structure. The chip defaults
 212  * to the primary (index 0) irq_chip_type and @handler
 213  */
 214 struct irq_chip_generic *
 215 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
 216                        void __iomem *reg_base, irq_flow_handler_t handler)
 217 {
 218         struct irq_chip_generic *gc;
 219         unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 220
 221         gc = kzalloc(sz, GFP_KERNEL);
 222         if (gc) {
 223                 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
 224                                       handler);
 225         }
 226         return gc;
 227 }
 228 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
 229
 230 static void
 231 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
 232 {
 233         struct irq_chip_type *ct = gc->chip_types;
 234         u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
 235         int i;
 236
 237         for (i = 0; i < gc->num_ct; i++) {
 238                 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
 239                         mskptr = &ct[i].mask_cache_priv;
 240                         mskreg = ct[i].regs.mask;
 241                 }
 242                 ct[i].mask_cache = mskptr;
 243                 if (flags & IRQ_GC_INIT_MASK_CACHE)
 244                         *mskptr = irq_reg_readl(gc->reg_base + mskreg);
 245         }
 246 }
 247
 248 /**
 249  * irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
 250  * @d:                  irq domain for which to allocate chips
 251  * @irqs_per_chip:      Number of interrupts each chip handles
 252  * @num_ct:             Number of irq_chip_type instances associated with this
 253  * @name:               Name of the irq chip
 254  * @handler:            Default flow handler associated with these chips
 255  * @clr:                IRQ_* bits to clear in the mapping function
 256  * @set:                IRQ_* bits to set in the mapping function
 257  */
 258 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
 259                                    int num_ct, const char *name,
 260                                    irq_flow_handler_t handler,
 261                                    unsigned int clr, unsigned int set,
 262                                    enum irq_gc_flags gcflags)
 263 {
 264         struct irq_domain_chip_generic *dgc;
 265         struct irq_chip_generic *gc;
 266         int numchips, sz, i;
 267         unsigned long flags;
 268         void *tmp;
 269
 270         if (d->gc)
 271                 return -EBUSY;
 272
 273         numchips = d->revmap_size / irqs_per_chip;
 274         if (!numchips)
 275                 return -EINVAL;
 276
 277         /* Allocate a pointer, generic chip and chiptypes for each chip */
 278         sz = sizeof(*dgc) + numchips * sizeof(gc);
 279         sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
 280
 281         tmp = dgc = kzalloc(sz, GFP_KERNEL);
 282         if (!dgc)
 283                 return -ENOMEM;
 284         dgc->irqs_per_chip = irqs_per_chip;
 285         dgc->num_chips = numchips;
 286         dgc->irq_flags_to_set = set;
 287         dgc->irq_flags_to_clear = clr;
 288         dgc->gc_flags = gcflags;
 289         d->gc = dgc;
 290
 291         /* Calc pointer to the first generic chip */
 292         tmp += sizeof(*dgc) + numchips * sizeof(gc);
 293         for (i = 0; i < numchips; i++) {
 294                 /* Store the pointer to the generic chip */
 295                 dgc->gc[i] = gc = tmp;
 296                 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
 297                                       NULL, handler);
 298                 gc->domain = d;
 299                 raw_spin_lock_irqsave(&gc_lock, flags);
 300                 list_add_tail(&gc->list, &gc_list);
 301                 raw_spin_unlock_irqrestore(&gc_lock, flags);
 302                 /* Calc pointer to the next generic chip */
 303                 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 304         }
 305         d->name = name;
 306         return 0;
 307 }
 308 EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips);
 309
 310 /**
 311  * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
 312  * @d:                  irq domain pointer
 313  * @hw_irq:             Hardware interrupt number
 314  */
 315 struct irq_chip_generic *
 316 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
 317 {
 318         struct irq_domain_chip_generic *dgc = d->gc;
 319         int idx;
 320
 321         if (!dgc)
 322                 return NULL;
 323         idx = hw_irq / dgc->irqs_per_chip;
 324         if (idx >= dgc->num_chips)
 325                 return NULL;
 326         return dgc->gc[idx];
 327 }
 328 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
 329
 330 /*
 331  * Separate lockdep class for interrupt chip which can nest irq_desc
 332  * lock.
 333  */
 334 static struct lock_class_key irq_nested_lock_class;
 335
 336 /**
 337  * irq_map_generic_chip - Map a generic chip for an irq domain
 338  */
 339 static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
 340                                 irq_hw_number_t hw_irq)
 341 {
 342         struct irq_data *data = irq_get_irq_data(virq);
 343         struct irq_domain_chip_generic *dgc = d->gc;
 344         struct irq_chip_generic *gc;
 345         struct irq_chip_type *ct;
 346         struct irq_chip *chip;
 347         unsigned long flags;
 348         int idx;
 349
 350         if (!d->gc)
 351                 return -ENODEV;
 352
 353         idx = hw_irq / dgc->irqs_per_chip;
 354         if (idx >= dgc->num_chips)
 355                 return -EINVAL;
 356         gc = dgc->gc[idx];
 357
 358         idx = hw_irq % dgc->irqs_per_chip;
 359
 360         if (test_bit(idx, &gc->unused))
 361                 return -ENOTSUPP;
 362
 363         if (test_bit(idx, &gc->installed))
 364                 return -EBUSY;
 365
 366         ct = gc->chip_types;
 367         chip = &ct->chip;
 368
 369         /* We only init the cache for the first mapping of a generic chip */
 370         if (!gc->installed) {
 371                 raw_spin_lock_irqsave(&gc->lock, flags);
 372                 irq_gc_init_mask_cache(gc, dgc->gc_flags);
 373                 raw_spin_unlock_irqrestore(&gc->lock, flags);
 374         }
 375
 376         /* Mark the interrupt as installed */
 377         set_bit(idx, &gc->installed);
 378
 379         if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
 380                 irq_set_lockdep_class(virq, &irq_nested_lock_class);
 381
 382         if (chip->irq_calc_mask)
 383                 chip->irq_calc_mask(data);
 384         else
 385                 data->mask = 1 << idx;
 386
 387         irq_set_chip_and_handler(virq, chip, ct->handler);
 388         irq_set_chip_data(virq, gc);
 389         irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
 390         return 0;
 391 }
 392
 393 struct irq_domain_ops irq_generic_chip_ops = {
 394         .map    = irq_map_generic_chip,
 395         .xlate  = irq_domain_xlate_onetwocell,
 396 };
 397 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
 398
 399 /**
 400  * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
 401  * @gc:         Generic irq chip holding all data
 402  * @msk:        Bitmask holding the irqs to initialize relative to gc->irq_base
 403  * @flags:      Flags for initialization
 404  * @clr:        IRQ_* bits to clear
 405  * @set:        IRQ_* bits to set
 406  *
 407  * Set up max. 32 interrupts starting from gc->irq_base. Note, this
 408  * initializes all interrupts to the primary irq_chip_type and its
 409  * associated handler.
 410  */
 411 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
 412                             enum irq_gc_flags flags, unsigned int clr,
 413                             unsigned int set)
 414 {
 415         struct irq_chip_type *ct = gc->chip_types;
 416         struct irq_chip *chip = &ct->chip;
 417         unsigned int i;
 418
 419         raw_spin_lock(&gc_lock);
 420         list_add_tail(&gc->list, &gc_list);
 421         raw_spin_unlock(&gc_lock);
 422
 423         irq_gc_init_mask_cache(gc, flags);
 424
 425         for (i = gc->irq_base; msk; msk >>= 1, i++) {
 426                 if (!(msk & 0x01))
 427                         continue;
 428
 429                 if (flags & IRQ_GC_INIT_NESTED_LOCK)
 430                         irq_set_lockdep_class(i, &irq_nested_lock_class);
 431
 432                 if (!(flags & IRQ_GC_NO_MASK)) {
 433                         struct irq_data *d = irq_get_irq_data(i);
 434
 435                         if (chip->irq_calc_mask)
 436                                 chip->irq_calc_mask(d);
 437                         else
 438                                 d->mask = 1 << (i - gc->irq_base);
 439                 }
 440                 irq_set_chip_and_handler(i, chip, ct->handler);
 441                 irq_set_chip_data(i, gc);
 442                 irq_modify_status(i, clr, set);
 443         }
 444         gc->irq_cnt = i - gc->irq_base;
 445 }
 446 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
 447
 448 /**
 449  * irq_setup_alt_chip - Switch to alternative chip
 450  * @d:          irq_data for this interrupt
 451  * @type        Flow type to be initialized
 452  *
 453  * Only to be called from chip->irq_set_type() callbacks.
 454  */
 455 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
 456 {
 457         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 458         struct irq_chip_type *ct = gc->chip_types;
 459         unsigned int i;
 460
 461         for (i = 0; i < gc->num_ct; i++, ct++) {
 462                 if (ct->type & type) {
 463                         d->chip = &ct->chip;
 464                         irq_data_to_desc(d)->handle_irq = ct->handler;
 465                         return 0;
 466                 }
 467         }
 468         return -EINVAL;
 469 }
 470 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
 471
 472 /**
 473  * irq_remove_generic_chip - Remove a chip
 474  * @gc:         Generic irq chip holding all data
 475  * @msk:        Bitmask holding the irqs to initialize relative to gc->irq_base
 476  * @clr:        IRQ_* bits to clear
 477  * @set:        IRQ_* bits to set
 478  *
 479  * Remove up to 32 interrupts starting from gc->irq_base.
 480  */
 481 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
 482                              unsigned int clr, unsigned int set)
 483 {
 484         unsigned int i = gc->irq_base;
 485
 486         raw_spin_lock(&gc_lock);
 487         list_del(&gc->list);
 488         raw_spin_unlock(&gc_lock);
 489
 490         for (; msk; msk >>= 1, i++) {
 491                 if (!(msk & 0x01))
 492                         continue;
 493
 494                 /* Remove handler first. That will mask the irq line */
 495                 irq_set_handler(i, NULL);
 496                 irq_set_chip(i, &no_irq_chip);
 497                 irq_set_chip_data(i, NULL);
 498                 irq_modify_status(i, clr, set);
 499         }
 500 }
 501 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
 502
 503 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
 504 {
 505         unsigned int virq;
 506
 507         if (!gc->domain)
 508                 return irq_get_irq_data(gc->irq_base);
 509
 510         /*
 511          * We don't know which of the irqs has been actually
 512          * installed. Use the first one.
 513          */
 514         if (!gc->installed)
 515                 return NULL;
 516
 517         virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
 518         return virq ? irq_get_irq_data(virq) : NULL;
 519 }
 520
 521 #ifdef CONFIG_PM
 522 static int irq_gc_suspend(void)
 523 {
 524         struct irq_chip_generic *gc;
 525
 526         list_for_each_entry(gc, &gc_list, list) {
 527                 struct irq_chip_type *ct = gc->chip_types;
 528
 529                 if (ct->chip.irq_suspend) {
 530                         struct irq_data *data = irq_gc_get_irq_data(gc);
 531
 532                         if (data)
 533                                 ct->chip.irq_suspend(data);
 534                 }
 535         }
 536         return 0;
 537 }
 538
 539 static void irq_gc_resume(void)
 540 {
 541         struct irq_chip_generic *gc;
 542
 543         list_for_each_entry(gc, &gc_list, list) {
 544                 struct irq_chip_type *ct = gc->chip_types;
 545
 546                 if (ct->chip.irq_resume) {
 547                         struct irq_data *data = irq_gc_get_irq_data(gc);
 548
 549                         if (data)
 550                                 ct->chip.irq_resume(data);
 551                 }
 552         }
 553 }
 554 #else
 555 #define irq_gc_suspend NULL
 556 #define irq_gc_resume NULL
 557 #endif
 558
 559 static void irq_gc_shutdown(void)
 560 {
 561         struct irq_chip_generic *gc;
 562
 563         list_for_each_entry(gc, &gc_list, list) {
 564                 struct irq_chip_type *ct = gc->chip_types;
 565
 566                 if (ct->chip.irq_pm_shutdown) {
 567                         struct irq_data *data = irq_gc_get_irq_data(gc);
 568
 569                         if (data)
 570                                 ct->chip.irq_pm_shutdown(data);
 571                 }
 572         }
 573 }
 574
 575 static struct syscore_ops irq_gc_syscore_ops = {
 576         .suspend = irq_gc_suspend,
 577         .resume = irq_gc_resume,
 578         .shutdown = irq_gc_shutdown,
 579 };
 580
 581 static int __init irq_gc_init_ops(void)
 582 {
 583         register_syscore_ops(&irq_gc_syscore_ops);
 584         return 0;
 585 }
 586 device_initcall(irq_gc_init_ops);