kernel/irq/generic-chip.c

   1 /*
   2  * Library implementing the most common irq chip callback functions
   3  *
   4  * Copyright (C) 2011, Thomas Gleixner
   5  */
   6 #include <linux/io.h>
   7 #include <linux/irq.h>
   8 #include <linux/slab.h>
   9 #include <linux/export.h>
  10 #include <linux/irqdomain.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/syscore_ops.h>
  14
  15 #include "internals.h"
  16
  17 static LIST_HEAD(gc_list);
  18 static DEFINE_RAW_SPINLOCK(gc_lock);
  19
  20 /**
  21  * irq_gc_noop - NOOP function
  22  * @d: irq_data
  23  */
  24 void irq_gc_noop(struct irq_data *d)
  25 {
  26 }
  27
  28 /**
  29  * irq_gc_mask_disable_reg - Mask chip via disable register
  30  * @d: irq_data
  31  *
  32  * Chip has separate enable/disable registers instead of a single mask
  33  * register.
  34  */
  35 void irq_gc_mask_disable_reg(struct irq_data *d)
  36 {
  37         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  38         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  39         u32 mask = d->mask;
  40
  41         irq_gc_lock(gc);
  42         irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
  43         *ct->mask_cache &= ~mask;
  44         irq_gc_unlock(gc);
  45 }
  46
  47 /**
  48  * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
  49  * @d: irq_data
  50  *
  51  * Chip has a single mask register. Values of this register are cached
  52  * and protected by gc->lock
  53  */
  54 void irq_gc_mask_set_bit(struct irq_data *d)
  55 {
  56         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  57         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  58         u32 mask = d->mask;
  59
  60         irq_gc_lock(gc);
  61         *ct->mask_cache |= mask;
  62         irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
  63         irq_gc_unlock(gc);
  64 }
  65 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
  66
  67 /**
  68  * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
  69  * @d: irq_data
  70  *
  71  * Chip has a single mask register. Values of this register are cached
  72  * and protected by gc->lock
  73  */
  74 void irq_gc_mask_clr_bit(struct irq_data *d)
  75 {
  76         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  77         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  78         u32 mask = d->mask;
  79
  80         irq_gc_lock(gc);
  81         *ct->mask_cache &= ~mask;
  82         irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
  83         irq_gc_unlock(gc);
  84 }
  85 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
  86
  87 /**
  88  * irq_gc_unmask_enable_reg - Unmask chip via enable register
  89  * @d: irq_data
  90  *
  91  * Chip has separate enable/disable registers instead of a single mask
  92  * register.
  93  */
  94 void irq_gc_unmask_enable_reg(struct irq_data *d)
  95 {
  96         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  97         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  98         u32 mask = d->mask;
  99
 100         irq_gc_lock(gc);
 101         irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
 102         *ct->mask_cache |= mask;
 103         irq_gc_unlock(gc);
 104 }
 105
 106 /**
 107  * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
 108  * @d: irq_data
 109  */
 110 void irq_gc_ack_set_bit(struct irq_data *d)
 111 {
 112         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 113         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 114         u32 mask = d->mask;
 115
 116         irq_gc_lock(gc);
 117         irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
 118         irq_gc_unlock(gc);
 119 }
 120 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
 121
 122 /**
 123  * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
 124  * @d: irq_data
 125  */
 126 void irq_gc_ack_clr_bit(struct irq_data *d)
 127 {
 128         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 129         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 130         u32 mask = ~d->mask;
 131
 132         irq_gc_lock(gc);
 133         irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
 134         irq_gc_unlock(gc);
 135 }
 136
 137 /**
 138  * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
 139  * @d: irq_data
 140  */
 141 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
 142 {
 143         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 144         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 145         u32 mask = d->mask;
 146
 147         irq_gc_lock(gc);
 148         irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
 149         irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
 150         irq_gc_unlock(gc);
 151 }
 152
 153 /**
 154  * irq_gc_eoi - EOI interrupt
 155  * @d: irq_data
 156  */
 157 void irq_gc_eoi(struct irq_data *d)
 158 {
 159         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 160         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 161         u32 mask = d->mask;
 162
 163         irq_gc_lock(gc);
 164         irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
 165         irq_gc_unlock(gc);
 166 }
 167
 168 /**
 169  * irq_gc_set_wake - Set/clr wake bit for an interrupt
 170  * @d:  irq_data
 171  * @on: Indicates whether the wake bit should be set or cleared
 172  *
 173  * For chips where the wake from suspend functionality is not
 174  * configured in a separate register and the wakeup active state is
 175  * just stored in a bitmask.
 176  */
 177 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
 178 {
 179         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 180         u32 mask = d->mask;
 181
 182         if (!(mask & gc->wake_enabled))
 183                 return -EINVAL;
 184
 185         irq_gc_lock(gc);
 186         if (on)
 187                 gc->wake_active |= mask;
 188         else
 189                 gc->wake_active &= ~mask;
 190         irq_gc_unlock(gc);
 191         return 0;
 192 }
 193
 194 static void
 195 irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
 196                       int num_ct, unsigned int irq_base,
 197                       void __iomem *reg_base, irq_flow_handler_t handler)
 198 {
 199         raw_spin_lock_init(&gc->lock);
 200         gc->num_ct = num_ct;
 201         gc->irq_base = irq_base;
 202         gc->reg_base = reg_base;
 203         gc->chip_types->chip.name = name;
 204         gc->chip_types->handler = handler;
 205 }
 206
 207 /**
 208  * irq_alloc_generic_chip - Allocate a generic chip and initialize it
 209  * @name:       Name of the irq chip
 210  * @num_ct:     Number of irq_chip_type instances associated with this
 211  * @irq_base:   Interrupt base nr for this chip
 212  * @reg_base:   Register base address (virtual)
 213  * @handler:    Default flow handler associated with this chip
 214  *
 215  * Returns an initialized irq_chip_generic structure. The chip defaults
 216  * to the primary (index 0) irq_chip_type and @handler
 217  */
 218 struct irq_chip_generic *
 219 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
 220                        void __iomem *reg_base, irq_flow_handler_t handler)
 221 {
 222         struct irq_chip_generic *gc;
 223         unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 224
 225         gc = kzalloc(sz, GFP_KERNEL);
 226         if (gc) {
 227                 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
 228                                       handler);
 229         }
 230         return gc;
 231 }
 232 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
 233
 234 static void
 235 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
 236 {
 237         struct irq_chip_type *ct = gc->chip_types;
 238         u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
 239         int i;
 240
 241         for (i = 0; i < gc->num_ct; i++) {
 242                 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
 243                         mskptr = &ct[i].mask_cache_priv;
 244                         mskreg = ct[i].regs.mask;
 245                 }
 246                 ct[i].mask_cache = mskptr;
 247                 if (flags & IRQ_GC_INIT_MASK_CACHE)
 248                         *mskptr = irq_reg_readl(gc->reg_base + mskreg);
 249         }
 250 }
 251
 252 /**
 253  * irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
 254  * @d:                  irq domain for which to allocate chips
 255  * @irqs_per_chip:      Number of interrupts each chip handles
 256  * @num_ct:             Number of irq_chip_type instances associated with this
 257  * @name:               Name of the irq chip
 258  * @handler:            Default flow handler associated with these chips
 259  * @clr:                IRQ_* bits to clear in the mapping function
 260  * @set:                IRQ_* bits to set in the mapping function
 261  * @gcflags:            Generic chip specific setup flags
 262  */
 263 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
 264                                    int num_ct, const char *name,
 265                                    irq_flow_handler_t handler,
 266                                    unsigned int clr, unsigned int set,
 267                                    enum irq_gc_flags gcflags)
 268 {
 269         struct irq_domain_chip_generic *dgc;
 270         struct irq_chip_generic *gc;
 271         int numchips, sz, i;
 272         unsigned long flags;
 273         void *tmp;
 274
 275         if (d->gc)
 276                 return -EBUSY;
 277
 278         if (d->revmap_type != IRQ_DOMAIN_MAP_LINEAR)
 279                 return -EINVAL;
 280
 281         numchips = d->revmap_data.linear.size / irqs_per_chip;
 282         if (!numchips)
 283                 return -EINVAL;
 284
 285         /* Allocate a pointer, generic chip and chiptypes for each chip */
 286         sz = sizeof(*dgc) + numchips * sizeof(gc);
 287         sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
 288
 289         tmp = dgc = kzalloc(sz, GFP_KERNEL);
 290         if (!dgc)
 291                 return -ENOMEM;
 292         dgc->irqs_per_chip = irqs_per_chip;
 293         dgc->num_chips = numchips;
 294         dgc->irq_flags_to_set = set;
 295         dgc->irq_flags_to_clear = clr;
 296         dgc->gc_flags = gcflags;
 297         d->gc = dgc;
 298
 299         /* Calc pointer to the first generic chip */
 300         tmp += sizeof(*dgc) + numchips * sizeof(gc);
 301         for (i = 0; i < numchips; i++) {
 302                 /* Store the pointer to the generic chip */
 303                 dgc->gc[i] = gc = tmp;
 304                 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
 305                                       NULL, handler);
 306                 gc->domain = d;
 307                 raw_spin_lock_irqsave(&gc_lock, flags);
 308                 list_add_tail(&gc->list, &gc_list);
 309                 raw_spin_unlock_irqrestore(&gc_lock, flags);
 310                 /* Calc pointer to the next generic chip */
 311                 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 312         }
 313         return 0;
 314 }
 315 EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips);
 316
 317 /**
 318  * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
 319  * @d:                  irq domain pointer
 320  * @hw_irq:             Hardware interrupt number
 321  */
 322 struct irq_chip_generic *
 323 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
 324 {
 325         struct irq_domain_chip_generic *dgc = d->gc;
 326         int idx;
 327
 328         if (!dgc)
 329                 return NULL;
 330         idx = hw_irq / dgc->irqs_per_chip;
 331         if (idx >= dgc->num_chips)
 332                 return NULL;
 333         return dgc->gc[idx];
 334 }
 335 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
 336
 337 /*
 338  * Separate lockdep class for interrupt chip which can nest irq_desc
 339  * lock.
 340  */
 341 static struct lock_class_key irq_nested_lock_class;
 342
 343 /*
 344  * irq_map_generic_chip - Map a generic chip for an irq domain
 345  */
 346 static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
 347                                 irq_hw_number_t hw_irq)
 348 {
 349         struct irq_data *data = irq_get_irq_data(virq);
 350         struct irq_domain_chip_generic *dgc = d->gc;
 351         struct irq_chip_generic *gc;
 352         struct irq_chip_type *ct;
 353         struct irq_chip *chip;
 354         unsigned long flags;
 355         int idx;
 356
 357         if (!d->gc)
 358                 return -ENODEV;
 359
 360         idx = hw_irq / dgc->irqs_per_chip;
 361         if (idx >= dgc->num_chips)
 362                 return -EINVAL;
 363         gc = dgc->gc[idx];
 364
 365         idx = hw_irq % dgc->irqs_per_chip;
 366
 367         if (test_bit(idx, &gc->unused))
 368                 return -ENOTSUPP;
 369
 370         if (test_bit(idx, &gc->installed))
 371                 return -EBUSY;
 372
 373         ct = gc->chip_types;
 374         chip = &ct->chip;
 375
 376         /* We only init the cache for the first mapping of a generic chip */
 377         if (!gc->installed) {
 378                 raw_spin_lock_irqsave(&gc->lock, flags);
 379                 irq_gc_init_mask_cache(gc, dgc->gc_flags);
 380                 raw_spin_unlock_irqrestore(&gc->lock, flags);
 381         }
 382
 383         /* Mark the interrupt as installed */
 384         set_bit(idx, &gc->installed);
 385
 386         if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
 387                 irq_set_lockdep_class(virq, &irq_nested_lock_class);
 388
 389         if (chip->irq_calc_mask)
 390                 chip->irq_calc_mask(data);
 391         else
 392                 data->mask = 1 << idx;
 393
 394         irq_set_chip_and_handler(virq, chip, ct->handler);
 395         irq_set_chip_data(virq, gc);
 396         irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
 397         return 0;
 398 }
 399
 400 struct irq_domain_ops irq_generic_chip_ops = {
 401         .map    = irq_map_generic_chip,
 402         .xlate  = irq_domain_xlate_onetwocell,
 403 };
 404 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
 405
 406 /**
 407  * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
 408  * @gc:         Generic irq chip holding all data
 409  * @msk:        Bitmask holding the irqs to initialize relative to gc->irq_base
 410  * @flags:      Flags for initialization
 411  * @clr:        IRQ_* bits to clear
 412  * @set:        IRQ_* bits to set
 413  *
 414  * Set up max. 32 interrupts starting from gc->irq_base. Note, this
 415  * initializes all interrupts to the primary irq_chip_type and its
 416  * associated handler.
 417  */
 418 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
 419                             enum irq_gc_flags flags, unsigned int clr,
 420                             unsigned int set)
 421 {
 422         struct irq_chip_type *ct = gc->chip_types;
 423         struct irq_chip *chip = &ct->chip;
 424         unsigned int i;
 425
 426         raw_spin_lock(&gc_lock);
 427         list_add_tail(&gc->list, &gc_list);
 428         raw_spin_unlock(&gc_lock);
 429
 430         irq_gc_init_mask_cache(gc, flags);
 431
 432         for (i = gc->irq_base; msk; msk >>= 1, i++) {
 433                 if (!(msk & 0x01))
 434                         continue;
 435
 436                 if (flags & IRQ_GC_INIT_NESTED_LOCK)
 437                         irq_set_lockdep_class(i, &irq_nested_lock_class);
 438
 439                 if (!(flags & IRQ_GC_NO_MASK)) {
 440                         struct irq_data *d = irq_get_irq_data(i);
 441
 442                         if (chip->irq_calc_mask)
 443                                 chip->irq_calc_mask(d);
 444                         else
 445                                 d->mask = 1 << (i - gc->irq_base);
 446                 }
 447                 irq_set_chip_and_handler(i, chip, ct->handler);
 448                 irq_set_chip_data(i, gc);
 449                 irq_modify_status(i, clr, set);
 450         }
 451         gc->irq_cnt = i - gc->irq_base;
 452 }
 453 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
 454
 455 /**
 456  * irq_setup_alt_chip - Switch to alternative chip
 457  * @d:          irq_data for this interrupt
 458  * @type:       Flow type to be initialized
 459  *
 460  * Only to be called from chip->irq_set_type() callbacks.
 461  */
 462 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
 463 {
 464         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 465         struct irq_chip_type *ct = gc->chip_types;
 466         unsigned int i;
 467
 468         for (i = 0; i < gc->num_ct; i++, ct++) {
 469                 if (ct->type & type) {
 470                         d->chip = &ct->chip;
 471                         irq_data_to_desc(d)->handle_irq = ct->handler;
 472                         return 0;
 473                 }
 474         }
 475         return -EINVAL;
 476 }
 477 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
 478
 479 /**
 480  * irq_remove_generic_chip - Remove a chip
 481  * @gc:         Generic irq chip holding all data
 482  * @msk:        Bitmask holding the irqs to initialize relative to gc->irq_base
 483  * @clr:        IRQ_* bits to clear
 484  * @set:        IRQ_* bits to set
 485  *
 486  * Remove up to 32 interrupts starting from gc->irq_base.
 487  */
 488 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
 489                              unsigned int clr, unsigned int set)
 490 {
 491         unsigned int i = gc->irq_base;
 492
 493         raw_spin_lock(&gc_lock);
 494         list_del(&gc->list);
 495         raw_spin_unlock(&gc_lock);
 496
 497         for (; msk; msk >>= 1, i++) {
 498                 if (!(msk & 0x01))
 499                         continue;
 500
 501                 /* Remove handler first. That will mask the irq line */
 502                 irq_set_handler(i, NULL);
 503                 irq_set_chip(i, &no_irq_chip);
 504                 irq_set_chip_data(i, NULL);
 505                 irq_modify_status(i, clr, set);
 506         }
 507 }
 508 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
 509
 510 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
 511 {
 512         unsigned int virq;
 513
 514         if (!gc->domain)
 515                 return irq_get_irq_data(gc->irq_base);
 516
 517         /*
 518          * We don't know which of the irqs has been actually
 519          * installed. Use the first one.
 520          */
 521         if (!gc->installed)
 522                 return NULL;
 523
 524         virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
 525         return virq ? irq_get_irq_data(virq) : NULL;
 526 }
 527
 528 #ifdef CONFIG_PM
 529 static int irq_gc_suspend(void)
 530 {
 531         struct irq_chip_generic *gc;
 532
 533         list_for_each_entry(gc, &gc_list, list) {
 534                 struct irq_chip_type *ct = gc->chip_types;
 535
 536                 if (ct->chip.irq_suspend) {
 537                         struct irq_data *data = irq_gc_get_irq_data(gc);
 538
 539                         if (data)
 540                                 ct->chip.irq_suspend(data);
 541                 }
 542         }
 543         return 0;
 544 }
 545
 546 static void irq_gc_resume(void)
 547 {
 548         struct irq_chip_generic *gc;
 549
 550         list_for_each_entry(gc, &gc_list, list) {
 551                 struct irq_chip_type *ct = gc->chip_types;
 552
 553                 if (ct->chip.irq_resume) {
 554                         struct irq_data *data = irq_gc_get_irq_data(gc);
 555
 556                         if (data)
 557                                 ct->chip.irq_resume(data);
 558                 }
 559         }
 560 }
 561 #else
 562 #define irq_gc_suspend NULL
 563 #define irq_gc_resume NULL
 564 #endif
 565
 566 static void irq_gc_shutdown(void)
 567 {
 568         struct irq_chip_generic *gc;
 569
 570         list_for_each_entry(gc, &gc_list, list) {
 571                 struct irq_chip_type *ct = gc->chip_types;
 572
 573                 if (ct->chip.irq_pm_shutdown) {
 574                         struct irq_data *data = irq_gc_get_irq_data(gc);
 575
 576                         if (data)
 577                                 ct->chip.irq_pm_shutdown(data);
 578                 }
 579         }
 580 }
 581
 582 static struct syscore_ops irq_gc_syscore_ops = {
 583         .suspend = irq_gc_suspend,
 584         .resume = irq_gc_resume,
 585         .shutdown = irq_gc_shutdown,
 586 };
 587
 588 static int __init irq_gc_init_ops(void)
 589 {
 590         register_syscore_ops(&irq_gc_syscore_ops);
 591         return 0;
 592 }
 593 device_initcall(irq_gc_init_ops);