1 .*: file format elf32-.*arm
2 architecture: arm.*, flags 0x00000150:
3 HAS_SYMS, DYNAMIC, D_PAGED
6 Disassembly of section .plt:
9 .*: e52de004 push {lr} ; .*
10 .*: e59fe004 ldr lr, \[pc, #4\] ; .*
11 .*: e08fe00e add lr, pc, lr
12 .*: e5bef008 ldr pc, \[lr, #8\]!
13 .*: 000080f0 .word 0x000080f0
14 .*: e08e0000 add r0, lr, r0
15 .*: e5901004 ldr r1, \[r0, #4\]
17 .*: e52d2004 push {r2} ; .*
18 .*: e59f200c ldr r2, \[pc, #12\] ; .*
19 .*: e59f100c ldr r1, \[pc, #12\] ; .*
20 .*: e79f2002 ldr r2, \[pc, r2\]
21 .*: e081100f add r1, r1, pc
23 .*: 000080e8 .word 0x000080e8
24 .*: 000080c8 .word 0x000080c8
26 Disassembly of section .text:
29 .*: e59f0004 ldr r0, \[pc, #4\] ; .*
30 .*: ebfffff1 bl .* <\.plt\+0x14>
32 .*: 000080c0 .word 0x000080c0
33 .*: 4801 ldr r0, \[pc, #4\] ; .*
34 .*: f000 f805 bl .* <__unnamed_veneer>
36 .*: 000080b1 .word 0x000080b1
37 .*: 00000000 .word 0x00000000
39 000081a0 <__unnamed_veneer>:
42 .*: e59f1000 ldr r1, \[pc\] ; .*
43 .*: e081f00f add pc, r1, pc
44 .*: ffffffa0 .word 0xffffffa0
46 Disassembly of section .foo:
49 .*: e59f0004 ldr r0, \[pc, #4\] ; .*
50 .*: eb000009 bl 4001030 .*
52 .*: fc00f240 .word 0xfc00f240
53 .*: e59f0004 ldr r0, \[pc, #4\] ; .*
54 .*: eb000005 bl 4001030 .*
56 .*: fc00f238 .word 0xfc00f238
57 .*: 4801 ldr r0, \[pc, #4\] ; .*
58 .*: f000 f80b bl 400103c .*
60 .*: fc00f221 .word 0xfc00f221
61 .*: 00000000 .word 0x00000000
63 04001030 <__unnamed_veneer>:
64 .*: e59f1000 ldr r1, \[pc\] ; .*
65 .*: e08ff001 add pc, pc, r1
66 .*: fc007114 .word 0xfc007114
68 0400103c <__unnamed_veneer>:
71 .*: e59f1000 ldr r1, \[pc\] ; .*
72 .*: e081f00f add pc, r1, pc
73 .*: fc007104 .word 0xfc007104
74 .*: 00000000 .word 0x00000000