3 #ld: -melf64ppc --emit-relocs
6 .*: file format elf64-powerpc
8 Disassembly of section \.text:
11 [0-9a-f ]*: 49 bf 00 2d bl .*
12 [0-9a-f ]*: R_PPC64_REL24 \.text\+0x37e003c
13 [0-9a-f ]*: 60 00 00 00 nop
14 [0-9a-f ]*: 49 bf 00 19 bl .*
15 [0-9a-f ]*: R_PPC64_REL24 \.text\+0x3bf0020
16 [0-9a-f ]*: 60 00 00 00 nop
17 [0-9a-f ]*: 49 bf 00 21 bl .*
18 [0-9a-f ]*: R_PPC64_REL24 \.text\+0x57e0024
19 [0-9a-f ]*: 60 00 00 00 nop
20 [0-9a-f ]*: 00 00 00 00 \.long 0x0
21 [0-9a-f ]*: 4b ff ff e4 b .* <_start>
24 [0-9a-f ]*<.*plt_branch.*>:
25 [0-9a-f ]*: e9 62 80 00 ld r11,-32768\(r2\)
26 [0-9a-f ]*: 7d 69 03 a6 mtctr r11
27 [0-9a-f ]*: 4e 80 04 20 bctr
29 [0-9a-f ]*<.*long_branch.*>:
30 [0-9a-f ]*: 49 bf 00 10 b .* <far>
31 [0-9a-f ]*: R_PPC64_REL24 \*ABS\*\+0x137e00ec
33 [0-9a-f ]*<.*plt_branch.*>:
34 [0-9a-f ]*: e9 62 80 08 ld r11,-32760\(r2\)
35 [0-9a-f ]*: 7d 69 03 a6 mtctr r11
36 [0-9a-f ]*: 4e 80 04 20 bctr
40 [0-9a-f ]*: 4e 80 00 20 blr
44 [0-9a-f ]*: 4e 80 00 20 blr
48 [0-9a-f ]*: 4e 80 00 20 blr