ld/testsuite/ld-powerpc/tlsexe.d

   1 #source: tls.s
   2 #as: -a64
   3 #ld: -melf64ppc tmpdir/libtlslib.so
   4 #objdump: -dr
   5 #target: powerpc64*-*-*
   6
   7 .*: +file format elf64-powerpc
   8
   9 Disassembly of section \.text:
  10
  11 .* <00000010\.plt_call\.__tls_get_addr(|_opt)\+0>:
  12 .*      e9 63 00 00     ld      r11,0\(r3\)
  13 .*      e9 83 00 08     ld      r12,8\(r3\)
  14 .*      7c 60 1b 78     mr      r0,r3
  15 .*      2c 2b 00 00     cmpdi   r11,0
  16 .*      7c 6c 6a 14     add     r3,r12,r13
  17 .*      4d 82 00 20     beqlr
  18 .*      7c 03 03 78     mr      r3,r0
  19 .*      7d 68 02 a6     mflr    r11
  20 .*      f9 61 00 20     std     r11,32\(r1\)
  21 .*      f8 41 00 28     std     r2,40\(r1\)
  22 .*      e9 62 80 48     ld      r11,-32696\(r2\)
  23 .*      7d 69 03 a6     mtctr   r11
  24 .*      e9 62 80 58     ld      r11,-32680\(r2\)
  25 .*      e8 42 80 50     ld      r2,-32688\(r2\)
  26 .*      4e 80 04 21     bctrl
  27 .*      e9 61 00 20     ld      r11,32\(r1\)
  28 .*      e8 41 00 28     ld      r2,40\(r1\)
  29 .*      7d 68 03 a6     mtlr    r11
  30 .*      4e 80 00 20     blr
  31
  32 .* <_start>:
  33 .*      e8 62 80 10     ld      r3,-32752\(r2\)
  34 .*      60 00 00 00     nop
  35 .*      7c 63 6a 14     add     r3,r3,r13
  36 .*      38 62 80 18     addi    r3,r2,-32744
  37 .*      4b ff ff a5     bl      .*
  38 .*      60 00 00 00     nop
  39 .*      3c 6d 00 00     addis   r3,r13,0
  40 .*      60 00 00 00     nop
  41 .*      38 63 90 38     addi    r3,r3,-28616
  42 .*      3c 6d 00 00     addis   r3,r13,0
  43 .*      60 00 00 00     nop
  44 .*      38 63 10 00     addi    r3,r3,4096
  45 .*      39 23 80 40     addi    r9,r3,-32704
  46 .*      3d 23 00 00     addis   r9,r3,0
  47 .*      81 49 80 48     lwz     r10,-32696\(r9\)
  48 .*      e9 22 80 28     ld      r9,-32728\(r2\)
  49 .*      7d 49 18 2a     ldx     r10,r9,r3
  50 .*      3d 2d 00 00     addis   r9,r13,0
  51 .*      a1 49 90 58     lhz     r10,-28584\(r9\)
  52 .*      89 4d 90 60     lbz     r10,-28576\(r13\)
  53 .*      3d 2d 00 00     addis   r9,r13,0
  54 .*      99 49 90 68     stb     r10,-28568\(r9\)
  55 .*      3c 6d 00 00     addis   r3,r13,0
  56 .*      60 00 00 00     nop
  57 .*      38 63 90 00     addi    r3,r3,-28672
  58 .*      3c 6d 00 00     addis   r3,r13,0
  59 .*      60 00 00 00     nop
  60 .*      38 63 10 00     addi    r3,r3,4096
  61 .*      f9 43 80 08     std     r10,-32760\(r3\)
  62 .*      3d 23 00 00     addis   r9,r3,0
  63 .*      91 49 80 10     stw     r10,-32752\(r9\)
  64 .*      e9 22 80 08     ld      r9,-32760\(r2\)
  65 .*      7d 49 19 2a     stdx    r10,r9,r3
  66 .*      3d 2d 00 00     addis   r9,r13,0
  67 .*      b1 49 90 58     sth     r10,-28584\(r9\)
  68 .*      e9 4d 90 2a     lwa     r10,-28632\(r13\)
  69 .*      3d 2d 00 00     addis   r9,r13,0
  70 .*      a9 49 90 30     lha     r10,-28624\(r9\)
  71 .*      60 00 00 00     nop
  72 .*      00 00 00 00 .*
  73 .*      00 01 02 00 .*
  74 .* <__glink_PLTresolve>:
  75 .*      7d 88 02 a6     mflr    r12
  76 .*      42 9f 00 05     bcl-    20,4\*cr7\+so,.*
  77 .*      7d 68 02 a6     mflr    r11
  78 .*      e8 4b ff f0     ld      r2,-16\(r11\)
  79 .*      7d 88 03 a6     mtlr    r12
  80 .*      7d 82 5a 14     add     r12,r2,r11
  81 .*      e9 6c 00 00     ld      r11,0\(r12\)
  82 .*      e8 4c 00 08     ld      r2,8\(r12\)
  83 .*      7d 69 03 a6     mtctr   r11
  84 .*      e9 6c 00 10     ld      r11,16\(r12\)
  85 .*      4e 80 04 20     bctr
  86 .*      60 00 00 00     nop
  87 .*      60 00 00 00     nop
  88 .*      60 00 00 00     nop
  89 .*      38 00 00 00     li      r0,0
  90 .*      4b ff ff c4     b       .*