1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "gdbsupport/x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
41 #include "gdbsupport/agent.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static struct target_desc
*tdesc_amd64_linux_no_xml
;
53 static struct target_desc
*tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char *xmltarget_i386_linux_no_xml
= "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char *xmltarget_amd64_linux_no_xml
= "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
77 #ifndef PTRACE_GET_THREAD_AREA
78 #define PTRACE_GET_THREAD_AREA 25
81 /* This definition comes from prctl.h, but some kernels may not have it. */
82 #ifndef PTRACE_ARCH_PRCTL
83 #define PTRACE_ARCH_PRCTL 30
86 /* The following definitions come from prctl.h, but may be absent
87 for certain configurations. */
89 #define ARCH_SET_GS 0x1001
90 #define ARCH_SET_FS 0x1002
91 #define ARCH_GET_FS 0x1003
92 #define ARCH_GET_GS 0x1004
95 /* Linux target op definitions for the x86 architecture.
96 This is initialized assuming an amd64 target.
97 'low_arch_setup' will correct it for i386 or amd64 targets. */
99 class x86_target
: public linux_process_target
103 const regs_info
*get_regs_info () override
;
105 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
107 bool supports_z_point_type (char z_type
) override
;
109 void process_qsupported (char **features
, int count
) override
;
111 bool supports_tracepoints () override
;
113 bool supports_fast_tracepoints () override
;
115 int install_fast_tracepoint_jump_pad
116 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
117 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
118 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
119 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
120 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
123 int get_min_fast_tracepoint_insn_len () override
;
125 struct emit_ops
*emit_ops () override
;
127 int get_ipa_tdesc_idx () override
;
131 void low_arch_setup () override
;
133 bool low_cannot_fetch_register (int regno
) override
;
135 bool low_cannot_store_register (int regno
) override
;
137 bool low_supports_breakpoints () override
;
139 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
141 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
143 int low_decr_pc_after_break () override
;
145 bool low_breakpoint_at (CORE_ADDR pc
) override
;
147 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
148 int size
, raw_breakpoint
*bp
) override
;
150 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
151 int size
, raw_breakpoint
*bp
) override
;
153 bool low_stopped_by_watchpoint () override
;
155 CORE_ADDR
low_stopped_data_address () override
;
157 /* collect_ptrace_register/supply_ptrace_register are not needed in the
158 native i386 case (no registers smaller than an xfer unit), and are not
159 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
161 /* Need to fix up i386 siginfo if host is amd64. */
162 bool low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
163 int direction
) override
;
165 arch_process_info
*low_new_process () override
;
167 void low_delete_process (arch_process_info
*info
) override
;
169 void low_new_thread (lwp_info
*) override
;
171 void low_delete_thread (arch_lwp_info
*) override
;
173 void low_new_fork (process_info
*parent
, process_info
*child
) override
;
175 void low_prepare_to_resume (lwp_info
*lwp
) override
;
177 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
179 bool low_supports_range_stepping () override
;
181 bool low_supports_catch_syscall () override
;
183 void low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
) override
;
187 /* Update all the target description of all processes; a new GDB
188 connected, and it may or not support xml target descriptions. */
189 void update_xmltarget ();
192 /* The singleton target ops object. */
194 static x86_target the_x86_target
;
196 /* Per-process arch-specific data we want to keep. */
198 struct arch_process_info
200 struct x86_debug_reg_state debug_reg_state
;
205 /* Mapping between the general-purpose registers in `struct user'
206 format and GDB's register array layout.
207 Note that the transfer layout uses 64-bit regs. */
208 static /*const*/ int i386_regmap
[] =
210 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
211 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
212 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
213 DS
* 8, ES
* 8, FS
* 8, GS
* 8
216 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
218 /* So code below doesn't have to care, i386 or amd64. */
219 #define ORIG_EAX ORIG_RAX
222 static const int x86_64_regmap
[] =
224 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
225 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
226 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
227 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
228 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
229 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
230 -1, -1, -1, -1, -1, -1, -1, -1,
231 -1, -1, -1, -1, -1, -1, -1, -1,
232 -1, -1, -1, -1, -1, -1, -1, -1,
234 -1, -1, -1, -1, -1, -1, -1, -1,
237 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
238 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
239 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
240 -1, -1, -1, -1, -1, -1, -1, -1,
241 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
242 -1, -1, -1, -1, -1, -1, -1, -1,
243 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
244 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
245 -1, -1, -1, -1, -1, -1, -1, -1,
246 -1, -1, -1, -1, -1, -1, -1, -1,
247 -1, -1, -1, -1, -1, -1, -1, -1,
251 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
252 #define X86_64_USER_REGS (GS + 1)
254 #else /* ! __x86_64__ */
256 /* Mapping between the general-purpose registers in `struct user'
257 format and GDB's register array layout. */
258 static /*const*/ int i386_regmap
[] =
260 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
261 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
262 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
263 DS
* 4, ES
* 4, FS
* 4, GS
* 4
266 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
274 /* Returns true if the current inferior belongs to a x86-64 process,
278 is_64bit_tdesc (void)
280 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
282 return register_size (regcache
->tdesc
, 0) == 8;
288 /* Called by libthread_db. */
291 ps_get_thread_area (struct ps_prochandle
*ph
,
292 lwpid_t lwpid
, int idx
, void **base
)
295 int use_64bit
= is_64bit_tdesc ();
302 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
306 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
317 unsigned int desc
[4];
319 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
320 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
323 /* Ensure we properly extend the value to 64-bits for x86_64. */
324 *base
= (void *) (uintptr_t) desc
[1];
329 /* Get the thread area address. This is used to recognize which
330 thread is which when tracing with the in-process agent library. We
331 don't read anything from the address, and treat it as opaque; it's
332 the address itself that we assume is unique per-thread. */
335 x86_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
338 int use_64bit
= is_64bit_tdesc ();
343 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
345 *addr
= (CORE_ADDR
) (uintptr_t) base
;
354 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
355 struct thread_info
*thr
= get_lwp_thread (lwp
);
356 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
357 unsigned int desc
[4];
359 const int reg_thread_area
= 3; /* bits to scale down register value. */
362 collect_register_by_name (regcache
, "gs", &gs
);
364 idx
= gs
>> reg_thread_area
;
366 if (ptrace (PTRACE_GET_THREAD_AREA
,
368 (void *) (long) idx
, (unsigned long) &desc
) < 0)
379 x86_target::low_cannot_store_register (int regno
)
382 if (is_64bit_tdesc ())
386 return regno
>= I386_NUM_REGS
;
390 x86_target::low_cannot_fetch_register (int regno
)
393 if (is_64bit_tdesc ())
397 return regno
>= I386_NUM_REGS
;
401 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
406 if (register_size (regcache
->tdesc
, 0) == 8)
408 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
409 if (x86_64_regmap
[i
] != -1)
410 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
415 /* 32-bit inferior registers need to be zero-extended.
416 Callers would read uninitialized memory otherwise. */
417 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
420 for (i
= 0; i
< I386_NUM_REGS
; i
++)
421 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
423 collect_register_by_name (regcache
, "orig_eax",
424 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
427 /* Sign extend EAX value to avoid potential syscall restart
430 See amd64_linux_collect_native_gregset() in gdb/amd64-linux-nat.c
431 for a detailed explanation. */
432 if (register_size (regcache
->tdesc
, 0) == 4)
434 void *ptr
= ((gdb_byte
*) buf
435 + i386_regmap
[find_regno (regcache
->tdesc
, "eax")]);
437 *(int64_t *) ptr
= *(int32_t *) ptr
;
443 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
448 if (register_size (regcache
->tdesc
, 0) == 8)
450 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
451 if (x86_64_regmap
[i
] != -1)
452 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
458 for (i
= 0; i
< I386_NUM_REGS
; i
++)
459 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
461 supply_register_by_name (regcache
, "orig_eax",
462 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
466 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
469 i387_cache_to_fxsave (regcache
, buf
);
471 i387_cache_to_fsave (regcache
, buf
);
476 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
479 i387_fxsave_to_cache (regcache
, buf
);
481 i387_fsave_to_cache (regcache
, buf
);
488 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
490 i387_cache_to_fxsave (regcache
, buf
);
494 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
496 i387_fxsave_to_cache (regcache
, buf
);
502 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
504 i387_cache_to_xsave (regcache
, buf
);
508 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
510 i387_xsave_to_cache (regcache
, buf
);
513 /* ??? The non-biarch i386 case stores all the i387 regs twice.
514 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
515 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
516 doesn't work. IWBN to avoid the duplication in the case where it
517 does work. Maybe the arch_setup routine could check whether it works
518 and update the supported regsets accordingly. */
520 static struct regset_info x86_regsets
[] =
522 #ifdef HAVE_PTRACE_GETREGS
523 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
525 x86_fill_gregset
, x86_store_gregset
},
526 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
527 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
529 # ifdef HAVE_PTRACE_GETFPXREGS
530 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
532 x86_fill_fpxregset
, x86_store_fpxregset
},
535 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
537 x86_fill_fpregset
, x86_store_fpregset
},
538 #endif /* HAVE_PTRACE_GETREGS */
543 x86_target::low_supports_breakpoints ()
549 x86_target::low_get_pc (regcache
*regcache
)
551 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
557 collect_register_by_name (regcache
, "rip", &pc
);
558 return (CORE_ADDR
) pc
;
564 collect_register_by_name (regcache
, "eip", &pc
);
565 return (CORE_ADDR
) pc
;
570 x86_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
572 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
578 supply_register_by_name (regcache
, "rip", &newpc
);
584 supply_register_by_name (regcache
, "eip", &newpc
);
589 x86_target::low_decr_pc_after_break ()
595 static const gdb_byte x86_breakpoint
[] = { 0xCC };
596 #define x86_breakpoint_len 1
599 x86_target::low_breakpoint_at (CORE_ADDR pc
)
603 read_memory (pc
, &c
, 1);
610 /* Low-level function vector. */
611 struct x86_dr_low_type x86_dr_low
=
613 x86_linux_dr_set_control
,
614 x86_linux_dr_set_addr
,
615 x86_linux_dr_get_addr
,
616 x86_linux_dr_get_status
,
617 x86_linux_dr_get_control
,
621 /* Breakpoint/Watchpoint support. */
624 x86_target::supports_z_point_type (char z_type
)
630 case Z_PACKET_WRITE_WP
:
631 case Z_PACKET_ACCESS_WP
:
639 x86_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
640 int size
, raw_breakpoint
*bp
)
642 struct process_info
*proc
= current_process ();
646 case raw_bkpt_type_hw
:
647 case raw_bkpt_type_write_wp
:
648 case raw_bkpt_type_access_wp
:
650 enum target_hw_bp_type hw_type
651 = raw_bkpt_type_to_target_hw_bp_type (type
);
652 struct x86_debug_reg_state
*state
653 = &proc
->priv
->arch_private
->debug_reg_state
;
655 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
665 x86_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
666 int size
, raw_breakpoint
*bp
)
668 struct process_info
*proc
= current_process ();
672 case raw_bkpt_type_hw
:
673 case raw_bkpt_type_write_wp
:
674 case raw_bkpt_type_access_wp
:
676 enum target_hw_bp_type hw_type
677 = raw_bkpt_type_to_target_hw_bp_type (type
);
678 struct x86_debug_reg_state
*state
679 = &proc
->priv
->arch_private
->debug_reg_state
;
681 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
690 x86_target::low_stopped_by_watchpoint ()
692 struct process_info
*proc
= current_process ();
693 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
697 x86_target::low_stopped_data_address ()
699 struct process_info
*proc
= current_process ();
701 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
707 /* Called when a new process is created. */
710 x86_target::low_new_process ()
712 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
714 x86_low_init_dregs (&info
->debug_reg_state
);
719 /* Called when a process is being deleted. */
722 x86_target::low_delete_process (arch_process_info
*info
)
728 x86_target::low_new_thread (lwp_info
*lwp
)
730 /* This comes from nat/. */
731 x86_linux_new_thread (lwp
);
735 x86_target::low_delete_thread (arch_lwp_info
*alwp
)
737 /* This comes from nat/. */
738 x86_linux_delete_thread (alwp
);
741 /* Target routine for new_fork. */
744 x86_target::low_new_fork (process_info
*parent
, process_info
*child
)
746 /* These are allocated by linux_add_process. */
747 gdb_assert (parent
->priv
!= NULL
748 && parent
->priv
->arch_private
!= NULL
);
749 gdb_assert (child
->priv
!= NULL
750 && child
->priv
->arch_private
!= NULL
);
752 /* Linux kernel before 2.6.33 commit
753 72f674d203cd230426437cdcf7dd6f681dad8b0d
754 will inherit hardware debug registers from parent
755 on fork/vfork/clone. Newer Linux kernels create such tasks with
756 zeroed debug registers.
758 GDB core assumes the child inherits the watchpoints/hw
759 breakpoints of the parent, and will remove them all from the
760 forked off process. Copy the debug registers mirrors into the
761 new process so that all breakpoints and watchpoints can be
762 removed together. The debug registers mirror will become zeroed
763 in the end before detaching the forked off process, thus making
764 this compatible with older Linux kernels too. */
766 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
770 x86_target::low_prepare_to_resume (lwp_info
*lwp
)
772 /* This comes from nat/. */
773 x86_linux_prepare_to_resume (lwp
);
776 /* See nat/x86-dregs.h. */
778 struct x86_debug_reg_state
*
779 x86_debug_reg_state (pid_t pid
)
781 struct process_info
*proc
= find_process_pid (pid
);
783 return &proc
->priv
->arch_private
->debug_reg_state
;
786 /* When GDBSERVER is built as a 64-bit application on linux, the
787 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
788 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
789 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
790 conversion in-place ourselves. */
792 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
793 layout of the inferiors' architecture. Returns true if any
794 conversion was done; false otherwise. If DIRECTION is 1, then copy
795 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
799 x86_target::low_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
802 unsigned int machine
;
803 int tid
= lwpid_of (current_thread
);
804 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
806 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
807 if (!is_64bit_tdesc ())
808 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
810 /* No fixup for native x32 GDB. */
811 else if (!is_elf64
&& sizeof (void *) == 8)
812 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
821 /* Format of XSAVE extended state is:
825 sw_usable_bytes[464..511]
826 xstate_hdr_bytes[512..575]
831 Same memory layout will be used for the coredump NT_X86_XSTATE
832 representing the XSAVE extended state registers.
834 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
835 extended state mask, which is the same as the extended control register
836 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
837 together with the mask saved in the xstate_hdr_bytes to determine what
838 states the processor/OS supports and what state, used or initialized,
839 the process/thread is in. */
840 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
842 /* Does the current host support the GETFPXREGS request? The header
843 file may or may not define it, and even if it is defined, the
844 kernel will return EIO if it's running on a pre-SSE processor. */
845 int have_ptrace_getfpxregs
=
846 #ifdef HAVE_PTRACE_GETFPXREGS
853 /* Get Linux/x86 target description from running target. */
855 static const struct target_desc
*
856 x86_linux_read_description (void)
858 unsigned int machine
;
862 static uint64_t xcr0
;
863 struct regset_info
*regset
;
865 tid
= lwpid_of (current_thread
);
867 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
869 if (sizeof (void *) == 4)
872 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
874 else if (machine
== EM_X86_64
)
875 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
879 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
880 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
882 elf_fpxregset_t fpxregs
;
884 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
886 have_ptrace_getfpxregs
= 0;
887 have_ptrace_getregset
= 0;
888 return i386_linux_read_description (X86_XSTATE_X87
);
891 have_ptrace_getfpxregs
= 1;
897 x86_xcr0
= X86_XSTATE_SSE_MASK
;
901 if (machine
== EM_X86_64
)
902 return tdesc_amd64_linux_no_xml
;
905 return tdesc_i386_linux_no_xml
;
908 if (have_ptrace_getregset
== -1)
910 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
913 iov
.iov_base
= xstateregs
;
914 iov
.iov_len
= sizeof (xstateregs
);
916 /* Check if PTRACE_GETREGSET works. */
917 if (ptrace (PTRACE_GETREGSET
, tid
,
918 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
919 have_ptrace_getregset
= 0;
922 have_ptrace_getregset
= 1;
924 /* Get XCR0 from XSAVE extended state. */
925 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
926 / sizeof (uint64_t))];
928 /* Use PTRACE_GETREGSET if it is available. */
929 for (regset
= x86_regsets
;
930 regset
->fill_function
!= NULL
; regset
++)
931 if (regset
->get_request
== PTRACE_GETREGSET
)
932 regset
->size
= X86_XSTATE_SIZE (xcr0
);
933 else if (regset
->type
!= GENERAL_REGS
)
938 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
939 xcr0_features
= (have_ptrace_getregset
940 && (xcr0
& X86_XSTATE_ALL_MASK
));
945 if (machine
== EM_X86_64
)
948 const target_desc
*tdesc
= NULL
;
952 tdesc
= amd64_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
,
957 tdesc
= amd64_linux_read_description (X86_XSTATE_SSE_MASK
, !is_elf64
);
963 const target_desc
*tdesc
= NULL
;
966 tdesc
= i386_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
);
969 tdesc
= i386_linux_read_description (X86_XSTATE_SSE
);
974 gdb_assert_not_reached ("failed to return tdesc");
977 /* Update all the target description of all processes; a new GDB
978 connected, and it may or not support xml target descriptions. */
981 x86_target::update_xmltarget ()
983 struct thread_info
*saved_thread
= current_thread
;
985 /* Before changing the register cache's internal layout, flush the
986 contents of the current valid caches back to the threads, and
987 release the current regcache objects. */
990 for_each_process ([this] (process_info
*proc
) {
993 /* Look up any thread of this process. */
994 current_thread
= find_any_thread_of_pid (pid
);
999 current_thread
= saved_thread
;
1002 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
1003 PTRACE_GETREGSET. */
1006 x86_target::process_qsupported (char **features
, int count
)
1010 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
1011 with "i386" in qSupported query, it supports x86 XML target
1014 for (i
= 0; i
< count
; i
++)
1016 const char *feature
= features
[i
];
1018 if (startswith (feature
, "xmlRegisters="))
1020 char *copy
= xstrdup (feature
+ 13);
1023 for (char *p
= strtok_r (copy
, ",", &saveptr
);
1025 p
= strtok_r (NULL
, ",", &saveptr
))
1027 if (strcmp (p
, "i386") == 0)
1037 update_xmltarget ();
1040 /* Common for x86/x86-64. */
1042 static struct regsets_info x86_regsets_info
=
1044 x86_regsets
, /* regsets */
1045 0, /* num_regsets */
1046 NULL
, /* disabled_regsets */
1050 static struct regs_info amd64_linux_regs_info
=
1052 NULL
, /* regset_bitmap */
1053 NULL
, /* usrregs_info */
1057 static struct usrregs_info i386_linux_usrregs_info
=
1063 static struct regs_info i386_linux_regs_info
=
1065 NULL
, /* regset_bitmap */
1066 &i386_linux_usrregs_info
,
1071 x86_target::get_regs_info ()
1074 if (is_64bit_tdesc ())
1075 return &amd64_linux_regs_info
;
1078 return &i386_linux_regs_info
;
1081 /* Initialize the target description for the architecture of the
1085 x86_target::low_arch_setup ()
1087 current_process ()->tdesc
= x86_linux_read_description ();
1091 x86_target::low_supports_catch_syscall ()
1096 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1097 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1100 x86_target::low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
)
1102 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1108 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1109 *sysno
= (int) l_sysno
;
1112 collect_register_by_name (regcache
, "orig_eax", sysno
);
1116 x86_target::supports_tracepoints ()
1122 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1124 target_write_memory (*to
, buf
, len
);
1129 push_opcode (unsigned char *buf
, const char *op
)
1131 unsigned char *buf_org
= buf
;
1136 unsigned long ul
= strtoul (op
, &endptr
, 16);
1145 return buf
- buf_org
;
1150 /* Build a jump pad that saves registers and calls a collection
1151 function. Writes a jump instruction to the jump pad to
1152 JJUMPAD_INSN. The caller is responsible to write it in at the
1153 tracepoint address. */
1156 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1157 CORE_ADDR collector
,
1160 CORE_ADDR
*jump_entry
,
1161 CORE_ADDR
*trampoline
,
1162 ULONGEST
*trampoline_size
,
1163 unsigned char *jjump_pad_insn
,
1164 ULONGEST
*jjump_pad_insn_size
,
1165 CORE_ADDR
*adjusted_insn_addr
,
1166 CORE_ADDR
*adjusted_insn_addr_end
,
1169 unsigned char buf
[40];
1173 CORE_ADDR buildaddr
= *jump_entry
;
1175 /* Build the jump pad. */
1177 /* First, do tracepoint data collection. Save registers. */
1179 /* Need to ensure stack pointer saved first. */
1180 buf
[i
++] = 0x54; /* push %rsp */
1181 buf
[i
++] = 0x55; /* push %rbp */
1182 buf
[i
++] = 0x57; /* push %rdi */
1183 buf
[i
++] = 0x56; /* push %rsi */
1184 buf
[i
++] = 0x52; /* push %rdx */
1185 buf
[i
++] = 0x51; /* push %rcx */
1186 buf
[i
++] = 0x53; /* push %rbx */
1187 buf
[i
++] = 0x50; /* push %rax */
1188 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1189 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1190 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1191 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1192 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1193 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1194 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1195 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1196 buf
[i
++] = 0x9c; /* pushfq */
1197 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1199 memcpy (buf
+ i
, &tpaddr
, 8);
1201 buf
[i
++] = 0x57; /* push %rdi */
1202 append_insns (&buildaddr
, i
, buf
);
1204 /* Stack space for the collecting_t object. */
1206 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1207 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1208 memcpy (buf
+ i
, &tpoint
, 8);
1210 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1211 i
+= push_opcode (&buf
[i
],
1212 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1213 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1214 append_insns (&buildaddr
, i
, buf
);
1218 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1219 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1221 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1222 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1223 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1224 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1225 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1226 append_insns (&buildaddr
, i
, buf
);
1228 /* Set up the gdb_collect call. */
1229 /* At this point, (stack pointer + 0x18) is the base of our saved
1233 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1234 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1236 /* tpoint address may be 64-bit wide. */
1237 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1238 memcpy (buf
+ i
, &tpoint
, 8);
1240 append_insns (&buildaddr
, i
, buf
);
1242 /* The collector function being in the shared library, may be
1243 >31-bits away off the jump pad. */
1245 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1246 memcpy (buf
+ i
, &collector
, 8);
1248 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1249 append_insns (&buildaddr
, i
, buf
);
1251 /* Clear the spin-lock. */
1253 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1254 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1255 memcpy (buf
+ i
, &lockaddr
, 8);
1257 append_insns (&buildaddr
, i
, buf
);
1259 /* Remove stack that had been used for the collect_t object. */
1261 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1262 append_insns (&buildaddr
, i
, buf
);
1264 /* Restore register state. */
1266 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1270 buf
[i
++] = 0x9d; /* popfq */
1271 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1272 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1273 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1274 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1275 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1276 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1277 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1278 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1279 buf
[i
++] = 0x58; /* pop %rax */
1280 buf
[i
++] = 0x5b; /* pop %rbx */
1281 buf
[i
++] = 0x59; /* pop %rcx */
1282 buf
[i
++] = 0x5a; /* pop %rdx */
1283 buf
[i
++] = 0x5e; /* pop %rsi */
1284 buf
[i
++] = 0x5f; /* pop %rdi */
1285 buf
[i
++] = 0x5d; /* pop %rbp */
1286 buf
[i
++] = 0x5c; /* pop %rsp */
1287 append_insns (&buildaddr
, i
, buf
);
1289 /* Now, adjust the original instruction to execute in the jump
1291 *adjusted_insn_addr
= buildaddr
;
1292 relocate_instruction (&buildaddr
, tpaddr
);
1293 *adjusted_insn_addr_end
= buildaddr
;
1295 /* Finally, write a jump back to the program. */
1297 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1298 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1301 "E.Jump back from jump pad too far from tracepoint "
1302 "(offset 0x%" PRIx64
" > int32).", loffset
);
1306 offset
= (int) loffset
;
1307 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1308 memcpy (buf
+ 1, &offset
, 4);
1309 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1311 /* The jump pad is now built. Wire in a jump to our jump pad. This
1312 is always done last (by our caller actually), so that we can
1313 install fast tracepoints with threads running. This relies on
1314 the agent's atomic write support. */
1315 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1316 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1319 "E.Jump pad too far from tracepoint "
1320 "(offset 0x%" PRIx64
" > int32).", loffset
);
1324 offset
= (int) loffset
;
1326 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1327 memcpy (buf
+ 1, &offset
, 4);
1328 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1329 *jjump_pad_insn_size
= sizeof (jump_insn
);
1331 /* Return the end address of our pad. */
1332 *jump_entry
= buildaddr
;
1337 #endif /* __x86_64__ */
1339 /* Build a jump pad that saves registers and calls a collection
1340 function. Writes a jump instruction to the jump pad to
1341 JJUMPAD_INSN. The caller is responsible to write it in at the
1342 tracepoint address. */
1345 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1346 CORE_ADDR collector
,
1349 CORE_ADDR
*jump_entry
,
1350 CORE_ADDR
*trampoline
,
1351 ULONGEST
*trampoline_size
,
1352 unsigned char *jjump_pad_insn
,
1353 ULONGEST
*jjump_pad_insn_size
,
1354 CORE_ADDR
*adjusted_insn_addr
,
1355 CORE_ADDR
*adjusted_insn_addr_end
,
1358 unsigned char buf
[0x100];
1360 CORE_ADDR buildaddr
= *jump_entry
;
1362 /* Build the jump pad. */
1364 /* First, do tracepoint data collection. Save registers. */
1366 buf
[i
++] = 0x60; /* pushad */
1367 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1368 *((int *)(buf
+ i
)) = (int) tpaddr
;
1370 buf
[i
++] = 0x9c; /* pushf */
1371 buf
[i
++] = 0x1e; /* push %ds */
1372 buf
[i
++] = 0x06; /* push %es */
1373 buf
[i
++] = 0x0f; /* push %fs */
1375 buf
[i
++] = 0x0f; /* push %gs */
1377 buf
[i
++] = 0x16; /* push %ss */
1378 buf
[i
++] = 0x0e; /* push %cs */
1379 append_insns (&buildaddr
, i
, buf
);
1381 /* Stack space for the collecting_t object. */
1383 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1385 /* Build the object. */
1386 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1387 memcpy (buf
+ i
, &tpoint
, 4);
1389 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1391 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1392 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1393 append_insns (&buildaddr
, i
, buf
);
1395 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1396 If we cared for it, this could be using xchg alternatively. */
1399 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1400 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1402 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1404 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1405 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1406 append_insns (&buildaddr
, i
, buf
);
1409 /* Set up arguments to the gdb_collect call. */
1411 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1412 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1413 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1414 append_insns (&buildaddr
, i
, buf
);
1417 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1418 append_insns (&buildaddr
, i
, buf
);
1421 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1422 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1424 append_insns (&buildaddr
, i
, buf
);
1426 buf
[0] = 0xe8; /* call <reladdr> */
1427 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1428 memcpy (buf
+ 1, &offset
, 4);
1429 append_insns (&buildaddr
, 5, buf
);
1430 /* Clean up after the call. */
1431 buf
[0] = 0x83; /* add $0x8,%esp */
1434 append_insns (&buildaddr
, 3, buf
);
1437 /* Clear the spin-lock. This would need the LOCK prefix on older
1440 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1441 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1442 memcpy (buf
+ i
, &lockaddr
, 4);
1444 append_insns (&buildaddr
, i
, buf
);
1447 /* Remove stack that had been used for the collect_t object. */
1449 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1450 append_insns (&buildaddr
, i
, buf
);
1453 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1456 buf
[i
++] = 0x17; /* pop %ss */
1457 buf
[i
++] = 0x0f; /* pop %gs */
1459 buf
[i
++] = 0x0f; /* pop %fs */
1461 buf
[i
++] = 0x07; /* pop %es */
1462 buf
[i
++] = 0x1f; /* pop %ds */
1463 buf
[i
++] = 0x9d; /* popf */
1464 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1467 buf
[i
++] = 0x61; /* popad */
1468 append_insns (&buildaddr
, i
, buf
);
1470 /* Now, adjust the original instruction to execute in the jump
1472 *adjusted_insn_addr
= buildaddr
;
1473 relocate_instruction (&buildaddr
, tpaddr
);
1474 *adjusted_insn_addr_end
= buildaddr
;
1476 /* Write the jump back to the program. */
1477 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1478 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1479 memcpy (buf
+ 1, &offset
, 4);
1480 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1482 /* The jump pad is now built. Wire in a jump to our jump pad. This
1483 is always done last (by our caller actually), so that we can
1484 install fast tracepoints with threads running. This relies on
1485 the agent's atomic write support. */
1488 /* Create a trampoline. */
1489 *trampoline_size
= sizeof (jump_insn
);
1490 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1492 /* No trampoline space available. */
1494 "E.Cannot allocate trampoline space needed for fast "
1495 "tracepoints on 4-byte instructions.");
1499 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1500 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1501 memcpy (buf
+ 1, &offset
, 4);
1502 target_write_memory (*trampoline
, buf
, sizeof (jump_insn
));
1504 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1505 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1506 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1507 memcpy (buf
+ 2, &offset
, 2);
1508 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1509 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1513 /* Else use a 32-bit relative jump instruction. */
1514 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1515 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1516 memcpy (buf
+ 1, &offset
, 4);
1517 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1518 *jjump_pad_insn_size
= sizeof (jump_insn
);
1521 /* Return the end address of our pad. */
1522 *jump_entry
= buildaddr
;
1528 x86_target::supports_fast_tracepoints ()
1534 x86_target::install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
1536 CORE_ADDR collector
,
1539 CORE_ADDR
*jump_entry
,
1540 CORE_ADDR
*trampoline
,
1541 ULONGEST
*trampoline_size
,
1542 unsigned char *jjump_pad_insn
,
1543 ULONGEST
*jjump_pad_insn_size
,
1544 CORE_ADDR
*adjusted_insn_addr
,
1545 CORE_ADDR
*adjusted_insn_addr_end
,
1549 if (is_64bit_tdesc ())
1550 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1551 collector
, lockaddr
,
1552 orig_size
, jump_entry
,
1553 trampoline
, trampoline_size
,
1555 jjump_pad_insn_size
,
1557 adjusted_insn_addr_end
,
1561 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1562 collector
, lockaddr
,
1563 orig_size
, jump_entry
,
1564 trampoline
, trampoline_size
,
1566 jjump_pad_insn_size
,
1568 adjusted_insn_addr_end
,
1572 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1576 x86_target::get_min_fast_tracepoint_insn_len ()
1578 static int warned_about_fast_tracepoints
= 0;
1581 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1582 used for fast tracepoints. */
1583 if (is_64bit_tdesc ())
1587 if (agent_loaded_p ())
1589 char errbuf
[IPA_BUFSIZ
];
1593 /* On x86, if trampolines are available, then 4-byte jump instructions
1594 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1595 with a 4-byte offset are used instead. */
1596 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1600 /* GDB has no channel to explain to user why a shorter fast
1601 tracepoint is not possible, but at least make GDBserver
1602 mention that something has gone awry. */
1603 if (!warned_about_fast_tracepoints
)
1605 warning ("4-byte fast tracepoints not available; %s", errbuf
);
1606 warned_about_fast_tracepoints
= 1;
1613 /* Indicate that the minimum length is currently unknown since the IPA
1614 has not loaded yet. */
1620 add_insns (unsigned char *start
, int len
)
1622 CORE_ADDR buildaddr
= current_insn_ptr
;
1625 debug_printf ("Adding %d bytes of insn at %s\n",
1626 len
, paddress (buildaddr
));
1628 append_insns (&buildaddr
, len
, start
);
1629 current_insn_ptr
= buildaddr
;
1632 /* Our general strategy for emitting code is to avoid specifying raw
1633 bytes whenever possible, and instead copy a block of inline asm
1634 that is embedded in the function. This is a little messy, because
1635 we need to keep the compiler from discarding what looks like dead
1636 code, plus suppress various warnings. */
1638 #define EMIT_ASM(NAME, INSNS) \
1641 extern unsigned char start_ ## NAME, end_ ## NAME; \
1642 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1643 __asm__ ("jmp end_" #NAME "\n" \
1644 "\t" "start_" #NAME ":" \
1646 "\t" "end_" #NAME ":"); \
1651 #define EMIT_ASM32(NAME,INSNS) \
1654 extern unsigned char start_ ## NAME, end_ ## NAME; \
1655 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1656 __asm__ (".code32\n" \
1657 "\t" "jmp end_" #NAME "\n" \
1658 "\t" "start_" #NAME ":\n" \
1660 "\t" "end_" #NAME ":\n" \
1666 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1673 amd64_emit_prologue (void)
1675 EMIT_ASM (amd64_prologue
,
1677 "movq %rsp,%rbp\n\t"
1678 "sub $0x20,%rsp\n\t"
1679 "movq %rdi,-8(%rbp)\n\t"
1680 "movq %rsi,-16(%rbp)");
1685 amd64_emit_epilogue (void)
1687 EMIT_ASM (amd64_epilogue
,
1688 "movq -16(%rbp),%rdi\n\t"
1689 "movq %rax,(%rdi)\n\t"
1696 amd64_emit_add (void)
1698 EMIT_ASM (amd64_add
,
1699 "add (%rsp),%rax\n\t"
1700 "lea 0x8(%rsp),%rsp");
1704 amd64_emit_sub (void)
1706 EMIT_ASM (amd64_sub
,
1707 "sub %rax,(%rsp)\n\t"
1712 amd64_emit_mul (void)
1718 amd64_emit_lsh (void)
1724 amd64_emit_rsh_signed (void)
1730 amd64_emit_rsh_unsigned (void)
1736 amd64_emit_ext (int arg
)
1741 EMIT_ASM (amd64_ext_8
,
1747 EMIT_ASM (amd64_ext_16
,
1752 EMIT_ASM (amd64_ext_32
,
1761 amd64_emit_log_not (void)
1763 EMIT_ASM (amd64_log_not
,
1764 "test %rax,%rax\n\t"
1770 amd64_emit_bit_and (void)
1772 EMIT_ASM (amd64_and
,
1773 "and (%rsp),%rax\n\t"
1774 "lea 0x8(%rsp),%rsp");
1778 amd64_emit_bit_or (void)
1781 "or (%rsp),%rax\n\t"
1782 "lea 0x8(%rsp),%rsp");
1786 amd64_emit_bit_xor (void)
1788 EMIT_ASM (amd64_xor
,
1789 "xor (%rsp),%rax\n\t"
1790 "lea 0x8(%rsp),%rsp");
1794 amd64_emit_bit_not (void)
1796 EMIT_ASM (amd64_bit_not
,
1797 "xorq $0xffffffffffffffff,%rax");
1801 amd64_emit_equal (void)
1803 EMIT_ASM (amd64_equal
,
1804 "cmp %rax,(%rsp)\n\t"
1805 "je .Lamd64_equal_true\n\t"
1807 "jmp .Lamd64_equal_end\n\t"
1808 ".Lamd64_equal_true:\n\t"
1810 ".Lamd64_equal_end:\n\t"
1811 "lea 0x8(%rsp),%rsp");
1815 amd64_emit_less_signed (void)
1817 EMIT_ASM (amd64_less_signed
,
1818 "cmp %rax,(%rsp)\n\t"
1819 "jl .Lamd64_less_signed_true\n\t"
1821 "jmp .Lamd64_less_signed_end\n\t"
1822 ".Lamd64_less_signed_true:\n\t"
1824 ".Lamd64_less_signed_end:\n\t"
1825 "lea 0x8(%rsp),%rsp");
1829 amd64_emit_less_unsigned (void)
1831 EMIT_ASM (amd64_less_unsigned
,
1832 "cmp %rax,(%rsp)\n\t"
1833 "jb .Lamd64_less_unsigned_true\n\t"
1835 "jmp .Lamd64_less_unsigned_end\n\t"
1836 ".Lamd64_less_unsigned_true:\n\t"
1838 ".Lamd64_less_unsigned_end:\n\t"
1839 "lea 0x8(%rsp),%rsp");
1843 amd64_emit_ref (int size
)
1848 EMIT_ASM (amd64_ref1
,
1852 EMIT_ASM (amd64_ref2
,
1856 EMIT_ASM (amd64_ref4
,
1857 "movl (%rax),%eax");
1860 EMIT_ASM (amd64_ref8
,
1861 "movq (%rax),%rax");
1867 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1869 EMIT_ASM (amd64_if_goto
,
1873 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1881 amd64_emit_goto (int *offset_p
, int *size_p
)
1883 EMIT_ASM (amd64_goto
,
1884 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1892 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1894 int diff
= (to
- (from
+ size
));
1895 unsigned char buf
[sizeof (int)];
1903 memcpy (buf
, &diff
, sizeof (int));
1904 target_write_memory (from
, buf
, sizeof (int));
1908 amd64_emit_const (LONGEST num
)
1910 unsigned char buf
[16];
1912 CORE_ADDR buildaddr
= current_insn_ptr
;
1915 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1916 memcpy (&buf
[i
], &num
, sizeof (num
));
1918 append_insns (&buildaddr
, i
, buf
);
1919 current_insn_ptr
= buildaddr
;
1923 amd64_emit_call (CORE_ADDR fn
)
1925 unsigned char buf
[16];
1927 CORE_ADDR buildaddr
;
1930 /* The destination function being in the shared library, may be
1931 >31-bits away off the compiled code pad. */
1933 buildaddr
= current_insn_ptr
;
1935 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1939 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1941 /* Offset is too large for a call. Use callq, but that requires
1942 a register, so avoid it if possible. Use r10, since it is
1943 call-clobbered, we don't have to push/pop it. */
1944 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1946 memcpy (buf
+ i
, &fn
, 8);
1948 buf
[i
++] = 0xff; /* callq *%r10 */
1953 int offset32
= offset64
; /* we know we can't overflow here. */
1955 buf
[i
++] = 0xe8; /* call <reladdr> */
1956 memcpy (buf
+ i
, &offset32
, 4);
1960 append_insns (&buildaddr
, i
, buf
);
1961 current_insn_ptr
= buildaddr
;
1965 amd64_emit_reg (int reg
)
1967 unsigned char buf
[16];
1969 CORE_ADDR buildaddr
;
1971 /* Assume raw_regs is still in %rdi. */
1972 buildaddr
= current_insn_ptr
;
1974 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1975 memcpy (&buf
[i
], ®
, sizeof (reg
));
1977 append_insns (&buildaddr
, i
, buf
);
1978 current_insn_ptr
= buildaddr
;
1979 amd64_emit_call (get_raw_reg_func_addr ());
1983 amd64_emit_pop (void)
1985 EMIT_ASM (amd64_pop
,
1990 amd64_emit_stack_flush (void)
1992 EMIT_ASM (amd64_stack_flush
,
1997 amd64_emit_zero_ext (int arg
)
2002 EMIT_ASM (amd64_zero_ext_8
,
2006 EMIT_ASM (amd64_zero_ext_16
,
2007 "and $0xffff,%rax");
2010 EMIT_ASM (amd64_zero_ext_32
,
2011 "mov $0xffffffff,%rcx\n\t"
2020 amd64_emit_swap (void)
2022 EMIT_ASM (amd64_swap
,
2029 amd64_emit_stack_adjust (int n
)
2031 unsigned char buf
[16];
2033 CORE_ADDR buildaddr
= current_insn_ptr
;
2036 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
2040 /* This only handles adjustments up to 16, but we don't expect any more. */
2042 append_insns (&buildaddr
, i
, buf
);
2043 current_insn_ptr
= buildaddr
;
2046 /* FN's prototype is `LONGEST(*fn)(int)'. */
2049 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2051 unsigned char buf
[16];
2053 CORE_ADDR buildaddr
;
2055 buildaddr
= current_insn_ptr
;
2057 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2058 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2060 append_insns (&buildaddr
, i
, buf
);
2061 current_insn_ptr
= buildaddr
;
2062 amd64_emit_call (fn
);
2065 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2068 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2070 unsigned char buf
[16];
2072 CORE_ADDR buildaddr
;
2074 buildaddr
= current_insn_ptr
;
2076 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2077 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2079 append_insns (&buildaddr
, i
, buf
);
2080 current_insn_ptr
= buildaddr
;
2081 EMIT_ASM (amd64_void_call_2_a
,
2082 /* Save away a copy of the stack top. */
2084 /* Also pass top as the second argument. */
2086 amd64_emit_call (fn
);
2087 EMIT_ASM (amd64_void_call_2_b
,
2088 /* Restore the stack top, %rax may have been trashed. */
2093 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2096 "cmp %rax,(%rsp)\n\t"
2097 "jne .Lamd64_eq_fallthru\n\t"
2098 "lea 0x8(%rsp),%rsp\n\t"
2100 /* jmp, but don't trust the assembler to choose the right jump */
2101 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2102 ".Lamd64_eq_fallthru:\n\t"
2103 "lea 0x8(%rsp),%rsp\n\t"
2113 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2116 "cmp %rax,(%rsp)\n\t"
2117 "je .Lamd64_ne_fallthru\n\t"
2118 "lea 0x8(%rsp),%rsp\n\t"
2120 /* jmp, but don't trust the assembler to choose the right jump */
2121 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2122 ".Lamd64_ne_fallthru:\n\t"
2123 "lea 0x8(%rsp),%rsp\n\t"
2133 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2136 "cmp %rax,(%rsp)\n\t"
2137 "jnl .Lamd64_lt_fallthru\n\t"
2138 "lea 0x8(%rsp),%rsp\n\t"
2140 /* jmp, but don't trust the assembler to choose the right jump */
2141 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2142 ".Lamd64_lt_fallthru:\n\t"
2143 "lea 0x8(%rsp),%rsp\n\t"
2153 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2156 "cmp %rax,(%rsp)\n\t"
2157 "jnle .Lamd64_le_fallthru\n\t"
2158 "lea 0x8(%rsp),%rsp\n\t"
2160 /* jmp, but don't trust the assembler to choose the right jump */
2161 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2162 ".Lamd64_le_fallthru:\n\t"
2163 "lea 0x8(%rsp),%rsp\n\t"
2173 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2176 "cmp %rax,(%rsp)\n\t"
2177 "jng .Lamd64_gt_fallthru\n\t"
2178 "lea 0x8(%rsp),%rsp\n\t"
2180 /* jmp, but don't trust the assembler to choose the right jump */
2181 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2182 ".Lamd64_gt_fallthru:\n\t"
2183 "lea 0x8(%rsp),%rsp\n\t"
2193 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2196 "cmp %rax,(%rsp)\n\t"
2197 "jnge .Lamd64_ge_fallthru\n\t"
2198 ".Lamd64_ge_jump:\n\t"
2199 "lea 0x8(%rsp),%rsp\n\t"
2201 /* jmp, but don't trust the assembler to choose the right jump */
2202 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2203 ".Lamd64_ge_fallthru:\n\t"
2204 "lea 0x8(%rsp),%rsp\n\t"
2213 struct emit_ops amd64_emit_ops
=
2215 amd64_emit_prologue
,
2216 amd64_emit_epilogue
,
2221 amd64_emit_rsh_signed
,
2222 amd64_emit_rsh_unsigned
,
2230 amd64_emit_less_signed
,
2231 amd64_emit_less_unsigned
,
2235 amd64_write_goto_address
,
2240 amd64_emit_stack_flush
,
2241 amd64_emit_zero_ext
,
2243 amd64_emit_stack_adjust
,
2244 amd64_emit_int_call_1
,
2245 amd64_emit_void_call_2
,
2254 #endif /* __x86_64__ */
2257 i386_emit_prologue (void)
2259 EMIT_ASM32 (i386_prologue
,
2263 /* At this point, the raw regs base address is at 8(%ebp), and the
2264 value pointer is at 12(%ebp). */
2268 i386_emit_epilogue (void)
2270 EMIT_ASM32 (i386_epilogue
,
2271 "mov 12(%ebp),%ecx\n\t"
2272 "mov %eax,(%ecx)\n\t"
2273 "mov %ebx,0x4(%ecx)\n\t"
2281 i386_emit_add (void)
2283 EMIT_ASM32 (i386_add
,
2284 "add (%esp),%eax\n\t"
2285 "adc 0x4(%esp),%ebx\n\t"
2286 "lea 0x8(%esp),%esp");
2290 i386_emit_sub (void)
2292 EMIT_ASM32 (i386_sub
,
2293 "subl %eax,(%esp)\n\t"
2294 "sbbl %ebx,4(%esp)\n\t"
2300 i386_emit_mul (void)
2306 i386_emit_lsh (void)
2312 i386_emit_rsh_signed (void)
2318 i386_emit_rsh_unsigned (void)
2324 i386_emit_ext (int arg
)
2329 EMIT_ASM32 (i386_ext_8
,
2332 "movl %eax,%ebx\n\t"
2336 EMIT_ASM32 (i386_ext_16
,
2338 "movl %eax,%ebx\n\t"
2342 EMIT_ASM32 (i386_ext_32
,
2343 "movl %eax,%ebx\n\t"
2352 i386_emit_log_not (void)
2354 EMIT_ASM32 (i386_log_not
,
2356 "test %eax,%eax\n\t"
2363 i386_emit_bit_and (void)
2365 EMIT_ASM32 (i386_and
,
2366 "and (%esp),%eax\n\t"
2367 "and 0x4(%esp),%ebx\n\t"
2368 "lea 0x8(%esp),%esp");
2372 i386_emit_bit_or (void)
2374 EMIT_ASM32 (i386_or
,
2375 "or (%esp),%eax\n\t"
2376 "or 0x4(%esp),%ebx\n\t"
2377 "lea 0x8(%esp),%esp");
2381 i386_emit_bit_xor (void)
2383 EMIT_ASM32 (i386_xor
,
2384 "xor (%esp),%eax\n\t"
2385 "xor 0x4(%esp),%ebx\n\t"
2386 "lea 0x8(%esp),%esp");
2390 i386_emit_bit_not (void)
2392 EMIT_ASM32 (i386_bit_not
,
2393 "xor $0xffffffff,%eax\n\t"
2394 "xor $0xffffffff,%ebx\n\t");
2398 i386_emit_equal (void)
2400 EMIT_ASM32 (i386_equal
,
2401 "cmpl %ebx,4(%esp)\n\t"
2402 "jne .Li386_equal_false\n\t"
2403 "cmpl %eax,(%esp)\n\t"
2404 "je .Li386_equal_true\n\t"
2405 ".Li386_equal_false:\n\t"
2407 "jmp .Li386_equal_end\n\t"
2408 ".Li386_equal_true:\n\t"
2410 ".Li386_equal_end:\n\t"
2412 "lea 0x8(%esp),%esp");
2416 i386_emit_less_signed (void)
2418 EMIT_ASM32 (i386_less_signed
,
2419 "cmpl %ebx,4(%esp)\n\t"
2420 "jl .Li386_less_signed_true\n\t"
2421 "jne .Li386_less_signed_false\n\t"
2422 "cmpl %eax,(%esp)\n\t"
2423 "jl .Li386_less_signed_true\n\t"
2424 ".Li386_less_signed_false:\n\t"
2426 "jmp .Li386_less_signed_end\n\t"
2427 ".Li386_less_signed_true:\n\t"
2429 ".Li386_less_signed_end:\n\t"
2431 "lea 0x8(%esp),%esp");
2435 i386_emit_less_unsigned (void)
2437 EMIT_ASM32 (i386_less_unsigned
,
2438 "cmpl %ebx,4(%esp)\n\t"
2439 "jb .Li386_less_unsigned_true\n\t"
2440 "jne .Li386_less_unsigned_false\n\t"
2441 "cmpl %eax,(%esp)\n\t"
2442 "jb .Li386_less_unsigned_true\n\t"
2443 ".Li386_less_unsigned_false:\n\t"
2445 "jmp .Li386_less_unsigned_end\n\t"
2446 ".Li386_less_unsigned_true:\n\t"
2448 ".Li386_less_unsigned_end:\n\t"
2450 "lea 0x8(%esp),%esp");
2454 i386_emit_ref (int size
)
2459 EMIT_ASM32 (i386_ref1
,
2463 EMIT_ASM32 (i386_ref2
,
2467 EMIT_ASM32 (i386_ref4
,
2468 "movl (%eax),%eax");
2471 EMIT_ASM32 (i386_ref8
,
2472 "movl 4(%eax),%ebx\n\t"
2473 "movl (%eax),%eax");
2479 i386_emit_if_goto (int *offset_p
, int *size_p
)
2481 EMIT_ASM32 (i386_if_goto
,
2487 /* Don't trust the assembler to choose the right jump */
2488 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2491 *offset_p
= 11; /* be sure that this matches the sequence above */
2497 i386_emit_goto (int *offset_p
, int *size_p
)
2499 EMIT_ASM32 (i386_goto
,
2500 /* Don't trust the assembler to choose the right jump */
2501 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2509 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2511 int diff
= (to
- (from
+ size
));
2512 unsigned char buf
[sizeof (int)];
2514 /* We're only doing 4-byte sizes at the moment. */
2521 memcpy (buf
, &diff
, sizeof (int));
2522 target_write_memory (from
, buf
, sizeof (int));
2526 i386_emit_const (LONGEST num
)
2528 unsigned char buf
[16];
2530 CORE_ADDR buildaddr
= current_insn_ptr
;
2533 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2534 lo
= num
& 0xffffffff;
2535 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2537 hi
= ((num
>> 32) & 0xffffffff);
2540 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2541 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2546 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2548 append_insns (&buildaddr
, i
, buf
);
2549 current_insn_ptr
= buildaddr
;
2553 i386_emit_call (CORE_ADDR fn
)
2555 unsigned char buf
[16];
2557 CORE_ADDR buildaddr
;
2559 buildaddr
= current_insn_ptr
;
2561 buf
[i
++] = 0xe8; /* call <reladdr> */
2562 offset
= ((int) fn
) - (buildaddr
+ 5);
2563 memcpy (buf
+ 1, &offset
, 4);
2564 append_insns (&buildaddr
, 5, buf
);
2565 current_insn_ptr
= buildaddr
;
2569 i386_emit_reg (int reg
)
2571 unsigned char buf
[16];
2573 CORE_ADDR buildaddr
;
2575 EMIT_ASM32 (i386_reg_a
,
2577 buildaddr
= current_insn_ptr
;
2579 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2580 memcpy (&buf
[i
], ®
, sizeof (reg
));
2582 append_insns (&buildaddr
, i
, buf
);
2583 current_insn_ptr
= buildaddr
;
2584 EMIT_ASM32 (i386_reg_b
,
2585 "mov %eax,4(%esp)\n\t"
2586 "mov 8(%ebp),%eax\n\t"
2588 i386_emit_call (get_raw_reg_func_addr ());
2589 EMIT_ASM32 (i386_reg_c
,
2591 "lea 0x8(%esp),%esp");
2595 i386_emit_pop (void)
2597 EMIT_ASM32 (i386_pop
,
2603 i386_emit_stack_flush (void)
2605 EMIT_ASM32 (i386_stack_flush
,
2611 i386_emit_zero_ext (int arg
)
2616 EMIT_ASM32 (i386_zero_ext_8
,
2617 "and $0xff,%eax\n\t"
2621 EMIT_ASM32 (i386_zero_ext_16
,
2622 "and $0xffff,%eax\n\t"
2626 EMIT_ASM32 (i386_zero_ext_32
,
2635 i386_emit_swap (void)
2637 EMIT_ASM32 (i386_swap
,
2647 i386_emit_stack_adjust (int n
)
2649 unsigned char buf
[16];
2651 CORE_ADDR buildaddr
= current_insn_ptr
;
2654 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2658 append_insns (&buildaddr
, i
, buf
);
2659 current_insn_ptr
= buildaddr
;
2662 /* FN's prototype is `LONGEST(*fn)(int)'. */
2665 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2667 unsigned char buf
[16];
2669 CORE_ADDR buildaddr
;
2671 EMIT_ASM32 (i386_int_call_1_a
,
2672 /* Reserve a bit of stack space. */
2674 /* Put the one argument on the stack. */
2675 buildaddr
= current_insn_ptr
;
2677 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2680 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2682 append_insns (&buildaddr
, i
, buf
);
2683 current_insn_ptr
= buildaddr
;
2684 i386_emit_call (fn
);
2685 EMIT_ASM32 (i386_int_call_1_c
,
2687 "lea 0x8(%esp),%esp");
2690 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2693 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2695 unsigned char buf
[16];
2697 CORE_ADDR buildaddr
;
2699 EMIT_ASM32 (i386_void_call_2_a
,
2700 /* Preserve %eax only; we don't have to worry about %ebx. */
2702 /* Reserve a bit of stack space for arguments. */
2703 "sub $0x10,%esp\n\t"
2704 /* Copy "top" to the second argument position. (Note that
2705 we can't assume function won't scribble on its
2706 arguments, so don't try to restore from this.) */
2707 "mov %eax,4(%esp)\n\t"
2708 "mov %ebx,8(%esp)");
2709 /* Put the first argument on the stack. */
2710 buildaddr
= current_insn_ptr
;
2712 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2715 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2717 append_insns (&buildaddr
, i
, buf
);
2718 current_insn_ptr
= buildaddr
;
2719 i386_emit_call (fn
);
2720 EMIT_ASM32 (i386_void_call_2_b
,
2721 "lea 0x10(%esp),%esp\n\t"
2722 /* Restore original stack top. */
2728 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2731 /* Check low half first, more likely to be decider */
2732 "cmpl %eax,(%esp)\n\t"
2733 "jne .Leq_fallthru\n\t"
2734 "cmpl %ebx,4(%esp)\n\t"
2735 "jne .Leq_fallthru\n\t"
2736 "lea 0x8(%esp),%esp\n\t"
2739 /* jmp, but don't trust the assembler to choose the right jump */
2740 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2741 ".Leq_fallthru:\n\t"
2742 "lea 0x8(%esp),%esp\n\t"
2753 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2756 /* Check low half first, more likely to be decider */
2757 "cmpl %eax,(%esp)\n\t"
2759 "cmpl %ebx,4(%esp)\n\t"
2760 "je .Lne_fallthru\n\t"
2762 "lea 0x8(%esp),%esp\n\t"
2765 /* jmp, but don't trust the assembler to choose the right jump */
2766 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2767 ".Lne_fallthru:\n\t"
2768 "lea 0x8(%esp),%esp\n\t"
2779 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2782 "cmpl %ebx,4(%esp)\n\t"
2784 "jne .Llt_fallthru\n\t"
2785 "cmpl %eax,(%esp)\n\t"
2786 "jnl .Llt_fallthru\n\t"
2788 "lea 0x8(%esp),%esp\n\t"
2791 /* jmp, but don't trust the assembler to choose the right jump */
2792 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2793 ".Llt_fallthru:\n\t"
2794 "lea 0x8(%esp),%esp\n\t"
2805 i386_emit_le_goto (int *offset_p
, int *size_p
)
2808 "cmpl %ebx,4(%esp)\n\t"
2810 "jne .Lle_fallthru\n\t"
2811 "cmpl %eax,(%esp)\n\t"
2812 "jnle .Lle_fallthru\n\t"
2814 "lea 0x8(%esp),%esp\n\t"
2817 /* jmp, but don't trust the assembler to choose the right jump */
2818 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2819 ".Lle_fallthru:\n\t"
2820 "lea 0x8(%esp),%esp\n\t"
2831 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2834 "cmpl %ebx,4(%esp)\n\t"
2836 "jne .Lgt_fallthru\n\t"
2837 "cmpl %eax,(%esp)\n\t"
2838 "jng .Lgt_fallthru\n\t"
2840 "lea 0x8(%esp),%esp\n\t"
2843 /* jmp, but don't trust the assembler to choose the right jump */
2844 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2845 ".Lgt_fallthru:\n\t"
2846 "lea 0x8(%esp),%esp\n\t"
2857 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2860 "cmpl %ebx,4(%esp)\n\t"
2862 "jne .Lge_fallthru\n\t"
2863 "cmpl %eax,(%esp)\n\t"
2864 "jnge .Lge_fallthru\n\t"
2866 "lea 0x8(%esp),%esp\n\t"
2869 /* jmp, but don't trust the assembler to choose the right jump */
2870 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2871 ".Lge_fallthru:\n\t"
2872 "lea 0x8(%esp),%esp\n\t"
2882 struct emit_ops i386_emit_ops
=
2890 i386_emit_rsh_signed
,
2891 i386_emit_rsh_unsigned
,
2899 i386_emit_less_signed
,
2900 i386_emit_less_unsigned
,
2904 i386_write_goto_address
,
2909 i386_emit_stack_flush
,
2912 i386_emit_stack_adjust
,
2913 i386_emit_int_call_1
,
2914 i386_emit_void_call_2
,
2925 x86_target::emit_ops ()
2928 if (is_64bit_tdesc ())
2929 return &amd64_emit_ops
;
2932 return &i386_emit_ops
;
2935 /* Implementation of target ops method "sw_breakpoint_from_kind". */
2938 x86_target::sw_breakpoint_from_kind (int kind
, int *size
)
2940 *size
= x86_breakpoint_len
;
2941 return x86_breakpoint
;
2945 x86_target::low_supports_range_stepping ()
2951 x86_target::get_ipa_tdesc_idx ()
2953 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2954 const struct target_desc
*tdesc
= regcache
->tdesc
;
2957 return amd64_get_ipa_tdesc_idx (tdesc
);
2960 if (tdesc
== tdesc_i386_linux_no_xml
)
2961 return X86_TDESC_SSE
;
2963 return i386_get_ipa_tdesc_idx (tdesc
);
2966 /* The linux target ops object. */
2968 linux_process_target
*the_linux_target
= &the_x86_target
;
2971 initialize_low_arch (void)
2973 /* Initialize the Linux target descriptions. */
2975 tdesc_amd64_linux_no_xml
= allocate_target_description ();
2976 copy_target_description (tdesc_amd64_linux_no_xml
,
2977 amd64_linux_read_description (X86_XSTATE_SSE_MASK
,
2979 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2982 tdesc_i386_linux_no_xml
= allocate_target_description ();
2983 copy_target_description (tdesc_i386_linux_no_xml
,
2984 i386_linux_read_description (X86_XSTATE_SSE_MASK
));
2985 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2987 initialize_regsets_info (&x86_regsets_info
);