opcodes/ChangeLog

   1 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/21594
   4         * i386-dis.c (OP_E_register): Check valid bnd register.
   5         (OP_G): Likewise.
   6
   7 2017-06-15  Nick Clifton  <nickc@redhat.com>
   8
   9         PR binutils/21595
  10         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
  11         range value.
  12
  13 2017-06-15  Nick Clifton  <nickc@redhat.com>
  14
  15         PR binutils/21588
  16         * rl78-decode.opc (OP_BUF_LEN): Define.
  17         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
  18         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
  19         array.
  20         * rl78-decode.c: Regenerate.
  21
  22 2017-06-15  Nick Clifton  <nickc@redhat.com>
  23
  24         PR binutils/21586
  25         * bfin-dis.c (gregs): Clip index to prevent overflow.
  26         (regs): Likewise.
  27         (regs_lo): Likewise.
  28         (regs_hi): Likewise.
  29
  30 2017-06-14  Nick Clifton  <nickc@redhat.com>
  31
  32         PR binutils/21576
  33         * score7-dis.c (score_opcodes): Add sentinel.
  34
  35 2017-06-14  Yao Qi  <yao.qi@linaro.org>
  36
  37         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
  38         * arm-dis.c: Likewise.
  39         * ia64-dis.c: Likewise.
  40         * mips-dis.c: Likewise.
  41         * spu-dis.c: Likewise.
  42         * disassemble.h (print_insn_aarch64): New declaration, moved from
  43         include/dis-asm.h.
  44         (print_insn_big_arm, print_insn_big_mips): Likewise.
  45         (print_insn_i386, print_insn_ia64): Likewise.
  46         (print_insn_little_arm, print_insn_little_mips): Likewise.
  47
  48 2017-06-14  Nick Clifton  <nickc@redhat.com>
  49
  50         PR binutils/21587
  51         * rx-decode.opc: Include libiberty.h
  52         (GET_SCALE): New macro - validates access to SCALE array.
  53         (GET_PSCALE): New macro - validates access to PSCALE array.
  54         (DIs, SIs, S2Is, rx_disp): Use new macros.
  55         * rx-decode.c: Regenerate.
  56
  57 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  58
  59         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
  60
  61 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
  62
  63         * arc-dis.c (enforced_isa_mask): Declare.
  64         (cpu_types): Likewise.
  65         (parse_cpu_option): New function.
  66         (parse_disassembler_options): Use it.
  67         (print_insn_arc): Use enforced_isa_mask.
  68         (print_arc_disassembler_options): Document new options.
  69
  70 2017-05-24  Yao Qi  <yao.qi@linaro.org>
  71
  72         * alpha-dis.c: Include disassemble.h, don't include
  73         dis-asm.h.
  74         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
  75         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
  76         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
  77         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
  78         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
  79         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
  80         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
  81         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
  82         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
  83         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
  84         * moxie-dis.c, msp430-dis.c, mt-dis.c:
  85         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
  86         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
  87         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
  88         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
  89         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
  90         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
  91         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
  92         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
  93         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
  94         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
  95         * z80-dis.c, z8k-dis.c: Likewise.
  96         * disassemble.h: New file.
  97
  98 2017-05-24  Yao Qi  <yao.qi@linaro.org>
  99
 100         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 101         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 102
 103 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 104
 105         * disassemble.c (disassembler): Add arguments a, big and mach.
 106         Use them.
 107
 108 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         * i386-dis.c (NOTRACK_Fixup): New.
 111         (NOTRACK): Likewise.
 112         (NOTRACK_PREFIX): Likewise.
 113         (last_active_prefix): Likewise.
 114         (reg_table): Use NOTRACK on indirect call and jmp.
 115         (ckprefix): Set last_active_prefix.
 116         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 117         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 118         * i386-opc.h (NoTrackPrefixOk): New.
 119         (i386_opcode_modifier): Add notrackprefixok.
 120         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 121         Add notrack.
 122         * i386-tbl.h: Regenerated.
 123
 124 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 125
 126         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 127         (X_IMM2): Define.
 128         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 129         bfd_mach_sparc_v9m8.
 130         (print_insn_sparc): Handle new operand types.
 131         * sparc-opc.c (MASK_M8): Define.
 132         (v6): Add MASK_M8.
 133         (v6notlet): Likewise.
 134         (v7): Likewise.
 135         (v8): Likewise.
 136         (v9): Likewise.
 137         (v9a): Likewise.
 138         (v9b): Likewise.
 139         (v9c): Likewise.
 140         (v9d): Likewise.
 141         (v9e): Likewise.
 142         (v9v): Likewise.
 143         (v9m): Likewise.
 144         (v9andleon): Likewise.
 145         (m8): Define.
 146         (HWS_VM8): Define.
 147         (HWS2_VM8): Likewise.
 148         (sparc_opcode_archs): Add entry for "m8".
 149         (sparc_opcodes): Add OSA2017 and M8 instructions
 150         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 151         fpx{ll,ra,rl}64x,
 152         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 153         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 154         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 155         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 156         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 157         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 158         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 159         ASI_CORE_SELECT_COMMIT_NHT.
 160
 161 2017-05-18  Alan Modra  <amodra@gmail.com>
 162
 163         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 164         * aarch64-dis.c: Likewise.
 165         * aarch64-gen.c: Likewise.
 166         * aarch64-opc.c: Likewise.
 167
 168 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 169             Matthew Fortune  <matthew.fortune@imgtec.com>
 170
 171         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 172         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 173         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 174         (print_insn_arg) <OP_REG28>: Add handler.
 175         (validate_insn_args) <OP_REG28>: Handle.
 176         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 177         32-bit encoding and 9-bit immediates.
 178         (print_insn_mips16): Handle MIPS16 instructions that require
 179         32-bit encoding and MFC0/MTC0 operand decoding.
 180         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 181         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 182         (RD_C0, WR_C0, E2, E2MT): New macros.
 183         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 184         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 185         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 186         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 187         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 188         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 189         instructions, "swl", "swr", "sync" and its "sync_acquire",
 190         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 191         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 192         regular/extended entries for original MIPS16 ISA revision
 193         instructions whose extended forms are subdecoded in the MIPS16e2
 194         ISA revision: "li", "sll" and "srl".
 195
 196 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 197
 198         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 199         reference in CP0 move operand decoding.
 200
 201 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 202
 203         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 204         type to hexadecimal.
 205         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 206
 207 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 208
 209         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 210         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 211         "sync_rmb" and "sync_wmb" as aliases.
 212         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 213         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 214
 215 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 216
 217         * arc-dis.c (parse_option): Update quarkse_em option..
 218         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 219         QUARKSE1.
 220         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 221
 222 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 223
 224         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 225
 226 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 227
 228         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 229         register.
 230
 231 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 232
 233         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 234         and branches and not synthetic data instructions.
 235
 236 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 237
 238         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 239
 240 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 241
 242         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 243         * arc-opc.c (insert_r13el): New function.
 244         (R13_EL): Define.
 245         * arc-tbl.h: Add new enter/leave variants.
 246
 247 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 248
 249         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 250
 251 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 252
 253         * mips-dis.c (print_mips_disassembler_options): Add
 254         `no-aliases'.
 255
 256 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 257
 258         * mips16-opc.c (AL): New macro.
 259         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 260         of "ld" and "lw" as aliases.
 261
 262 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 263
 264         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 265         arguments.
 266
 267 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 268             Alan Modra  <amodra@gmail.com>
 269
 270         * ppc-opc.c (ELEV): Define.
 271         (vle_opcodes): Add se_rfgi and e_sc.
 272         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 273         for E200Z4.
 274
 275 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 276
 277         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 278
 279 2017-04-21  Nick Clifton  <nickc@redhat.com>
 280
 281         PR binutils/21380
 282         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 283         LD3R and LD4R.
 284
 285 2017-04-13  Alan Modra  <amodra@gmail.com>
 286
 287         * epiphany-desc.c: Regenerate.
 288         * fr30-desc.c: Regenerate.
 289         * frv-desc.c: Regenerate.
 290         * ip2k-desc.c: Regenerate.
 291         * iq2000-desc.c: Regenerate.
 292         * lm32-desc.c: Regenerate.
 293         * m32c-desc.c: Regenerate.
 294         * m32r-desc.c: Regenerate.
 295         * mep-desc.c: Regenerate.
 296         * mt-desc.c: Regenerate.
 297         * or1k-desc.c: Regenerate.
 298         * xc16x-desc.c: Regenerate.
 299         * xstormy16-desc.c: Regenerate.
 300
 301 2017-04-11  Alan Modra  <amodra@gmail.com>
 302
 303         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 304         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 305         PPC_OPCODE_TMR for e6500.
 306         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 307         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 308         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 309         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 310         (PPCHTM): Define as PPC_OPCODE_POWER8.
 311         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 312
 313 2017-04-10  Alan Modra  <amodra@gmail.com>
 314
 315         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 316         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 317         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 318         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 319
 320 2017-04-09  Pip Cet  <pipcet@gmail.com>
 321
 322         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 323         appropriate floating-point precision directly.
 324
 325 2017-04-07  Alan Modra  <amodra@gmail.com>
 326
 327         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 328         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 329         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 330         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 331         vector instructions with E6500 not PPCVEC2.
 332
 333 2017-04-06  Pip Cet  <pipcet@gmail.com>
 334
 335         * Makefile.am: Add wasm32-dis.c.
 336         * configure.ac: Add wasm32-dis.c to wasm32 target.
 337         * disassemble.c: Add wasm32 disassembler code.
 338         * wasm32-dis.c: New file.
 339         * Makefile.in: Regenerate.
 340         * configure: Regenerate.
 341         * po/POTFILES.in: Regenerate.
 342         * po/opcodes.pot: Regenerate.
 343
 344 2017-04-05  Pedro Alves  <palves@redhat.com>
 345
 346         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 347         * arm-dis.c (parse_arm_disassembler_options): Constify.
 348         * ppc-dis.c (powerpc_init_dialect): Constify local.
 349         * vax-dis.c (parse_disassembler_options): Constify.
 350
 351 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 352
 353         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 354         RISCV_GP_SYMBOL.
 355
 356 2017-03-30  Pip Cet  <pipcet@gmail.com>
 357
 358         * configure.ac: Add (empty) bfd_wasm32_arch target.
 359         * configure: Regenerate
 360         * po/opcodes.pot: Regenerate.
 361
 362 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 363
 364         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 365         OSA2015.
 366         * opcodes/sparc-opc.c (asi_table): New ASIs.
 367
 368 2017-03-29  Alan Modra  <amodra@gmail.com>
 369
 370         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 371         "raw" option.
 372         (lookup_powerpc): Don't special case -1 dialect.  Handle
 373         PPC_OPCODE_RAW.
 374         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 375         lookup_powerpc call, pass it on second.
 376
 377 2017-03-27  Alan Modra  <amodra@gmail.com>
 378
 379         PR 21303
 380         * ppc-dis.c (struct ppc_mopt): Comment.
 381         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 382
 383 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 384
 385         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 386         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 387         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 388         (insert_nps_misc_imm_offset): New function.
 389         (extract_nps_misc imm_offset): New function.
 390         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 391         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 392
 393 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 394
 395         * s390-mkopc.c (main): Remove vx2 check.
 396         * s390-opc.txt: Remove vx2 instruction flags.
 397
 398 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 399
 400         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 401         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 402         (insert_nps_imm_offset): New function.
 403         (extract_nps_imm_offset): New function.
 404         (insert_nps_imm_entry): New function.
 405         (extract_nps_imm_entry): New function.
 406
 407 2017-03-17  Alan Modra  <amodra@gmail.com>
 408
 409         PR 21248
 410         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 411         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 412         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 413
 414 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 415
 416         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 417         <c.andi>: Likewise.
 418         <c.addiw> Likewise.
 419
 420 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 421
 422         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 423
 424 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 425
 426         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 427         <srl> Likewise.
 428         <srai> Likewise.
 429         <sra> Likewise.
 430
 431 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 432
 433         * i386-gen.c (opcode_modifiers): Replace S with Load.
 434         * i386-opc.h (S): Removed.
 435         (Load): New.
 436         (i386_opcode_modifier): Replace s with load.
 437         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 438         and {evex}.  Replace S with Load.
 439         * i386-tbl.h: Regenerated.
 440
 441 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 442
 443         * i386-opc.tbl: Use CpuCET on rdsspq.
 444         * i386-tbl.h: Regenerated.
 445
 446 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 447
 448         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 449         <vsx>: Do not use PPC_OPCODE_VSX3;
 450
 451 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 452
 453         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 454
 455 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 456
 457         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 458         (MOD_0F1E_PREFIX_1): Likewise.
 459         (MOD_0F38F5_PREFIX_2): Likewise.
 460         (MOD_0F38F6_PREFIX_0): Likewise.
 461         (RM_0F1E_MOD_3_REG_7): Likewise.
 462         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 463         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 464         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 465         (PREFIX_0F1E): Likewise.
 466         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 467         (PREFIX_0F38F5): Likewise.
 468         (dis386_twobyte): Use PREFIX_0F1E.
 469         (reg_table): Add REG_0F1E_MOD_3.
 470         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 471         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 472         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 473         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 474         (three_byte_table): Use PREFIX_0F38F5.
 475         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 476         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 477         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 478         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 479         PREFIX_MOD_3_0F01_REG_5_RM_2.
 480         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 481         (cpu_flags): Add CpuCET.
 482         * i386-opc.h (CpuCET): New enum.
 483         (CpuUnused): Commented out.
 484         (i386_cpu_flags): Add cpucet.
 485         * i386-opc.tbl: Add Intel CET instructions.
 486         * i386-init.h: Regenerated.
 487         * i386-tbl.h: Likewise.
 488
 489 2017-03-06  Alan Modra  <amodra@gmail.com>
 490
 491         PR 21124
 492         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 493         (extract_raq, extract_ras, extract_rbx): New functions.
 494         (powerpc_operands): Use opposite corresponding insert function.
 495         (Q_MASK): Define.
 496         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 497         register restriction.
 498
 499 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 500
 501         * disassemble.c Include "safe-ctype.h".
 502         (disassemble_init_for_target): Handle s390 init.
 503         (remove_whitespace_and_extra_commas): New function.
 504         (disassembler_options_cmp): Likewise.
 505         * arm-dis.c: Include "libiberty.h".
 506         (NUM_ELEM): Delete.
 507         (regnames): Use long disassembler style names.
 508         Add force-thumb and no-force-thumb options.
 509         (NUM_ARM_REGNAMES): Rename from this...
 510         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 511         (get_arm_regname_num_options): Delete.
 512         (set_arm_regname_option): Likewise.
 513         (get_arm_regnames): Likewise.
 514         (parse_disassembler_options): Likewise.
 515         (parse_arm_disassembler_option): Rename from this...
 516         (parse_arm_disassembler_options): ...to this.  Make static.
 517         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 518         (print_insn): Use parse_arm_disassembler_options.
 519         (disassembler_options_arm): New function.
 520         (print_arm_disassembler_options): Handle updated regnames.
 521         * ppc-dis.c: Include "libiberty.h".
 522         (ppc_opts): Add "32" and "64" entries.
 523         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 524         (powerpc_init_dialect): Add break to switch statement.
 525         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 526         (disassembler_options_powerpc): New function.
 527         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 528         Remove printing of "32" and "64".
 529         * s390-dis.c: Include "libiberty.h".
 530         (init_flag): Remove unneeded variable.
 531         (struct s390_options_t): New structure type.
 532         (options): New structure.
 533         (init_disasm): Rename from this...
 534         (disassemble_init_s390): ...to this.  Add initializations for
 535         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 536         (print_insn_s390): Delete call to init_disasm.
 537         (disassembler_options_s390): New function.
 538         (print_s390_disassembler_options): Print using information from
 539         struct 'options'.
 540         * po/opcodes.pot: Regenerate.
 541
 542 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 543
 544         * i386-dis.c (PCMPESTR_Fixup): New.
 545         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 546         (prefix_table): Use PCMPESTR_Fixup.
 547         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 548         PCMPESTR_Fixup.
 549         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 550         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 551         Split 64-bit and non-64-bit variants.
 552         * opcodes/i386-tbl.h: Re-generate.
 553
 554 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 555
 556         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 557         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 558         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 559         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 560         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 561         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 562         (OP_SVE_V_HSD): New macros.
 563         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 564         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 565         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 566         (aarch64_opcode_table): Add new SVE instructions.
 567         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 568         for rotation operands.  Add new SVE operands.
 569         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 570         (ins_sve_quad_index): Likewise.
 571         (ins_imm_rotate): Split into...
 572         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 573         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 574         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 575         functions.
 576         (aarch64_ins_sve_addr_ri_s4): New function.
 577         (aarch64_ins_sve_quad_index): Likewise.
 578         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 579         * aarch64-asm-2.c: Regenerate.
 580         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 581         (ext_sve_quad_index): Likewise.
 582         (ext_imm_rotate): Split into...
 583         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 584         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 585         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 586         functions.
 587         (aarch64_ext_sve_addr_ri_s4): New function.
 588         (aarch64_ext_sve_quad_index): Likewise.
 589         (aarch64_ext_sve_index): Allow quad indices.
 590         (do_misc_decoding): Likewise.
 591         * aarch64-dis-2.c: Regenerate.
 592         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 593         aarch64_field_kinds.
 594         (OPD_F_OD_MASK): Widen by one bit.
 595         (OPD_F_NO_ZR): Bump accordingly.
 596         (get_operand_field_width): New function.
 597         * aarch64-opc.c (fields): Add new SVE fields.
 598         (operand_general_constraint_met_p): Handle new SVE operands.
 599         (aarch64_print_operand): Likewise.
 600         * aarch64-opc-2.c: Regenerate.
 601
 602 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 603
 604         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 605         (aarch64_feature_compnum): ...this.
 606         (SIMD_V8_3): Replace with...
 607         (COMPNUM): ...this.
 608         (CNUM_INSN): New macro.
 609         (aarch64_opcode_table): Use it for the complex number instructions.
 610
 611 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 614
 615 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 616
 617         Add support for associating SPARC ASIs with an architecture level.
 618         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 619         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 620         decoding of SPARC ASIs.
 621
 622 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 623
 624         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 625         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 626
 627 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 628
 629         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 630         1 (instead of to itself). Correct typo.
 631
 632 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 633
 634         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 635         pseudoinstructions.
 636
 637 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 638
 639         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 640         (aarch64_sys_reg_supported_p): Handle them.
 641
 642 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 643
 644         * arc-opc.c (UIMM6_20R): Define.
 645         (SIMM12_20): Use above.
 646         (SIMM12_20R): Define.
 647         (SIMM3_5_S): Use above.
 648         (UIMM7_A32_11R_S): Define.
 649         (UIMM7_9_S): Use above.
 650         (UIMM3_13R_S): Define.
 651         (SIMM11_A32_7_S): Use above.
 652         (SIMM9_8R): Define.
 653         (UIMM10_A32_8_S): Use above.
 654         (UIMM8_8R_S): Define.
 655         (W6): Use above.
 656         (arc_relax_opcodes): Use all above defines.
 657
 658 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 659
 660         * arc-regs.h: Distinguish some of the registers different on
 661         ARC700 and HS38 cpus.
 662
 663 2017-02-14  Alan Modra  <amodra@gmail.com>
 664
 665         PR 21118
 666         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 667         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 668
 669 2017-02-11  Stafford Horne  <shorne@gmail.com>
 670             Alan Modra  <amodra@gmail.com>
 671
 672         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 673         Use insn_bytes_value and insn_int_value directly instead.  Don't
 674         free allocated memory until function exit.
 675
 676 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 677
 678         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 679
 680 2017-02-03  Nick Clifton  <nickc@redhat.com>
 681
 682         PR 21096
 683         * aarch64-opc.c (print_register_list): Ensure that the register
 684         list index will fir into the tb buffer.
 685         (print_register_offset_address): Likewise.
 686         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 687
 688 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 689
 690         PR 21056
 691         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 692         instructions when the previous fetch packet ends with a 32-bit
 693         instruction.
 694
 695 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 696
 697         * pru-opc.c: Remove vague reference to a future GDB port.
 698
 699 2017-01-20  Nick Clifton  <nickc@redhat.com>
 700
 701         * po/ga.po: Updated Irish translation.
 702
 703 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 704
 705         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 706
 707 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 708
 709         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 710         if FETCH_DATA returns 0.
 711         (m68k_scan_mask): Likewise.
 712         (print_insn_m68k): Update code to handle -1 return value.
 713
 714 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 715
 716         * m68k-dis.c (enum print_insn_arg_error): New.
 717         (NEXTBYTE): Replace -3 with
 718         PRINT_INSN_ARG_MEMORY_ERROR.
 719         (NEXTULONG): Likewise.
 720         (NEXTSINGLE): Likewise.
 721         (NEXTDOUBLE): Likewise.
 722         (NEXTDOUBLE): Likewise.
 723         (NEXTPACKED): Likewise.
 724         (FETCH_ARG): Likewise.
 725         (FETCH_DATA): Update comments.
 726         (print_insn_arg): Update comments. Replace magic numbers with
 727         enum.
 728         (match_insn_m68k): Likewise.
 729
 730 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 731
 732         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 733         * i386-dis-evex.h (evex_table): Updated.
 734         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 735         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 736         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 737         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 738         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 739         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 740         * i386-init.h: Regenerate.
 741         * i386-tbl.h: Ditto.
 742
 743 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 744
 745         * msp430-dis.c (msp430_singleoperand): Return -1 if
 746         msp430dis_opcode_signed returns false.
 747         (msp430_doubleoperand): Likewise.
 748         (msp430_branchinstr): Return -1 if
 749         msp430dis_opcode_unsigned returns false.
 750         (msp430x_calla_instr): Likewise.
 751         (print_insn_msp430): Likewise.
 752
 753 2017-01-05  Nick Clifton  <nickc@redhat.com>
 754
 755         PR 20946
 756         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 757         could not be matched.
 758         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 759         NULL.
 760
 761 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 762
 763         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 764         (aarch64_opcode_table): Use RCPC_INSN.
 765
 766 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 767
 768         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 769         extension.
 770         * riscv-opcodes/all-opcodes: Likewise.
 771
 772 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 773
 774         * riscv-dis.c (print_insn_args): Add fall through comment.
 775
 776 2017-01-03  Nick Clifton  <nickc@redhat.com>
 777
 778         * po/sr.po: New Serbian translation.
 779         * configure.ac (ALL_LINGUAS): Add sr.
 780         * configure: Regenerate.
 781
 782 2017-01-02  Alan Modra  <amodra@gmail.com>
 783
 784         * epiphany-desc.h: Regenerate.
 785         * epiphany-opc.h: Regenerate.
 786         * fr30-desc.h: Regenerate.
 787         * fr30-opc.h: Regenerate.
 788         * frv-desc.h: Regenerate.
 789         * frv-opc.h: Regenerate.
 790         * ip2k-desc.h: Regenerate.
 791         * ip2k-opc.h: Regenerate.
 792         * iq2000-desc.h: Regenerate.
 793         * iq2000-opc.h: Regenerate.
 794         * lm32-desc.h: Regenerate.
 795         * lm32-opc.h: Regenerate.
 796         * m32c-desc.h: Regenerate.
 797         * m32c-opc.h: Regenerate.
 798         * m32r-desc.h: Regenerate.
 799         * m32r-opc.h: Regenerate.
 800         * mep-desc.h: Regenerate.
 801         * mep-opc.h: Regenerate.
 802         * mt-desc.h: Regenerate.
 803         * mt-opc.h: Regenerate.
 804         * or1k-desc.h: Regenerate.
 805         * or1k-opc.h: Regenerate.
 806         * xc16x-desc.h: Regenerate.
 807         * xc16x-opc.h: Regenerate.
 808         * xstormy16-desc.h: Regenerate.
 809         * xstormy16-opc.h: Regenerate.
 810
 811 2017-01-02  Alan Modra  <amodra@gmail.com>
 812
 813         Update year range in copyright notice of all files.
 814
 815 For older changes see ChangeLog-2016
 816 \f
 817 Copyright (C) 2017 Free Software Foundation, Inc.
 818
 819 Copying and distribution of this file, with or without modification,
 820 are permitted in any medium without royalty provided the copyright
 821 notice and this notice are preserved.
 822
 823 Local Variables:
 824 mode: change-log
 825 left-margin: 8
 826 fill-column: 74
 827 version-control: never
 828 End: