opcodes/ChangeLog

   1 2017-11-14  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
   4         smov, ssca, stos, ssto, xlat): Drop Disp*.
   5         * i386-tbl.h: Re-generate.
   6
   7 2017-11-13  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
  10         xsaveopt64): Add No_qSuf.
  11         * i386-tbl.h: Re-generate.
  12
  13 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  14
  15         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
  16         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
  17         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
  18         sder32_el2, vncr_el2.
  19         (aarch64_sys_reg_supported_p): Likewise.
  20         (aarch64_pstatefields): Add dit register.
  21         (aarch64_pstatefield_supported_p): Likewise.
  22         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
  23         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
  24         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
  25         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
  26         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
  27         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
  28         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
  29
  30 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  31
  32         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
  33         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
  34         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
  35         (QL_STLW, QL_STLX): New.
  36
  37 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  38
  39         * aarch64-asm.h (ins_addr_offset): New.
  40         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
  41         (aarch64_ins_addr_offset): New.
  42         * aarch64-asm-2.c: Regenerate.
  43         * aarch64-dis.h (ext_addr_offset): New.
  44         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
  45         (aarch64_ext_addr_offset): New.
  46         * aarch64-dis-2.c: Regenerate.
  47         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
  48         FLD_imm4_2 and FLD_SM3_imm2.
  49         * aarch64-opc.c (fields): Add FLD_imm6_2,
  50         FLD_imm4_2 and FLD_SM3_imm2.
  51         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
  52         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
  53         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
  54         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
  55         * aarch64-tbl.h
  56         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
  57
  58 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
  59
  60         * aarch64-tbl.h
  61         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
  62         (aarch64_feature_sm4, aarch64_feature_sha3): New.
  63         (aarch64_feature_fp_16_v8_2): New.
  64         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
  65         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
  66         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
  67
  68 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
  69
  70         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
  71         (aarch64_feature_sha2, aarch64_feature_aes): New.
  72         (SHA2, AES): New.
  73         (AES_INSN, SHA2_INSN): New.
  74         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
  75         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
  76          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
  77         Change to SHA2_INS.
  78
  79 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
  80             Tamar Christina <tamar.christina@arm.com>
  81
  82         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
  83         FP16 instructions, including vfmal.f16 and vfmsl.f16.
  84
  85 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
  86
  87         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
  88
  89 2017-11-07  Alan Modra  <amodra@gmail.com>
  90
  91         * opintl.h: Formatting, comment fixes.
  92         (gettext, ngettext): Redefine when ENABLE_NLS.
  93         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
  94         (_): Define using gettext.
  95         (textdomain, bindtextdomain): Use safer "do nothing".
  96
  97 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
  98
  99         * arc-dis.c (print_hex): New variable.
 100         (parse_option): Check for hex option.
 101         (print_insn_arc): Use hexadecimal representation for short
 102         immediate values when requested.
 103         (print_arc_disassembler_options): Add hex option to the list.
 104
 105 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 106
 107         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 108         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 109         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 110         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 111         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 112         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 113         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 114         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 115         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 116         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 117         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 118         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 119         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 120         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 121         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 122         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 123         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 124         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 125         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 126         Changed opcodes.
 127         (prealloc, prefetch*): Place them before ld instruction.
 128         * arc-opc.c (skip_this_opcode): Add ARITH class.
 129
 130 2017-10-25  Alan Modra  <amodra@gmail.com>
 131
 132         PR 22348
 133         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 134         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 135         (imm4flag, size_changed): Likewise.
 136         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 137         (words, allWords, processing_argument_number): Likewise.
 138         (cst4flag, size_changed): Likewise.
 139         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 140         (crx_cst4_maps): Rename from cst4_maps.
 141         (crx_no_op_insn): Rename from no_op_insn.
 142
 143 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 144
 145         * riscv-opc.c (match_c_addi16sp) : New function.
 146         (match_c_addi4spn): New function.
 147         (match_c_lui): Don't allow 0-immediate encodings.
 148         (riscv_opcodes) <addi>: Use the above functions.
 149         <add>: Likewise.
 150         <c.addi4spn>: Likewise.
 151         <c.addi16sp>: Likewise.
 152
 153 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 154
 155         * i386-init.h: Regenerate
 156         * i386-tbl.h: Likewise
 157
 158 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 159
 160         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 161         (enum): Add EVEX_W_0F3854_P_2.
 162         * i386-dis-evex.h (evex_table): Updated.
 163         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 164         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 165         (cpu_flags): Add CpuAVX512_BITALG.
 166         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 167         (i386_cpu_flags): Add cpuavx512_bitalg..
 168         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 169         * i386-init.h: Regenerate.
 170         * i386-tbl.h: Likewise.
 171
 172 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 173
 174         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 175         * i386-dis-evex.h (evex_table): Updated.
 176         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 177         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 178         (cpu_flags): Add CpuAVX512_VNNI.
 179         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 180         (i386_cpu_flags): Add cpuavx512_vnni.
 181         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 182         * i386-init.h: Regenerate.
 183         * i386-tbl.h: Likewise.
 184
 185 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 186
 187         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 188         (enum): Remove VEX_LEN_0F3A44_P_2.
 189         (vex_len_table): Ditto.
 190         (enum): Remove VEX_W_0F3A44_P_2.
 191         (vew_w_table): Ditto.
 192         (prefix_table): Adjust instructions (see prefixes above).
 193         * i386-dis-evex.h (evex_table):
 194         Add new instructions (see prefixes above).
 195         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 196         (bitfield_cpu_flags): Ditto.
 197         * i386-opc.h (enum): Ditto.
 198         (i386_cpu_flags): Ditto.
 199         (CpuUnused): Comment out to avoid zero-width field problem.
 200         * i386-opc.tbl (vpclmulqdq): New instruction.
 201         * i386-init.h: Regenerate.
 202         * i386-tbl.h: Ditto.
 203
 204 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 205
 206         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 207         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 208         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 209         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 210         (vex_len_table): Ditto.
 211         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 212         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 213         (vew_w_table): Ditto.
 214         (prefix_table): Adjust instructions (see prefixes above).
 215         * i386-dis-evex.h (evex_table):
 216         Add new instructions (see prefixes above).
 217         * i386-gen.c (cpu_flag_init): Add VAES.
 218         (bitfield_cpu_flags): Ditto.
 219         * i386-opc.h (enum): Ditto.
 220         (i386_cpu_flags): Ditto.
 221         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 222         * i386-init.h: Regenerate.
 223         * i386-tbl.h: Ditto.
 224
 225 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 226
 227         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 228         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 229         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 230         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 231         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 232         (prefix_table): Updated (see prefixes above).
 233         (three_byte_table): Likewise.
 234         (vex_w_table): Likewise.
 235         * i386-dis-evex.h: Likewise.
 236         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 237         (cpu_flags): Add CpuGFNI.
 238         * i386-opc.h (enum): Add CpuGFNI.
 239         (i386_cpu_flags): Add cpugfni.
 240         * i386-opc.tbl: Add Intel GFNI instructions.
 241         * i386-init.h: Regenerate.
 242         * i386-tbl.h: Likewise.
 243
 244 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 245
 246         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 247         Define EXbScalar and EXwScalar for OP_EX.
 248         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 249         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 250         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 251         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 252         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 253         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 254         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 255         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 256         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 257         (OP_E_memory): Likewise.
 258         * i386-dis-evex.h: Updated.
 259         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 260         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 261         (cpu_flags): Add CpuAVX512_VBMI2.
 262         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 263         (i386_cpu_flags): Add cpuavx512_vbmi2.
 264         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 265         * i386-init.h: Regenerate.
 266         * i386-tbl.h: Likewise.
 267
 268 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 269
 270         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 271
 272 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 273
 274         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 275         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 276         K15. Add jmpix pattern.
 277
 278 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 279
 280         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 281
 282 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 283
 284         * s390-opc.c (INSTR_SI_RD): New macro.
 285         (INSTR_S_RD): Adjust example instruction.
 286         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 287         SI_RD.
 288
 289 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 290
 291         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 292         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 293         VLE multimple load/store instructions. Old e_ldm* variants are
 294         kept as aliases.
 295         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 296
 297 2017-09-27  Nick Clifton  <nickc@redhat.com>
 298
 299         PR 22179
 300         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 301         names for the fmv.x.s and fmv.s.x instructions respectively.
 302
 303 2017-09-26  do  <do@nerilex.org>
 304
 305         PR 22123
 306         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 307         be used on CPUs that have emacs support.
 308
 309 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 310
 311         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 312
 313 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 314
 315         * nds32-asm.c: Rename __BIT() to N32_BIT().
 316         * nds32-asm.h: Likewise.
 317         * nds32-dis.c: Likewise.
 318
 319 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 320
 321         * i386-dis.c (last_active_prefix): Removed.
 322         (ckprefix): Don't set last_active_prefix.
 323         (NOTRACK_Fixup): Don't check last_active_prefix.
 324
 325 2017-08-31  Nick Clifton  <nickc@redhat.com>
 326
 327         * po/fr.po: Updated French translation.
 328
 329 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 330
 331         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 332         fields.
 333
 334 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 335             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 336
 337         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 338         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 339         New entries efs2 and spe2.
 340         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 341         (SPE2_OPCD_SEGS): New macro.
 342         (spe2_opcd_indices): New.
 343         (disassemble_init_powerpc): Handle SPE2 opcodes.
 344         (lookup_spe2): New function.
 345         (print_insn_powerpc): call lookup_spe2.
 346         * ppc-opc.c (insert_evuimm1_ex0): New function.
 347         (extract_evuimm1_ex0): Likewise.
 348         (insert_evuimm_lt8): Likewise.
 349         (extract_evuimm_lt8): Likewise.
 350         (insert_off_spe2): Likewise.
 351         (extract_off_spe2): Likewise.
 352         (insert_Ddd): Likewise.
 353         (extract_Ddd): Likewise.
 354         (DD): New operand.
 355         (EVUIMM_LT8): Likewise.
 356         (EVUIMM_LT16): Adjust.
 357         (MMMM): New operand.
 358         (EVUIMM_1): Likewise.
 359         (EVUIMM_1_EX0): Likewise.
 360         (EVUIMM_2): Adjust.
 361         (NNN): New operand.
 362         (VX_OFF_SPE2): Likewise.
 363         (BBB): Likewise.
 364         (DDD): Likewise.
 365         (VX_MASK_DDD): New mask.
 366         (HH): New operand.
 367         (VX_RA_CONST): New macro.
 368         (VX_RA_CONST_MASK): Likewise.
 369         (VX_RB_CONST): Likewise.
 370         (VX_RB_CONST_MASK): Likewise.
 371         (VX_OFF_SPE2_MASK): Likewise.
 372         (VX_SPE_CRFD): Likewise.
 373         (VX_SPE_CRFD_MASK VX): Likewise.
 374         (VX_SPE2_CLR): Likewise.
 375         (VX_SPE2_CLR_MASK): Likewise.
 376         (VX_SPE2_SPLATB): Likewise.
 377         (VX_SPE2_SPLATB_MASK): Likewise.
 378         (VX_SPE2_OCTET): Likewise.
 379         (VX_SPE2_OCTET_MASK): Likewise.
 380         (VX_SPE2_DDHH): Likewise.
 381         (VX_SPE2_DDHH_MASK): Likewise.
 382         (VX_SPE2_HH): Likewise.
 383         (VX_SPE2_HH_MASK): Likewise.
 384         (VX_SPE2_EVMAR): Likewise.
 385         (VX_SPE2_EVMAR_MASK): Likewise.
 386         (PPCSPE2): Likewise.
 387         (PPCEFS2): Likewise.
 388         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 389         (powerpc_macros): Map old SPE instructions have new names
 390         with the same opcodes. Add SPE2 instructions which just are
 391         mapped to SPE2.
 392         (spe2_opcodes): Add SPE2 opcodes.
 393
 394 2017-08-23  Alan Modra  <amodra@gmail.com>
 395
 396         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 397         extract functions earlier, deleting forward declarations.
 398         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 399         RA_MASK.
 400
 401 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 402
 403         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 404
 405 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 406             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 407
 408         * ppc-opc.c (insert_evuimm2_ex0): New function.
 409         (extract_evuimm2_ex0): Likewise.
 410         (insert_evuimm4_ex0): Likewise.
 411         (extract_evuimm4_ex0): Likewise.
 412         (insert_evuimm8_ex0): Likewise.
 413         (extract_evuimm8_ex0): Likewise.
 414         (insert_evuimm_lt16): Likewise.
 415         (extract_evuimm_lt16): Likewise.
 416         (insert_rD_rS_even): Likewise.
 417         (extract_rD_rS_even): Likewise.
 418         (insert_off_lsp): Likewise.
 419         (extract_off_lsp): Likewise.
 420         (RD_EVEN): New operand.
 421         (RS_EVEN): Likewise.
 422         (RSQ): Adjust.
 423         (EVUIMM_LT16): New operand.
 424         (HTM_SI): Adjust.
 425         (EVUIMM_2_EX0): New operand.
 426         (EVUIMM_4): Adjust.
 427         (EVUIMM_4_EX0): New operand.
 428         (EVUIMM_8): Adjust.
 429         (EVUIMM_8_EX0): New operand.
 430         (WS): Adjust.
 431         (VX_OFF): New operand.
 432         (VX_LSP): New macro.
 433         (VX_LSP_MASK): Likewise.
 434         (VX_LSP_OFF_MASK): Likewise.
 435         (PPC_OPCODE_LSP): Likewise.
 436         (vle_opcodes): Add LSP opcodes.
 437         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 438
 439 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 440
 441         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 442         register operands in CRC instructions.
 443         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 444         comments.
 445
 446 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 447
 448         * disassemble.c (disassembler): Mark big and mach with
 449         ATTRIBUTE_UNUSED.
 450
 451 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 452
 453         * disassemble.c (disassembler): Remove arch/mach/endian
 454         assertions.
 455
 456 2017-07-25  Nick Clifton  <nickc@redhat.com>
 457
 458         PR 21739
 459         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 460         message.
 461         (insert_r0): Likewise.
 462         (insert_r1): Likewise.
 463         (insert_r2): Likewise.
 464         (insert_r3): Likewise.
 465         (insert_sp): Likewise.
 466         (insert_gp): Likewise.
 467         (insert_pcl): Likewise.
 468         (insert_blink): Likewise.
 469         (insert_ilink1): Likewise.
 470         (insert_ilink2): Likewise.
 471         (insert_ras): Likewise.
 472         (insert_rbs): Likewise.
 473         (insert_rcs): Likewise.
 474         (insert_simm3s): Likewise.
 475         (insert_rrange): Likewise.
 476         (insert_r13el): Likewise.
 477         (insert_fpel): Likewise.
 478         (insert_blinkel): Likewise.
 479         (insert_pclel): Likewise.
 480         (insert_nps_bitop_size_2b): Likewise.
 481         (insert_nps_imm_offset): Likewise.
 482         (insert_nps_imm_entry): Likewise.
 483         (insert_nps_size_16bit): Likewise.
 484         (insert_nps_##NAME##_pos): Likewise.
 485         (insert_nps_##NAME): Likewise.
 486         (insert_nps_bitop_ins_ext): Likewise.
 487         (insert_nps_##NAME): Likewise.
 488         (insert_nps_min_hofs): Likewise.
 489         (insert_nps_##NAME): Likewise.
 490         (insert_nps_rbdouble_64): Likewise.
 491         (insert_nps_misc_imm_offset): Likewise.
 492         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 493         option description.
 494
 495 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 496             Jiong Wang  <jiong.wang@arm.com>
 497
 498         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 499         correct the print.
 500         * aarch64-dis-2.c: Regenerated.
 501
 502 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 503
 504         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 505         table.
 506
 507 2017-07-20  Nick Clifton  <nickc@redhat.com>
 508
 509         * po/de.po: Updated German translation.
 510
 511 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 512
 513         * arc-regs.h (sec_stat): New aux register.
 514         (aux_kernel_sp): Likewise.
 515         (aux_sec_u_sp): Likewise.
 516         (aux_sec_k_sp): Likewise.
 517         (sec_vecbase_build): Likewise.
 518         (nsc_table_top): Likewise.
 519         (nsc_table_base): Likewise.
 520         (ersec_stat): Likewise.
 521         (aux_sec_except): Likewise.
 522
 523 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 524
 525         * arc-opc.c (extract_uimm12_20): New function.
 526         (UIMM12_20): New operand.
 527         (SIMM3_5_S): Adjust.
 528         * arc-tbl.h (sjli): Add new instruction.
 529
 530 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 531             John Eric Martin  <John.Martin@emmicro-us.com>
 532
 533         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 534         (UIMM3_23): Adjust accordingly.
 535         * arc-regs.h: Add/correct jli_base register.
 536         * arc-tbl.h (jli_s): Likewise.
 537
 538 2017-07-18  Nick Clifton  <nickc@redhat.com>
 539
 540         PR 21775
 541         * aarch64-opc.c: Fix spelling typos.
 542         * i386-dis.c: Likewise.
 543
 544 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 545
 546         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 547         max_addr_offset and octets variables to size_t.
 548
 549 2017-07-12  Alan Modra  <amodra@gmail.com>
 550
 551         * po/da.po: Update from translationproject.org/latest/opcodes/.
 552         * po/de.po: Likewise.
 553         * po/es.po: Likewise.
 554         * po/fi.po: Likewise.
 555         * po/fr.po: Likewise.
 556         * po/id.po: Likewise.
 557         * po/it.po: Likewise.
 558         * po/nl.po: Likewise.
 559         * po/pt_BR.po: Likewise.
 560         * po/ro.po: Likewise.
 561         * po/sv.po: Likewise.
 562         * po/tr.po: Likewise.
 563         * po/uk.po: Likewise.
 564         * po/vi.po: Likewise.
 565         * po/zh_CN.po: Likewise.
 566
 567 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 568             Alan Modra  <amodra@gmail.com>
 569
 570         * cgen.sh: Mark generated files read-only.
 571         * epiphany-asm.c: Regenerate.
 572         * epiphany-desc.c: Regenerate.
 573         * epiphany-desc.h: Regenerate.
 574         * epiphany-dis.c: Regenerate.
 575         * epiphany-ibld.c: Regenerate.
 576         * epiphany-opc.c: Regenerate.
 577         * epiphany-opc.h: Regenerate.
 578         * fr30-asm.c: Regenerate.
 579         * fr30-desc.c: Regenerate.
 580         * fr30-desc.h: Regenerate.
 581         * fr30-dis.c: Regenerate.
 582         * fr30-ibld.c: Regenerate.
 583         * fr30-opc.c: Regenerate.
 584         * fr30-opc.h: Regenerate.
 585         * frv-asm.c: Regenerate.
 586         * frv-desc.c: Regenerate.
 587         * frv-desc.h: Regenerate.
 588         * frv-dis.c: Regenerate.
 589         * frv-ibld.c: Regenerate.
 590         * frv-opc.c: Regenerate.
 591         * frv-opc.h: Regenerate.
 592         * ip2k-asm.c: Regenerate.
 593         * ip2k-desc.c: Regenerate.
 594         * ip2k-desc.h: Regenerate.
 595         * ip2k-dis.c: Regenerate.
 596         * ip2k-ibld.c: Regenerate.
 597         * ip2k-opc.c: Regenerate.
 598         * ip2k-opc.h: Regenerate.
 599         * iq2000-asm.c: Regenerate.
 600         * iq2000-desc.c: Regenerate.
 601         * iq2000-desc.h: Regenerate.
 602         * iq2000-dis.c: Regenerate.
 603         * iq2000-ibld.c: Regenerate.
 604         * iq2000-opc.c: Regenerate.
 605         * iq2000-opc.h: Regenerate.
 606         * lm32-asm.c: Regenerate.
 607         * lm32-desc.c: Regenerate.
 608         * lm32-desc.h: Regenerate.
 609         * lm32-dis.c: Regenerate.
 610         * lm32-ibld.c: Regenerate.
 611         * lm32-opc.c: Regenerate.
 612         * lm32-opc.h: Regenerate.
 613         * lm32-opinst.c: Regenerate.
 614         * m32c-asm.c: Regenerate.
 615         * m32c-desc.c: Regenerate.
 616         * m32c-desc.h: Regenerate.
 617         * m32c-dis.c: Regenerate.
 618         * m32c-ibld.c: Regenerate.
 619         * m32c-opc.c: Regenerate.
 620         * m32c-opc.h: Regenerate.
 621         * m32r-asm.c: Regenerate.
 622         * m32r-desc.c: Regenerate.
 623         * m32r-desc.h: Regenerate.
 624         * m32r-dis.c: Regenerate.
 625         * m32r-ibld.c: Regenerate.
 626         * m32r-opc.c: Regenerate.
 627         * m32r-opc.h: Regenerate.
 628         * m32r-opinst.c: Regenerate.
 629         * mep-asm.c: Regenerate.
 630         * mep-desc.c: Regenerate.
 631         * mep-desc.h: Regenerate.
 632         * mep-dis.c: Regenerate.
 633         * mep-ibld.c: Regenerate.
 634         * mep-opc.c: Regenerate.
 635         * mep-opc.h: Regenerate.
 636         * mt-asm.c: Regenerate.
 637         * mt-desc.c: Regenerate.
 638         * mt-desc.h: Regenerate.
 639         * mt-dis.c: Regenerate.
 640         * mt-ibld.c: Regenerate.
 641         * mt-opc.c: Regenerate.
 642         * mt-opc.h: Regenerate.
 643         * or1k-asm.c: Regenerate.
 644         * or1k-desc.c: Regenerate.
 645         * or1k-desc.h: Regenerate.
 646         * or1k-dis.c: Regenerate.
 647         * or1k-ibld.c: Regenerate.
 648         * or1k-opc.c: Regenerate.
 649         * or1k-opc.h: Regenerate.
 650         * or1k-opinst.c: Regenerate.
 651         * xc16x-asm.c: Regenerate.
 652         * xc16x-desc.c: Regenerate.
 653         * xc16x-desc.h: Regenerate.
 654         * xc16x-dis.c: Regenerate.
 655         * xc16x-ibld.c: Regenerate.
 656         * xc16x-opc.c: Regenerate.
 657         * xc16x-opc.h: Regenerate.
 658         * xstormy16-asm.c: Regenerate.
 659         * xstormy16-desc.c: Regenerate.
 660         * xstormy16-desc.h: Regenerate.
 661         * xstormy16-dis.c: Regenerate.
 662         * xstormy16-ibld.c: Regenerate.
 663         * xstormy16-opc.c: Regenerate.
 664         * xstormy16-opc.h: Regenerate.
 665
 666 2017-07-07  Alan Modra  <amodra@gmail.com>
 667
 668         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 669         * m32c-dis.c: Regenerate.
 670         * mep-dis.c: Regenerate.
 671
 672 2017-07-05  Borislav Petkov  <bp@suse.de>
 673
 674         * i386-dis.c: Enable ModRM.reg /6 aliases.
 675
 676 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 677
 678         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 679         with vmrs and vmsr.
 680
 681 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 682
 683         * configure: Regenerate.
 684
 685 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 686
 687         * po/opcodes.pot: Regenerate.
 688
 689 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 690
 691         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 692         entries to the MSA ASE instruction block.
 693
 694 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 695             Maciej W. Rozycki  <macro@imgtec.com>
 696
 697         * micromips-opc.c (XPA, XPAVZ): New macros.
 698         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 699         "mthgc0".
 700
 701 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 702             Maciej W. Rozycki  <macro@imgtec.com>
 703
 704         * micromips-opc.c (I36): New macro.
 705         (micromips_opcodes): Add "eretnc".
 706
 707 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 708             Andrew Bennett  <andrew.bennett@imgtec.com>
 709
 710         * mips-dis.c (mips_calculate_combination_ases): Handle the
 711         ASE_XPA_VIRT flag.
 712         (parse_mips_ase_option): New function.
 713         (parse_mips_dis_option): Factor out ASE option handling to the
 714         new function.  Call `mips_calculate_combination_ases'.
 715         * mips-opc.c (XPAVZ): New macro.
 716         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 717         "mfhgc0", "mthc0" and "mthgc0".
 718
 719 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 720
 721         * mips-dis.c (mips_calculate_combination_ases): New function.
 722         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 723         calculation to the new function.
 724         (set_default_mips_dis_options): Call the new function.
 725
 726 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 727
 728         * arc-dis.c (parse_disassembler_options): Use
 729         FOR_EACH_DISASSEMBLER_OPTION.
 730
 731 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 732
 733         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 734         disassembler option strings.
 735         (parse_cpu_option): Likewise.
 736
 737 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 738
 739         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 740         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 741         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 742         (aarch64_feature_dotprod, DOT_INSN): New.
 743         (udot, sdot): New.
 744         * aarch64-dis-2.c: Regenerated.
 745
 746 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 747
 748         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 749
 750 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 751             Matthew Fortune  <matthew.fortune@imgtec.com>
 752             Andrew Bennett  <andrew.bennett@imgtec.com>
 753
 754         * mips-formats.h (INT_BIAS): New macro.
 755         (INT_ADJ): Redefine in INT_BIAS terms.
 756         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 757         (mips_print_save_restore): New function.
 758         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 759         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 760         call.
 761         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 762         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 763         OP_SAVE_RESTORE_LIST handling, factored out from here.
 764         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 765         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 766         (mips_builtin_opcodes): Add "restore" and "save" entries.
 767         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 768         (IAMR2): New macro.
 769         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 770
 771 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 772
 773         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 774         alias; do not mark SLTI instruction as an alias.
 775
 776 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 777
 778         * i386-dis.c (RM_0FAE_REG_5): Removed.
 779         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 780         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 781         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 782         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 783         PREFIX_MOD_3_0F01_REG_5_RM_0.
 784         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 785         PREFIX_MOD_3_0FAE_REG_5.
 786         (mod_table): Update MOD_0FAE_REG_5.
 787         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 788         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 789         * i386-tbl.h: Regenerated.
 790
 791 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 792
 793         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 794         * i386-opc.tbl: Likewise.
 795         * i386-tbl.h: Regenerated.
 796
 797 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 798
 799         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 800         and "jmp{&|}".
 801         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 802         prefix.
 803
 804 2017-06-19  Nick Clifton  <nickc@redhat.com>
 805
 806         PR binutils/21614
 807         * score-dis.c (score_opcodes): Add sentinel.
 808
 809 2017-06-16  Alan Modra  <amodra@gmail.com>
 810
 811         * rx-decode.c: Regenerate.
 812
 813 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 814
 815         PR binutils/21594
 816         * i386-dis.c (OP_E_register): Check valid bnd register.
 817         (OP_G): Likewise.
 818
 819 2017-06-15  Nick Clifton  <nickc@redhat.com>
 820
 821         PR binutils/21595
 822         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 823         range value.
 824
 825 2017-06-15  Nick Clifton  <nickc@redhat.com>
 826
 827         PR binutils/21588
 828         * rl78-decode.opc (OP_BUF_LEN): Define.
 829         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 830         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 831         array.
 832         * rl78-decode.c: Regenerate.
 833
 834 2017-06-15  Nick Clifton  <nickc@redhat.com>
 835
 836         PR binutils/21586
 837         * bfin-dis.c (gregs): Clip index to prevent overflow.
 838         (regs): Likewise.
 839         (regs_lo): Likewise.
 840         (regs_hi): Likewise.
 841
 842 2017-06-14  Nick Clifton  <nickc@redhat.com>
 843
 844         PR binutils/21576
 845         * score7-dis.c (score_opcodes): Add sentinel.
 846
 847 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 848
 849         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 850         * arm-dis.c: Likewise.
 851         * ia64-dis.c: Likewise.
 852         * mips-dis.c: Likewise.
 853         * spu-dis.c: Likewise.
 854         * disassemble.h (print_insn_aarch64): New declaration, moved from
 855         include/dis-asm.h.
 856         (print_insn_big_arm, print_insn_big_mips): Likewise.
 857         (print_insn_i386, print_insn_ia64): Likewise.
 858         (print_insn_little_arm, print_insn_little_mips): Likewise.
 859
 860 2017-06-14  Nick Clifton  <nickc@redhat.com>
 861
 862         PR binutils/21587
 863         * rx-decode.opc: Include libiberty.h
 864         (GET_SCALE): New macro - validates access to SCALE array.
 865         (GET_PSCALE): New macro - validates access to PSCALE array.
 866         (DIs, SIs, S2Is, rx_disp): Use new macros.
 867         * rx-decode.c: Regenerate.
 868
 869 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 870
 871         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 872
 873 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 874
 875         * arc-dis.c (enforced_isa_mask): Declare.
 876         (cpu_types): Likewise.
 877         (parse_cpu_option): New function.
 878         (parse_disassembler_options): Use it.
 879         (print_insn_arc): Use enforced_isa_mask.
 880         (print_arc_disassembler_options): Document new options.
 881
 882 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 883
 884         * alpha-dis.c: Include disassemble.h, don't include
 885         dis-asm.h.
 886         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 887         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 888         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 889         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 890         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 891         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 892         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 893         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 894         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 895         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 896         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 897         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 898         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 899         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 900         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 901         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 902         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 903         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 904         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 905         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 906         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 907         * z80-dis.c, z8k-dis.c: Likewise.
 908         * disassemble.h: New file.
 909
 910 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 911
 912         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 913         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 914
 915 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 916
 917         * disassemble.c (disassembler): Add arguments a, big and mach.
 918         Use them.
 919
 920 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 921
 922         * i386-dis.c (NOTRACK_Fixup): New.
 923         (NOTRACK): Likewise.
 924         (NOTRACK_PREFIX): Likewise.
 925         (last_active_prefix): Likewise.
 926         (reg_table): Use NOTRACK on indirect call and jmp.
 927         (ckprefix): Set last_active_prefix.
 928         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 929         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 930         * i386-opc.h (NoTrackPrefixOk): New.
 931         (i386_opcode_modifier): Add notrackprefixok.
 932         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 933         Add notrack.
 934         * i386-tbl.h: Regenerated.
 935
 936 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 937
 938         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 939         (X_IMM2): Define.
 940         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 941         bfd_mach_sparc_v9m8.
 942         (print_insn_sparc): Handle new operand types.
 943         * sparc-opc.c (MASK_M8): Define.
 944         (v6): Add MASK_M8.
 945         (v6notlet): Likewise.
 946         (v7): Likewise.
 947         (v8): Likewise.
 948         (v9): Likewise.
 949         (v9a): Likewise.
 950         (v9b): Likewise.
 951         (v9c): Likewise.
 952         (v9d): Likewise.
 953         (v9e): Likewise.
 954         (v9v): Likewise.
 955         (v9m): Likewise.
 956         (v9andleon): Likewise.
 957         (m8): Define.
 958         (HWS_VM8): Define.
 959         (HWS2_VM8): Likewise.
 960         (sparc_opcode_archs): Add entry for "m8".
 961         (sparc_opcodes): Add OSA2017 and M8 instructions
 962         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 963         fpx{ll,ra,rl}64x,
 964         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 965         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 966         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 967         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 968         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 969         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 970         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 971         ASI_CORE_SELECT_COMMIT_NHT.
 972
 973 2017-05-18  Alan Modra  <amodra@gmail.com>
 974
 975         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 976         * aarch64-dis.c: Likewise.
 977         * aarch64-gen.c: Likewise.
 978         * aarch64-opc.c: Likewise.
 979
 980 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 981             Matthew Fortune  <matthew.fortune@imgtec.com>
 982
 983         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 984         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 985         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 986         (print_insn_arg) <OP_REG28>: Add handler.
 987         (validate_insn_args) <OP_REG28>: Handle.
 988         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 989         32-bit encoding and 9-bit immediates.
 990         (print_insn_mips16): Handle MIPS16 instructions that require
 991         32-bit encoding and MFC0/MTC0 operand decoding.
 992         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 993         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 994         (RD_C0, WR_C0, E2, E2MT): New macros.
 995         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 996         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 997         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 998         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 999         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1000         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1001         instructions, "swl", "swr", "sync" and its "sync_acquire",
1002         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1003         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1004         regular/extended entries for original MIPS16 ISA revision
1005         instructions whose extended forms are subdecoded in the MIPS16e2
1006         ISA revision: "li", "sll" and "srl".
1007
1008 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1009
1010         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1011         reference in CP0 move operand decoding.
1012
1013 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1014
1015         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1016         type to hexadecimal.
1017         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1018
1019 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1020
1021         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1022         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1023         "sync_rmb" and "sync_wmb" as aliases.
1024         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1025         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1026
1027 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1028
1029         * arc-dis.c (parse_option): Update quarkse_em option..
1030         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1031         QUARKSE1.
1032         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1033
1034 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1035
1036         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1037
1038 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1039
1040         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1041         register.
1042
1043 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1044
1045         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1046         and branches and not synthetic data instructions.
1047
1048 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1049
1050         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1051
1052 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1053
1054         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1055         * arc-opc.c (insert_r13el): New function.
1056         (R13_EL): Define.
1057         * arc-tbl.h: Add new enter/leave variants.
1058
1059 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1060
1061         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1062
1063 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1064
1065         * mips-dis.c (print_mips_disassembler_options): Add
1066         `no-aliases'.
1067
1068 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1069
1070         * mips16-opc.c (AL): New macro.
1071         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1072         of "ld" and "lw" as aliases.
1073
1074 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1075
1076         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1077         arguments.
1078
1079 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1080             Alan Modra  <amodra@gmail.com>
1081
1082         * ppc-opc.c (ELEV): Define.
1083         (vle_opcodes): Add se_rfgi and e_sc.
1084         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1085         for E200Z4.
1086
1087 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1088
1089         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1090
1091 2017-04-21  Nick Clifton  <nickc@redhat.com>
1092
1093         PR binutils/21380
1094         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1095         LD3R and LD4R.
1096
1097 2017-04-13  Alan Modra  <amodra@gmail.com>
1098
1099         * epiphany-desc.c: Regenerate.
1100         * fr30-desc.c: Regenerate.
1101         * frv-desc.c: Regenerate.
1102         * ip2k-desc.c: Regenerate.
1103         * iq2000-desc.c: Regenerate.
1104         * lm32-desc.c: Regenerate.
1105         * m32c-desc.c: Regenerate.
1106         * m32r-desc.c: Regenerate.
1107         * mep-desc.c: Regenerate.
1108         * mt-desc.c: Regenerate.
1109         * or1k-desc.c: Regenerate.
1110         * xc16x-desc.c: Regenerate.
1111         * xstormy16-desc.c: Regenerate.
1112
1113 2017-04-11  Alan Modra  <amodra@gmail.com>
1114
1115         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1116         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1117         PPC_OPCODE_TMR for e6500.
1118         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1119         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1120         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1121         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1122         (PPCHTM): Define as PPC_OPCODE_POWER8.
1123         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1124
1125 2017-04-10  Alan Modra  <amodra@gmail.com>
1126
1127         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1128         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1129         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1130         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1131
1132 2017-04-09  Pip Cet  <pipcet@gmail.com>
1133
1134         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1135         appropriate floating-point precision directly.
1136
1137 2017-04-07  Alan Modra  <amodra@gmail.com>
1138
1139         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1140         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1141         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1142         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1143         vector instructions with E6500 not PPCVEC2.
1144
1145 2017-04-06  Pip Cet  <pipcet@gmail.com>
1146
1147         * Makefile.am: Add wasm32-dis.c.
1148         * configure.ac: Add wasm32-dis.c to wasm32 target.
1149         * disassemble.c: Add wasm32 disassembler code.
1150         * wasm32-dis.c: New file.
1151         * Makefile.in: Regenerate.
1152         * configure: Regenerate.
1153         * po/POTFILES.in: Regenerate.
1154         * po/opcodes.pot: Regenerate.
1155
1156 2017-04-05  Pedro Alves  <palves@redhat.com>
1157
1158         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1159         * arm-dis.c (parse_arm_disassembler_options): Constify.
1160         * ppc-dis.c (powerpc_init_dialect): Constify local.
1161         * vax-dis.c (parse_disassembler_options): Constify.
1162
1163 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1164
1165         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1166         RISCV_GP_SYMBOL.
1167
1168 2017-03-30  Pip Cet  <pipcet@gmail.com>
1169
1170         * configure.ac: Add (empty) bfd_wasm32_arch target.
1171         * configure: Regenerate
1172         * po/opcodes.pot: Regenerate.
1173
1174 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1175
1176         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1177         OSA2015.
1178         * opcodes/sparc-opc.c (asi_table): New ASIs.
1179
1180 2017-03-29  Alan Modra  <amodra@gmail.com>
1181
1182         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1183         "raw" option.
1184         (lookup_powerpc): Don't special case -1 dialect.  Handle
1185         PPC_OPCODE_RAW.
1186         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1187         lookup_powerpc call, pass it on second.
1188
1189 2017-03-27  Alan Modra  <amodra@gmail.com>
1190
1191         PR 21303
1192         * ppc-dis.c (struct ppc_mopt): Comment.
1193         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1194
1195 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1196
1197         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1198         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1199         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1200         (insert_nps_misc_imm_offset): New function.
1201         (extract_nps_misc imm_offset): New function.
1202         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1203         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1204
1205 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1206
1207         * s390-mkopc.c (main): Remove vx2 check.
1208         * s390-opc.txt: Remove vx2 instruction flags.
1209
1210 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1211
1212         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1213         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1214         (insert_nps_imm_offset): New function.
1215         (extract_nps_imm_offset): New function.
1216         (insert_nps_imm_entry): New function.
1217         (extract_nps_imm_entry): New function.
1218
1219 2017-03-17  Alan Modra  <amodra@gmail.com>
1220
1221         PR 21248
1222         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1223         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1224         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1225
1226 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1227
1228         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1229         <c.andi>: Likewise.
1230         <c.addiw> Likewise.
1231
1232 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1233
1234         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1235
1236 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1237
1238         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1239         <srl> Likewise.
1240         <srai> Likewise.
1241         <sra> Likewise.
1242
1243 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1244
1245         * i386-gen.c (opcode_modifiers): Replace S with Load.
1246         * i386-opc.h (S): Removed.
1247         (Load): New.
1248         (i386_opcode_modifier): Replace s with load.
1249         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1250         and {evex}.  Replace S with Load.
1251         * i386-tbl.h: Regenerated.
1252
1253 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1254
1255         * i386-opc.tbl: Use CpuCET on rdsspq.
1256         * i386-tbl.h: Regenerated.
1257
1258 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1259
1260         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1261         <vsx>: Do not use PPC_OPCODE_VSX3;
1262
1263 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1264
1265         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1266
1267 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1268
1269         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1270         (MOD_0F1E_PREFIX_1): Likewise.
1271         (MOD_0F38F5_PREFIX_2): Likewise.
1272         (MOD_0F38F6_PREFIX_0): Likewise.
1273         (RM_0F1E_MOD_3_REG_7): Likewise.
1274         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1275         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1276         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1277         (PREFIX_0F1E): Likewise.
1278         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1279         (PREFIX_0F38F5): Likewise.
1280         (dis386_twobyte): Use PREFIX_0F1E.
1281         (reg_table): Add REG_0F1E_MOD_3.
1282         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1283         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1284         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1285         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1286         (three_byte_table): Use PREFIX_0F38F5.
1287         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1288         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1289         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1290         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1291         PREFIX_MOD_3_0F01_REG_5_RM_2.
1292         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1293         (cpu_flags): Add CpuCET.
1294         * i386-opc.h (CpuCET): New enum.
1295         (CpuUnused): Commented out.
1296         (i386_cpu_flags): Add cpucet.
1297         * i386-opc.tbl: Add Intel CET instructions.
1298         * i386-init.h: Regenerated.
1299         * i386-tbl.h: Likewise.
1300
1301 2017-03-06  Alan Modra  <amodra@gmail.com>
1302
1303         PR 21124
1304         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1305         (extract_raq, extract_ras, extract_rbx): New functions.
1306         (powerpc_operands): Use opposite corresponding insert function.
1307         (Q_MASK): Define.
1308         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1309         register restriction.
1310
1311 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1312
1313         * disassemble.c Include "safe-ctype.h".
1314         (disassemble_init_for_target): Handle s390 init.
1315         (remove_whitespace_and_extra_commas): New function.
1316         (disassembler_options_cmp): Likewise.
1317         * arm-dis.c: Include "libiberty.h".
1318         (NUM_ELEM): Delete.
1319         (regnames): Use long disassembler style names.
1320         Add force-thumb and no-force-thumb options.
1321         (NUM_ARM_REGNAMES): Rename from this...
1322         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1323         (get_arm_regname_num_options): Delete.
1324         (set_arm_regname_option): Likewise.
1325         (get_arm_regnames): Likewise.
1326         (parse_disassembler_options): Likewise.
1327         (parse_arm_disassembler_option): Rename from this...
1328         (parse_arm_disassembler_options): ...to this.  Make static.
1329         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1330         (print_insn): Use parse_arm_disassembler_options.
1331         (disassembler_options_arm): New function.
1332         (print_arm_disassembler_options): Handle updated regnames.
1333         * ppc-dis.c: Include "libiberty.h".
1334         (ppc_opts): Add "32" and "64" entries.
1335         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1336         (powerpc_init_dialect): Add break to switch statement.
1337         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1338         (disassembler_options_powerpc): New function.
1339         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1340         Remove printing of "32" and "64".
1341         * s390-dis.c: Include "libiberty.h".
1342         (init_flag): Remove unneeded variable.
1343         (struct s390_options_t): New structure type.
1344         (options): New structure.
1345         (init_disasm): Rename from this...
1346         (disassemble_init_s390): ...to this.  Add initializations for
1347         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1348         (print_insn_s390): Delete call to init_disasm.
1349         (disassembler_options_s390): New function.
1350         (print_s390_disassembler_options): Print using information from
1351         struct 'options'.
1352         * po/opcodes.pot: Regenerate.
1353
1354 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1355
1356         * i386-dis.c (PCMPESTR_Fixup): New.
1357         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1358         (prefix_table): Use PCMPESTR_Fixup.
1359         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1360         PCMPESTR_Fixup.
1361         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1362         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1363         Split 64-bit and non-64-bit variants.
1364         * opcodes/i386-tbl.h: Re-generate.
1365
1366 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1367
1368         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1369         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1370         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1371         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1372         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1373         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1374         (OP_SVE_V_HSD): New macros.
1375         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1376         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1377         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1378         (aarch64_opcode_table): Add new SVE instructions.
1379         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1380         for rotation operands.  Add new SVE operands.
1381         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1382         (ins_sve_quad_index): Likewise.
1383         (ins_imm_rotate): Split into...
1384         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1385         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1386         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1387         functions.
1388         (aarch64_ins_sve_addr_ri_s4): New function.
1389         (aarch64_ins_sve_quad_index): Likewise.
1390         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1391         * aarch64-asm-2.c: Regenerate.
1392         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1393         (ext_sve_quad_index): Likewise.
1394         (ext_imm_rotate): Split into...
1395         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1396         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1397         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1398         functions.
1399         (aarch64_ext_sve_addr_ri_s4): New function.
1400         (aarch64_ext_sve_quad_index): Likewise.
1401         (aarch64_ext_sve_index): Allow quad indices.
1402         (do_misc_decoding): Likewise.
1403         * aarch64-dis-2.c: Regenerate.
1404         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1405         aarch64_field_kinds.
1406         (OPD_F_OD_MASK): Widen by one bit.
1407         (OPD_F_NO_ZR): Bump accordingly.
1408         (get_operand_field_width): New function.
1409         * aarch64-opc.c (fields): Add new SVE fields.
1410         (operand_general_constraint_met_p): Handle new SVE operands.
1411         (aarch64_print_operand): Likewise.
1412         * aarch64-opc-2.c: Regenerate.
1413
1414 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1415
1416         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1417         (aarch64_feature_compnum): ...this.
1418         (SIMD_V8_3): Replace with...
1419         (COMPNUM): ...this.
1420         (CNUM_INSN): New macro.
1421         (aarch64_opcode_table): Use it for the complex number instructions.
1422
1423 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1424
1425         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1426
1427 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1428
1429         Add support for associating SPARC ASIs with an architecture level.
1430         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1431         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1432         decoding of SPARC ASIs.
1433
1434 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1435
1436         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1437         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1438
1439 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1440
1441         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1442         1 (instead of to itself). Correct typo.
1443
1444 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1445
1446         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1447         pseudoinstructions.
1448
1449 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1450
1451         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1452         (aarch64_sys_reg_supported_p): Handle them.
1453
1454 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1455
1456         * arc-opc.c (UIMM6_20R): Define.
1457         (SIMM12_20): Use above.
1458         (SIMM12_20R): Define.
1459         (SIMM3_5_S): Use above.
1460         (UIMM7_A32_11R_S): Define.
1461         (UIMM7_9_S): Use above.
1462         (UIMM3_13R_S): Define.
1463         (SIMM11_A32_7_S): Use above.
1464         (SIMM9_8R): Define.
1465         (UIMM10_A32_8_S): Use above.
1466         (UIMM8_8R_S): Define.
1467         (W6): Use above.
1468         (arc_relax_opcodes): Use all above defines.
1469
1470 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1471
1472         * arc-regs.h: Distinguish some of the registers different on
1473         ARC700 and HS38 cpus.
1474
1475 2017-02-14  Alan Modra  <amodra@gmail.com>
1476
1477         PR 21118
1478         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1479         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1480
1481 2017-02-11  Stafford Horne  <shorne@gmail.com>
1482             Alan Modra  <amodra@gmail.com>
1483
1484         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1485         Use insn_bytes_value and insn_int_value directly instead.  Don't
1486         free allocated memory until function exit.
1487
1488 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1489
1490         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1491
1492 2017-02-03  Nick Clifton  <nickc@redhat.com>
1493
1494         PR 21096
1495         * aarch64-opc.c (print_register_list): Ensure that the register
1496         list index will fir into the tb buffer.
1497         (print_register_offset_address): Likewise.
1498         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1499
1500 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1501
1502         PR 21056
1503         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1504         instructions when the previous fetch packet ends with a 32-bit
1505         instruction.
1506
1507 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1508
1509         * pru-opc.c: Remove vague reference to a future GDB port.
1510
1511 2017-01-20  Nick Clifton  <nickc@redhat.com>
1512
1513         * po/ga.po: Updated Irish translation.
1514
1515 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1516
1517         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1518
1519 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1520
1521         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1522         if FETCH_DATA returns 0.
1523         (m68k_scan_mask): Likewise.
1524         (print_insn_m68k): Update code to handle -1 return value.
1525
1526 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1527
1528         * m68k-dis.c (enum print_insn_arg_error): New.
1529         (NEXTBYTE): Replace -3 with
1530         PRINT_INSN_ARG_MEMORY_ERROR.
1531         (NEXTULONG): Likewise.
1532         (NEXTSINGLE): Likewise.
1533         (NEXTDOUBLE): Likewise.
1534         (NEXTDOUBLE): Likewise.
1535         (NEXTPACKED): Likewise.
1536         (FETCH_ARG): Likewise.
1537         (FETCH_DATA): Update comments.
1538         (print_insn_arg): Update comments. Replace magic numbers with
1539         enum.
1540         (match_insn_m68k): Likewise.
1541
1542 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1543
1544         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1545         * i386-dis-evex.h (evex_table): Updated.
1546         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1547         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1548         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1549         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1550         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1551         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1552         * i386-init.h: Regenerate.
1553         * i386-tbl.h: Ditto.
1554
1555 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1556
1557         * msp430-dis.c (msp430_singleoperand): Return -1 if
1558         msp430dis_opcode_signed returns false.
1559         (msp430_doubleoperand): Likewise.
1560         (msp430_branchinstr): Return -1 if
1561         msp430dis_opcode_unsigned returns false.
1562         (msp430x_calla_instr): Likewise.
1563         (print_insn_msp430): Likewise.
1564
1565 2017-01-05  Nick Clifton  <nickc@redhat.com>
1566
1567         PR 20946
1568         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1569         could not be matched.
1570         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1571         NULL.
1572
1573 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1574
1575         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1576         (aarch64_opcode_table): Use RCPC_INSN.
1577
1578 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1579
1580         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1581         extension.
1582         * riscv-opcodes/all-opcodes: Likewise.
1583
1584 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1585
1586         * riscv-dis.c (print_insn_args): Add fall through comment.
1587
1588 2017-01-03  Nick Clifton  <nickc@redhat.com>
1589
1590         * po/sr.po: New Serbian translation.
1591         * configure.ac (ALL_LINGUAS): Add sr.
1592         * configure: Regenerate.
1593
1594 2017-01-02  Alan Modra  <amodra@gmail.com>
1595
1596         * epiphany-desc.h: Regenerate.
1597         * epiphany-opc.h: Regenerate.
1598         * fr30-desc.h: Regenerate.
1599         * fr30-opc.h: Regenerate.
1600         * frv-desc.h: Regenerate.
1601         * frv-opc.h: Regenerate.
1602         * ip2k-desc.h: Regenerate.
1603         * ip2k-opc.h: Regenerate.
1604         * iq2000-desc.h: Regenerate.
1605         * iq2000-opc.h: Regenerate.
1606         * lm32-desc.h: Regenerate.
1607         * lm32-opc.h: Regenerate.
1608         * m32c-desc.h: Regenerate.
1609         * m32c-opc.h: Regenerate.
1610         * m32r-desc.h: Regenerate.
1611         * m32r-opc.h: Regenerate.
1612         * mep-desc.h: Regenerate.
1613         * mep-opc.h: Regenerate.
1614         * mt-desc.h: Regenerate.
1615         * mt-opc.h: Regenerate.
1616         * or1k-desc.h: Regenerate.
1617         * or1k-opc.h: Regenerate.
1618         * xc16x-desc.h: Regenerate.
1619         * xc16x-opc.h: Regenerate.
1620         * xstormy16-desc.h: Regenerate.
1621         * xstormy16-opc.h: Regenerate.
1622
1623 2017-01-02  Alan Modra  <amodra@gmail.com>
1624
1625         Update year range in copyright notice of all files.
1626
1627 For older changes see ChangeLog-2016
1628 \f
1629 Copyright (C) 2017 Free Software Foundation, Inc.
1630
1631 Copying and distribution of this file, with or without modification,
1632 are permitted in any medium without royalty provided the copyright
1633 notice and this notice are preserved.
1634
1635 Local Variables:
1636 mode: change-log
1637 left-margin: 8
1638 fill-column: 74
1639 version-control: never
1640 End: