1 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
5 * i386-tbl.h: Regenerated.
7 2019-11-08 Jan Beulich <jbeulich@suse.com>
9 * i386-gen.c (operand_type_init): Add Class= to
10 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
11 OPERAND_TYPE_REGBND entry.
12 (operand_classes): Add RegMask and RegBND entries.
13 (operand_types): Drop RegMask and RegBND entry.
14 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
15 (RegMask, RegBND): Delete.
16 (union i386_operand_type): Remove regmask and regbnd fields.
17 * i386-opc.tbl (RegMask, RegBND): Define.
18 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
20 * i386-init.h, i386-tbl.h: Re-generate.
22 2019-11-08 Jan Beulich <jbeulich@suse.com>
24 * i386-gen.c (operand_type_init): Add Class= to
25 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
26 OPERAND_TYPE_REGZMM entries.
27 (operand_classes): Add RegMMX and RegSIMD entries.
28 (operand_types): Drop RegMMX and RegSIMD entries.
29 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
30 (RegMMX, RegSIMD): Delete.
31 (union i386_operand_type): Remove regmmx and regsimd fields.
32 * i386-opc.tbl (RegMMX): Define.
33 (RegXMM, RegYMM, RegZMM): Add Class=.
34 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
36 * i386-init.h, i386-tbl.h: Re-generate.
38 2019-11-08 Jan Beulich <jbeulich@suse.com>
40 * i386-gen.c (operand_type_init): Add Class= to
41 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
43 (operand_classes): Add RegCR, RegDR, and RegTR entries.
44 (operand_types): Drop Control, Debug, and Test entries.
45 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
46 (Control, Debug, Test): Delete.
47 (union i386_operand_type): Remove control, debug, and test
49 * i386-opc.tbl (Control, Debug, Test): Define.
50 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
51 Class=RegDR, and Test by Class=RegTR.
52 * i386-init.h, i386-tbl.h: Re-generate.
54 2019-11-08 Jan Beulich <jbeulich@suse.com>
56 * i386-gen.c (operand_type_init): Add Class= to
57 OPERAND_TYPE_SREG entry.
58 (operand_classes): Add SReg entry.
59 (operand_types): Drop SReg entry.
60 * i386-opc.h (enum operand_class): Add SReg.
62 (union i386_operand_type): Remove sreg field.
63 * i386-opc.tbl (SReg): Define.
64 * i386-reg.tbl: Replace SReg by Class=SReg.
65 * i386-init.h, i386-tbl.h: Re-generate.
67 2019-11-08 Jan Beulich <jbeulich@suse.com>
69 * i386-gen.c (operand_type_init): Add Class=. New
70 OPERAND_TYPE_ANYIMM entry.
71 (operand_classes): New.
72 (operand_types): Drop Reg entry.
73 (output_operand_type): New parameter "class". Process it.
74 (process_i386_operand_type): New local variable "class".
75 (main): Adjust static assertions.
76 * i386-opc.h (CLASS_WIDTH): Define.
77 (enum operand_class): New.
78 (Reg): Replace by Class. Adjust comment.
79 (union i386_operand_type): Replace reg by class.
80 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
82 * i386-reg.tbl: Replace Reg by Class=Reg.
83 * i386-init.h: Re-generate.
85 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
87 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
88 (aarch64_opcode_table): Add data gathering hint mnemonic.
89 * opcodes/aarch64-dis-2.c: Account for new instruction.
91 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
93 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
96 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
98 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
99 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
100 aarch64_feature_f64mm): New feature sets.
101 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
102 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
104 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
106 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
107 (OP_SVE_QQQ): New qualifier.
108 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
109 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
110 the movprfx constraint.
111 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
112 (aarch64_opcode_table): Define new instructions smmla,
113 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
115 * aarch64-opc.c (operand_general_constraint_met_p): Handle
116 AARCH64_OPND_SVE_ADDR_RI_S4x32.
117 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
118 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
119 Account for new instructions.
120 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
122 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
124 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
125 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
127 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
129 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
130 (neon_opcodes): Add bfloat SIMD instructions.
131 (print_insn_coprocessor): Add new control character %b to print
132 condition code without checking cp_num.
133 (print_insn_neon): Account for BFloat16 instructions that have no
134 special top-byte handling.
136 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
137 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
139 * arm-dis.c (print_insn_coprocessor,
140 print_insn_generic_coprocessor): Create wrapper functions around
141 the implementation of the print_insn_coprocessor control codes.
142 (print_insn_coprocessor_1): Original print_insn_coprocessor
143 function that now takes which array to look at as an argument.
144 (print_insn_arm): Use both print_insn_coprocessor and
145 print_insn_generic_coprocessor.
146 (print_insn_thumb32): As above.
148 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
149 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
151 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
152 in reglane special case.
153 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
154 aarch64_find_next_opcode): Account for new instructions.
155 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
156 in reglane special case.
157 * aarch64-opc.c (struct operand_qualifier_data): Add data for
158 new AARCH64_OPND_QLF_S_2H qualifier.
159 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
160 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
161 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
163 (BFLOAT_SVE, BFLOAT): New feature set macros.
164 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
166 (aarch64_opcode_table): Define new instructions bfdot,
167 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
170 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
171 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
173 * aarch64-tbl.h (ARMV8_6): New macro.
175 2019-11-07 Jan Beulich <jbeulich@suse.com>
177 * i386-dis.c (prefix_table): Add mcommit.
178 (rm_table): Add rdpru.
179 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
180 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
181 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
182 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
183 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
184 * i386-opc.tbl (mcommit, rdpru): New.
185 * i386-init.h, i386-tbl.h: Re-generate.
187 2019-11-07 Jan Beulich <jbeulich@suse.com>
189 * i386-dis.c (OP_Mwait): Drop local variable "names", use
191 (OP_Monitor): Drop local variable "op1_names", re-purpose
192 "names" for it instead, and replace former "names" uses by
195 2019-11-07 Jan Beulich <jbeulich@suse.com>
198 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
200 * opcodes/i386-tbl.h: Re-generate.
202 2019-11-05 Jan Beulich <jbeulich@suse.com>
204 * i386-dis.c (OP_Mwaitx): Delete.
205 (prefix_table): Use OP_Mwait for mwaitx entry.
206 (OP_Mwait): Also handle mwaitx.
208 2019-11-05 Jan Beulich <jbeulich@suse.com>
210 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
211 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
212 (prefix_table): Add respective entries.
213 (rm_table): Link to those entries.
215 2019-11-05 Jan Beulich <jbeulich@suse.com>
217 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
218 (REG_0F1C_P_0_MOD_0): ... this.
219 (REG_0F1E_MOD_3): Rename to ...
220 (REG_0F1E_P_1_MOD_3): ... this.
221 (RM_0F01_REG_5): Rename to ...
222 (RM_0F01_REG_5_MOD_3): ... this.
223 (RM_0F01_REG_7): Rename to ...
224 (RM_0F01_REG_7_MOD_3): ... this.
225 (RM_0F1E_MOD_3_REG_7): Rename to ...
226 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
227 (RM_0FAE_REG_6): Rename to ...
228 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
229 (RM_0FAE_REG_7): Rename to ...
230 (RM_0FAE_REG_7_MOD_3): ... this.
231 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
232 (PREFIX_0F01_REG_5_MOD_0): ... this.
233 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
234 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
235 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
236 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
237 (PREFIX_0FAE_REG_0): Rename to ...
238 (PREFIX_0FAE_REG_0_MOD_3): ... this.
239 (PREFIX_0FAE_REG_1): Rename to ...
240 (PREFIX_0FAE_REG_1_MOD_3): ... this.
241 (PREFIX_0FAE_REG_2): Rename to ...
242 (PREFIX_0FAE_REG_2_MOD_3): ... this.
243 (PREFIX_0FAE_REG_3): Rename to ...
244 (PREFIX_0FAE_REG_3_MOD_3): ... this.
245 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
246 (PREFIX_0FAE_REG_4_MOD_0): ... this.
247 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
248 (PREFIX_0FAE_REG_4_MOD_3): ... this.
249 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
250 (PREFIX_0FAE_REG_5_MOD_0): ... this.
251 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
252 (PREFIX_0FAE_REG_5_MOD_3): ... this.
253 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
254 (PREFIX_0FAE_REG_6_MOD_0): ... this.
255 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
256 (PREFIX_0FAE_REG_6_MOD_3): ... this.
257 (PREFIX_0FAE_REG_7): Rename to ...
258 (PREFIX_0FAE_REG_7_MOD_0): ... this.
259 (PREFIX_MOD_0_0FC3): Rename to ...
260 (PREFIX_0FC3_MOD_0): ... this.
261 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
262 (PREFIX_0FC7_REG_6_MOD_0): ... this.
263 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
264 (PREFIX_0FC7_REG_6_MOD_3): ... this.
265 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
266 (PREFIX_0FC7_REG_7_MOD_3): ... this.
267 (reg_table, prefix_table, mod_table, rm_table): Adjust
270 2019-11-04 Nick Clifton <nickc@redhat.com>
272 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
273 of a v850 system register. Move the v850_sreg_names array into
275 (get_v850_reg_name): Likewise for ordinary register names.
276 (get_v850_vreg_name): Likewise for vector register names.
277 (get_v850_cc_name): Likewise for condition codes.
278 * get_v850_float_cc_name): Likewise for floating point condition
280 (get_v850_cacheop_name): Likewise for cache-ops.
281 (get_v850_prefop_name): Likewise for pref-ops.
282 (disassemble): Use the new accessor functions.
284 2019-10-30 Delia Burduv <delia.burduv@arm.com>
286 * aarch64-opc.c (print_immediate_offset_address): Don't print the
287 immediate for the writeback form of ldraa/ldrab if it is 0.
288 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
289 * aarch64-opc-2.c: Regenerated.
291 2019-10-30 Jan Beulich <jbeulich@suse.com>
293 * i386-gen.c (operand_type_shorthands): Delete.
294 (operand_type_init): Expand previous shorthands.
295 (set_bitfield_from_shorthand): Rename back to ...
296 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
297 of operand_type_init[].
298 (set_bitfield): Adjust call to the above function.
299 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
300 RegXMM, RegYMM, RegZMM): Define.
301 * i386-reg.tbl: Expand prior shorthands.
303 2019-10-30 Jan Beulich <jbeulich@suse.com>
305 * i386-gen.c (output_i386_opcode): Change order of fields
307 * i386-opc.h (struct insn_template): Move operands field.
308 Convert extension_opcode field to unsigned short.
309 * i386-tbl.h: Re-generate.
311 2019-10-30 Jan Beulich <jbeulich@suse.com>
313 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
315 * i386-opc.h (W): Extend comment.
316 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
317 general purpose variants not allowing for byte operands.
318 * i386-tbl.h: Re-generate.
320 2019-10-29 Nick Clifton <nickc@redhat.com>
322 * tic30-dis.c (print_branch): Correct size of operand array.
324 2019-10-29 Nick Clifton <nickc@redhat.com>
326 * d30v-dis.c (print_insn): Check that operand index is valid
327 before attempting to access the operands array.
329 2019-10-29 Nick Clifton <nickc@redhat.com>
331 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
332 locating the bit to be tested.
334 2019-10-29 Nick Clifton <nickc@redhat.com>
336 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
338 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
339 (print_insn_s12z): Check for illegal size values.
341 2019-10-28 Nick Clifton <nickc@redhat.com>
343 * csky-dis.c (csky_chars_to_number): Check for a negative
344 count. Use an unsigned integer to construct the return value.
346 2019-10-28 Nick Clifton <nickc@redhat.com>
348 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
349 operand buffer. Set value to 15 not 13.
350 (get_register_operand): Use OPERAND_BUFFER_LEN.
351 (get_indirect_operand): Likewise.
352 (print_two_operand): Likewise.
353 (print_three_operand): Likewise.
354 (print_oar_insn): Likewise.
356 2019-10-28 Nick Clifton <nickc@redhat.com>
358 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
359 (bit_extract_simple): Likewise.
360 (bit_copy): Likewise.
361 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
362 index_offset array are not accessed.
364 2019-10-28 Nick Clifton <nickc@redhat.com>
366 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
369 2019-10-25 Nick Clifton <nickc@redhat.com>
371 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
372 access to opcodes.op array element.
374 2019-10-23 Nick Clifton <nickc@redhat.com>
376 * rx-dis.c (get_register_name): Fix spelling typo in error
378 (get_condition_name, get_flag_name, get_double_register_name)
379 (get_double_register_high_name, get_double_register_low_name)
380 (get_double_control_register_name, get_double_condition_name)
381 (get_opsize_name, get_size_name): Likewise.
383 2019-10-22 Nick Clifton <nickc@redhat.com>
385 * rx-dis.c (get_size_name): New function. Provides safe
386 access to name array.
387 (get_opsize_name): Likewise.
388 (print_insn_rx): Use the accessor functions.
390 2019-10-16 Nick Clifton <nickc@redhat.com>
392 * rx-dis.c (get_register_name): New function. Provides safe
393 access to name array.
394 (get_condition_name, get_flag_name, get_double_register_name)
395 (get_double_register_high_name, get_double_register_low_name)
396 (get_double_control_register_name, get_double_condition_name):
398 (print_insn_rx): Use the accessor functions.
400 2019-10-09 Nick Clifton <nickc@redhat.com>
403 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
406 2019-10-07 Jan Beulich <jbeulich@suse.com>
408 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
409 (cmpsd): Likewise. Move EsSeg to other operand.
410 * opcodes/i386-tbl.h: Re-generate.
412 2019-09-23 Alan Modra <amodra@gmail.com>
414 * m68k-dis.c: Include cpu-m68k.h
416 2019-09-23 Alan Modra <amodra@gmail.com>
418 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
419 "elf/mips.h" earlier.
421 2018-09-20 Jan Beulich <jbeulich@suse.com>
424 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
426 * i386-tbl.h: Re-generate.
428 2019-09-18 Alan Modra <amodra@gmail.com>
430 * arc-ext.c: Update throughout for bfd section macro changes.
432 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
434 * Makefile.in: Re-generate.
435 * configure: Re-generate.
437 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
439 * riscv-opc.c (riscv_opcodes): Change subset field
440 to insn_class field for all instructions.
441 (riscv_insn_types): Likewise.
443 2019-09-16 Phil Blundell <pb@pbcl.net>
445 * configure: Regenerated.
447 2019-09-10 Miod Vallat <miod@online.fr>
450 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
452 2019-09-09 Phil Blundell <pb@pbcl.net>
454 binutils 2.33 branch created.
456 2019-09-03 Nick Clifton <nickc@redhat.com>
459 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
460 greater than zero before indexing via (bufcnt -1).
462 2019-09-03 Nick Clifton <nickc@redhat.com>
465 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
466 (MAX_SPEC_REG_NAME_LEN): Define.
467 (struct mmix_dis_info): Use defined constants for array lengths.
468 (get_reg_name): New function.
469 (get_sprec_reg_name): New function.
470 (print_insn_mmix): Use new functions.
472 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
474 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
475 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
476 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
478 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
480 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
481 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
482 (aarch64_sys_reg_supported_p): Update checks for the above.
484 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
486 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
487 cases MVE_SQRSHRL and MVE_UQRSHLL.
488 (print_insn_mve): Add case for specifier 'k' to check
489 specific bit of the instruction.
491 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
494 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
495 encountering an unknown machine type.
496 (print_insn_arc): Handle arc_insn_length returning 0. In error
497 cases return -1 rather than calling abort.
499 2019-08-07 Jan Beulich <jbeulich@suse.com>
501 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
502 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
504 * i386-tbl.h: Re-generate.
506 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
508 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
511 2019-07-30 Mel Chen <mel.chen@sifive.com>
513 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
514 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
516 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
519 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
521 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
522 and MPY class instructions.
523 (parse_option): Add nps400 option.
524 (print_arc_disassembler_options): Add nps400 info.
526 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
528 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
531 * arc-opc.c (RAD_CHK): Add.
532 * arc-tbl.h: Regenerate.
534 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
536 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
537 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
539 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
541 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
542 instructions as UNPREDICTABLE.
544 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
546 * bpf-desc.c: Regenerated.
548 2019-07-17 Jan Beulich <jbeulich@suse.com>
550 * i386-gen.c (static_assert): Define.
552 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
553 (Opcode_Modifier_Num): ... this.
556 2019-07-16 Jan Beulich <jbeulich@suse.com>
558 * i386-gen.c (operand_types): Move RegMem ...
559 (opcode_modifiers): ... here.
560 * i386-opc.h (RegMem): Move to opcode modifer enum.
561 (union i386_operand_type): Move regmem field ...
562 (struct i386_opcode_modifier): ... here.
563 * i386-opc.tbl (RegMem): Define.
564 (mov, movq): Move RegMem on segment, control, debug, and test
566 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
567 to non-SSE2AVX flavor.
568 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
569 Move RegMem on register only flavors. Drop IgnoreSize from
570 legacy encoding flavors.
571 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
573 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
574 register only flavors.
575 (vmovd): Move RegMem and drop IgnoreSize on register only
576 flavor. Change opcode and operand order to store form.
577 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
579 2019-07-16 Jan Beulich <jbeulich@suse.com>
581 * i386-gen.c (operand_type_init, operand_types): Replace SReg
583 * i386-opc.h (SReg2, SReg3): Replace by ...
585 (union i386_operand_type): Replace sreg fields.
586 * i386-opc.tbl (mov, ): Use SReg.
587 (push, pop): Likewies. Drop i386 and x86-64 specific segment
589 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
590 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
592 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
594 * bpf-desc.c: Regenerate.
595 * bpf-opc.c: Likewise.
596 * bpf-opc.h: Likewise.
598 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
600 * bpf-desc.c: Regenerate.
601 * bpf-opc.c: Likewise.
603 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
605 * arm-dis.c (print_insn_coprocessor): Rename index to
608 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
610 * riscv-opc.c (riscv_insn_types): Add r4 type.
612 * riscv-opc.c (riscv_insn_types): Add b and j type.
614 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
615 format for sb type and correct s type.
617 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
619 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
620 SVE FMOV alias of FCPY.
622 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
624 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
625 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
627 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
629 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
630 registers in an instruction prefixed by MOVPRFX.
632 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
634 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
635 sve_size_13 icode to account for variant behaviour of
637 * aarch64-dis-2.c: Regenerate.
638 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
639 sve_size_13 icode to account for variant behaviour of
641 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
642 (OP_SVE_VVV_Q_D): Add new qualifier.
643 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
644 (struct aarch64_opcode): Split pmull{t,b} into those requiring
647 2019-07-01 Jan Beulich <jbeulich@suse.com>
649 * opcodes/i386-gen.c (operand_type_init): Remove
650 OPERAND_TYPE_VEC_IMM4 entry.
651 (operand_types): Remove Vec_Imm4.
652 * opcodes/i386-opc.h (Vec_Imm4): Delete.
653 (union i386_operand_type): Remove vec_imm4.
654 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
655 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
657 2019-07-01 Jan Beulich <jbeulich@suse.com>
659 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
660 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
661 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
662 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
663 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
664 monitorx, mwaitx): Drop ImmExt from operand-less forms.
665 * i386-tbl.h: Re-generate.
667 2019-07-01 Jan Beulich <jbeulich@suse.com>
669 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
671 * i386-tbl.h: Re-generate.
673 2019-07-01 Jan Beulich <jbeulich@suse.com>
675 * i386-opc.tbl (C): New.
676 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
677 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
678 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
679 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
680 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
681 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
682 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
683 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
684 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
685 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
686 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
687 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
688 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
689 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
690 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
691 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
692 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
693 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
694 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
695 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
696 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
697 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
698 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
699 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
700 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
701 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
703 * i386-tbl.h: Re-generate.
705 2019-07-01 Jan Beulich <jbeulich@suse.com>
707 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
709 * i386-tbl.h: Re-generate.
711 2019-07-01 Jan Beulich <jbeulich@suse.com>
713 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
714 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
715 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
716 * i386-tbl.h: Re-generate.
718 2019-07-01 Jan Beulich <jbeulich@suse.com>
720 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
721 Disp8MemShift from register only templates.
722 * i386-tbl.h: Re-generate.
724 2019-07-01 Jan Beulich <jbeulich@suse.com>
726 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
727 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
728 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
729 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
730 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
731 EVEX_W_0F11_P_3_M_1): Delete.
732 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
733 EVEX_W_0F11_P_3): New.
734 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
735 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
736 MOD_EVEX_0F11_PREFIX_3 table entries.
737 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
738 PREFIX_EVEX_0F11 table entries.
739 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
740 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
741 EVEX_W_0F11_P_3_M_{0,1} table entries.
743 2019-07-01 Jan Beulich <jbeulich@suse.com>
745 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
748 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
751 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
752 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
753 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
754 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
755 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
756 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
757 EVEX_LEN_0F38C7_R_6_P_2_W_1.
758 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
759 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
760 PREFIX_EVEX_0F38C6_REG_6 entries.
761 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
762 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
763 EVEX_W_0F38C7_R_6_P_2 entries.
764 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
765 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
766 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
767 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
768 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
769 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
770 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
772 2019-06-27 Jan Beulich <jbeulich@suse.com>
774 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
775 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
776 VEX_LEN_0F2D_P_3): Delete.
777 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
778 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
779 (prefix_table): ... here.
781 2019-06-27 Jan Beulich <jbeulich@suse.com>
783 * i386-dis.c (Iq): Delete.
785 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
787 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
788 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
789 (OP_E_memory): Also honor needindex when deciding whether an
790 address size prefix needs printing.
791 (OP_I): Remove handling of q_mode. Add handling of d_mode.
793 2019-06-26 Jim Wilson <jimw@sifive.com>
796 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
797 Set info->display_endian to info->endian_code.
799 2019-06-25 Jan Beulich <jbeulich@suse.com>
801 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
802 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
803 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
804 OPERAND_TYPE_ACC64 entries.
805 * i386-init.h: Re-generate.
807 2019-06-25 Jan Beulich <jbeulich@suse.com>
809 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
811 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
813 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
815 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
816 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
818 2019-06-25 Jan Beulich <jbeulich@suse.com>
820 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
823 2019-06-25 Jan Beulich <jbeulich@suse.com>
825 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
826 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
828 * i386-opc.tbl (movnti): Add IgnoreSize.
829 * i386-tbl.h: Re-generate.
831 2019-06-25 Jan Beulich <jbeulich@suse.com>
833 * i386-opc.tbl (and): Mark Imm8S form for optimization.
834 * i386-tbl.h: Re-generate.
836 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
838 * i386-dis-evex.h: Break into ...
839 * i386-dis-evex-len.h: New file.
840 * i386-dis-evex-mod.h: Likewise.
841 * i386-dis-evex-prefix.h: Likewise.
842 * i386-dis-evex-reg.h: Likewise.
843 * i386-dis-evex-w.h: Likewise.
844 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
845 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
848 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
851 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
852 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
854 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
855 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
856 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
857 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
858 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
859 EVEX_LEN_0F385B_P_2_W_1.
860 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
861 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
862 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
863 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
864 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
865 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
866 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
867 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
868 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
869 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
871 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
874 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
875 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
876 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
877 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
878 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
879 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
880 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
881 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
882 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
883 EVEX_LEN_0F3A43_P_2_W_1.
884 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
885 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
886 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
887 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
888 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
889 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
890 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
891 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
892 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
893 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
894 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
895 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
897 2019-06-14 Nick Clifton <nickc@redhat.com>
899 * po/fr.po; Updated French translation.
901 2019-06-13 Stafford Horne <shorne@gmail.com>
903 * or1k-asm.c: Regenerated.
904 * or1k-desc.c: Regenerated.
905 * or1k-desc.h: Regenerated.
906 * or1k-dis.c: Regenerated.
907 * or1k-ibld.c: Regenerated.
908 * or1k-opc.c: Regenerated.
909 * or1k-opc.h: Regenerated.
910 * or1k-opinst.c: Regenerated.
912 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
914 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
916 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
919 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
920 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
921 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
922 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
923 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
924 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
925 EVEX_LEN_0F3A1B_P_2_W_1.
926 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
927 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
928 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
929 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
930 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
931 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
932 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
933 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
935 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
938 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
939 EVEX.vvvv when disassembling VEX and EVEX instructions.
940 (OP_VEX): Set vex.register_specifier to 0 after readding
941 vex.register_specifier.
942 (OP_Vex_2src_1): Likewise.
943 (OP_Vex_2src_2): Likewise.
944 (OP_LWP_E): Likewise.
945 (OP_EX_Vex): Don't check vex.register_specifier.
946 (OP_XMM_Vex): Likewise.
948 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
949 Lili Cui <lili.cui@intel.com>
951 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
952 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
954 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
955 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
956 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
957 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
958 (i386_cpu_flags): Add cpuavx512_vp2intersect.
959 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
960 * i386-init.h: Regenerated.
961 * i386-tbl.h: Likewise.
963 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
964 Lili Cui <lili.cui@intel.com>
966 * doc/c-i386.texi: Document enqcmd.
967 * testsuite/gas/i386/enqcmd-intel.d: New file.
968 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
969 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
970 * testsuite/gas/i386/enqcmd.d: Likewise.
971 * testsuite/gas/i386/enqcmd.s: Likewise.
972 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
973 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
974 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
975 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
976 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
977 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
978 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
981 2019-06-04 Alan Hayward <alan.hayward@arm.com>
983 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
985 2019-06-03 Alan Modra <amodra@gmail.com>
987 * ppc-dis.c (prefix_opcd_indices): Correct size.
989 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
992 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
994 * i386-tbl.h: Regenerated.
996 2019-05-24 Alan Modra <amodra@gmail.com>
998 * po/POTFILES.in: Regenerate.
1000 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1001 Alan Modra <amodra@gmail.com>
1003 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1004 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1005 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1006 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1007 XTOP>): Define and add entries.
1008 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1009 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1010 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1011 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1013 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1014 Alan Modra <amodra@gmail.com>
1016 * ppc-dis.c (ppc_opts): Add "future" entry.
1017 (PREFIX_OPCD_SEGS): Define.
1018 (prefix_opcd_indices): New array.
1019 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1020 (lookup_prefix): New function.
1021 (print_insn_powerpc): Handle 64-bit prefix instructions.
1022 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1023 (PMRR, POWERXX): Define.
1024 (prefix_opcodes): New instruction table.
1025 (prefix_num_opcodes): New constant.
1027 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1029 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1030 * configure: Regenerated.
1031 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1033 (HFILES): Add bpf-desc.h and bpf-opc.h.
1034 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1035 bpf-ibld.c and bpf-opc.c.
1037 * Makefile.in: Regenerated.
1038 * disassemble.c (ARCH_bpf): Define.
1039 (disassembler): Add case for bfd_arch_bpf.
1040 (disassemble_init_for_target): Likewise.
1041 (enum epbf_isa_attr): Define.
1042 * disassemble.h: extern print_insn_bpf.
1043 * bpf-asm.c: Generated.
1044 * bpf-opc.h: Likewise.
1045 * bpf-opc.c: Likewise.
1046 * bpf-ibld.c: Likewise.
1047 * bpf-dis.c: Likewise.
1048 * bpf-desc.h: Likewise.
1049 * bpf-desc.c: Likewise.
1051 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1053 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1054 and VMSR with the new operands.
1056 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1058 * arm-dis.c (enum mve_instructions): New enum
1059 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1061 (mve_opcodes): New instructions as above.
1062 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1064 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1066 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1068 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1069 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1070 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1071 uqshl, urshrl and urshr.
1072 (is_mve_okay_in_it): Add new instructions to TRUE list.
1073 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1074 (print_insn_mve): Updated to accept new %j,
1075 %<bitfield>m and %<bitfield>n patterns.
1077 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1079 * mips-opc.c (mips_builtin_opcodes): Change source register
1080 constraint for DAUI.
1082 2019-05-20 Nick Clifton <nickc@redhat.com>
1084 * po/fr.po: Updated French translation.
1086 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1087 Michael Collison <michael.collison@arm.com>
1089 * arm-dis.c (thumb32_opcodes): Add new instructions.
1090 (enum mve_instructions): Likewise.
1091 (enum mve_undefined): Add new reasons.
1092 (is_mve_encoding_conflict): Handle new instructions.
1093 (is_mve_undefined): Likewise.
1094 (is_mve_unpredictable): Likewise.
1095 (print_mve_undefined): Likewise.
1096 (print_mve_size): Likewise.
1098 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1099 Michael Collison <michael.collison@arm.com>
1101 * arm-dis.c (thumb32_opcodes): Add new instructions.
1102 (enum mve_instructions): Likewise.
1103 (is_mve_encoding_conflict): Handle new instructions.
1104 (is_mve_undefined): Likewise.
1105 (is_mve_unpredictable): Likewise.
1106 (print_mve_size): Likewise.
1108 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1109 Michael Collison <michael.collison@arm.com>
1111 * arm-dis.c (thumb32_opcodes): Add new instructions.
1112 (enum mve_instructions): Likewise.
1113 (is_mve_encoding_conflict): Likewise.
1114 (is_mve_unpredictable): Likewise.
1115 (print_mve_size): Likewise.
1117 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1118 Michael Collison <michael.collison@arm.com>
1120 * arm-dis.c (thumb32_opcodes): Add new instructions.
1121 (enum mve_instructions): Likewise.
1122 (is_mve_encoding_conflict): Handle new instructions.
1123 (is_mve_undefined): Likewise.
1124 (is_mve_unpredictable): Likewise.
1125 (print_mve_size): Likewise.
1127 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1128 Michael Collison <michael.collison@arm.com>
1130 * arm-dis.c (thumb32_opcodes): Add new instructions.
1131 (enum mve_instructions): Likewise.
1132 (is_mve_encoding_conflict): Handle new instructions.
1133 (is_mve_undefined): Likewise.
1134 (is_mve_unpredictable): Likewise.
1135 (print_mve_size): Likewise.
1136 (print_insn_mve): Likewise.
1138 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1139 Michael Collison <michael.collison@arm.com>
1141 * arm-dis.c (thumb32_opcodes): Add new instructions.
1142 (print_insn_thumb32): Handle new instructions.
1144 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1145 Michael Collison <michael.collison@arm.com>
1147 * arm-dis.c (enum mve_instructions): Add new instructions.
1148 (enum mve_undefined): Add new reasons.
1149 (is_mve_encoding_conflict): Handle new instructions.
1150 (is_mve_undefined): Likewise.
1151 (is_mve_unpredictable): Likewise.
1152 (print_mve_undefined): Likewise.
1153 (print_mve_size): Likewise.
1154 (print_mve_shift_n): Likewise.
1155 (print_insn_mve): Likewise.
1157 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1158 Michael Collison <michael.collison@arm.com>
1160 * arm-dis.c (enum mve_instructions): Add new instructions.
1161 (is_mve_encoding_conflict): Handle new instructions.
1162 (is_mve_unpredictable): Likewise.
1163 (print_mve_rotate): Likewise.
1164 (print_mve_size): Likewise.
1165 (print_insn_mve): Likewise.
1167 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1168 Michael Collison <michael.collison@arm.com>
1170 * arm-dis.c (enum mve_instructions): Add new instructions.
1171 (is_mve_encoding_conflict): Handle new instructions.
1172 (is_mve_unpredictable): Likewise.
1173 (print_mve_size): Likewise.
1174 (print_insn_mve): Likewise.
1176 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1177 Michael Collison <michael.collison@arm.com>
1179 * arm-dis.c (enum mve_instructions): Add new instructions.
1180 (enum mve_undefined): Add new reasons.
1181 (is_mve_encoding_conflict): Handle new instructions.
1182 (is_mve_undefined): Likewise.
1183 (is_mve_unpredictable): Likewise.
1184 (print_mve_undefined): Likewise.
1185 (print_mve_size): Likewise.
1186 (print_insn_mve): Likewise.
1188 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1189 Michael Collison <michael.collison@arm.com>
1191 * arm-dis.c (enum mve_instructions): Add new instructions.
1192 (is_mve_encoding_conflict): Handle new instructions.
1193 (is_mve_undefined): Likewise.
1194 (is_mve_unpredictable): Likewise.
1195 (print_mve_size): Likewise.
1196 (print_insn_mve): Likewise.
1198 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1199 Michael Collison <michael.collison@arm.com>
1201 * arm-dis.c (enum mve_instructions): Add new instructions.
1202 (enum mve_unpredictable): Add new reasons.
1203 (enum mve_undefined): Likewise.
1204 (is_mve_okay_in_it): Handle new isntructions.
1205 (is_mve_encoding_conflict): Likewise.
1206 (is_mve_undefined): Likewise.
1207 (is_mve_unpredictable): Likewise.
1208 (print_mve_vmov_index): Likewise.
1209 (print_simd_imm8): Likewise.
1210 (print_mve_undefined): Likewise.
1211 (print_mve_unpredictable): Likewise.
1212 (print_mve_size): Likewise.
1213 (print_insn_mve): Likewise.
1215 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1216 Michael Collison <michael.collison@arm.com>
1218 * arm-dis.c (enum mve_instructions): Add new instructions.
1219 (enum mve_unpredictable): Add new reasons.
1220 (enum mve_undefined): Likewise.
1221 (is_mve_encoding_conflict): Handle new instructions.
1222 (is_mve_undefined): Likewise.
1223 (is_mve_unpredictable): Likewise.
1224 (print_mve_undefined): Likewise.
1225 (print_mve_unpredictable): Likewise.
1226 (print_mve_rounding_mode): Likewise.
1227 (print_mve_vcvt_size): Likewise.
1228 (print_mve_size): Likewise.
1229 (print_insn_mve): Likewise.
1231 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1232 Michael Collison <michael.collison@arm.com>
1234 * arm-dis.c (enum mve_instructions): Add new instructions.
1235 (enum mve_unpredictable): Add new reasons.
1236 (enum mve_undefined): Likewise.
1237 (is_mve_undefined): Handle new instructions.
1238 (is_mve_unpredictable): Likewise.
1239 (print_mve_undefined): Likewise.
1240 (print_mve_unpredictable): Likewise.
1241 (print_mve_size): Likewise.
1242 (print_insn_mve): Likewise.
1244 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1245 Michael Collison <michael.collison@arm.com>
1247 * arm-dis.c (enum mve_instructions): Add new instructions.
1248 (enum mve_undefined): Add new reasons.
1249 (insns): Add new instructions.
1250 (is_mve_encoding_conflict):
1251 (print_mve_vld_str_addr): New print function.
1252 (is_mve_undefined): Handle new instructions.
1253 (is_mve_unpredictable): Likewise.
1254 (print_mve_undefined): Likewise.
1255 (print_mve_size): Likewise.
1256 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1257 (print_insn_mve): Handle new operands.
1259 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1260 Michael Collison <michael.collison@arm.com>
1262 * arm-dis.c (enum mve_instructions): Add new instructions.
1263 (enum mve_unpredictable): Add new reasons.
1264 (is_mve_encoding_conflict): Handle new instructions.
1265 (is_mve_unpredictable): Likewise.
1266 (mve_opcodes): Add new instructions.
1267 (print_mve_unpredictable): Handle new reasons.
1268 (print_mve_register_blocks): New print function.
1269 (print_mve_size): Handle new instructions.
1270 (print_insn_mve): Likewise.
1272 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1273 Michael Collison <michael.collison@arm.com>
1275 * arm-dis.c (enum mve_instructions): Add new instructions.
1276 (enum mve_unpredictable): Add new reasons.
1277 (enum mve_undefined): Likewise.
1278 (is_mve_encoding_conflict): Handle new instructions.
1279 (is_mve_undefined): Likewise.
1280 (is_mve_unpredictable): Likewise.
1281 (coprocessor_opcodes): Move NEON VDUP from here...
1282 (neon_opcodes): ... to here.
1283 (mve_opcodes): Add new instructions.
1284 (print_mve_undefined): Handle new reasons.
1285 (print_mve_unpredictable): Likewise.
1286 (print_mve_size): Handle new instructions.
1287 (print_insn_neon): Handle vdup.
1288 (print_insn_mve): Handle new operands.
1290 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1291 Michael Collison <michael.collison@arm.com>
1293 * arm-dis.c (enum mve_instructions): Add new instructions.
1294 (enum mve_unpredictable): Add new values.
1295 (mve_opcodes): Add new instructions.
1296 (vec_condnames): New array with vector conditions.
1297 (mve_predicatenames): New array with predicate suffixes.
1298 (mve_vec_sizename): New array with vector sizes.
1299 (enum vpt_pred_state): New enum with vector predication states.
1300 (struct vpt_block): New struct type for vpt blocks.
1301 (vpt_block_state): Global struct to keep track of state.
1302 (mve_extract_pred_mask): New helper function.
1303 (num_instructions_vpt_block): Likewise.
1304 (mark_outside_vpt_block): Likewise.
1305 (mark_inside_vpt_block): Likewise.
1306 (invert_next_predicate_state): Likewise.
1307 (update_next_predicate_state): Likewise.
1308 (update_vpt_block_state): Likewise.
1309 (is_vpt_instruction): Likewise.
1310 (is_mve_encoding_conflict): Add entries for new instructions.
1311 (is_mve_unpredictable): Likewise.
1312 (print_mve_unpredictable): Handle new cases.
1313 (print_instruction_predicate): Likewise.
1314 (print_mve_size): New function.
1315 (print_vec_condition): New function.
1316 (print_insn_mve): Handle vpt blocks and new print operands.
1318 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1320 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1321 8, 14 and 15 for Armv8.1-M Mainline.
1323 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1324 Michael Collison <michael.collison@arm.com>
1326 * arm-dis.c (enum mve_instructions): New enum.
1327 (enum mve_unpredictable): Likewise.
1328 (enum mve_undefined): Likewise.
1329 (struct mopcode32): New struct.
1330 (is_mve_okay_in_it): New function.
1331 (is_mve_architecture): Likewise.
1332 (arm_decode_field): Likewise.
1333 (arm_decode_field_multiple): Likewise.
1334 (is_mve_encoding_conflict): Likewise.
1335 (is_mve_undefined): Likewise.
1336 (is_mve_unpredictable): Likewise.
1337 (print_mve_undefined): Likewise.
1338 (print_mve_unpredictable): Likewise.
1339 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1340 (print_insn_mve): New function.
1341 (print_insn_thumb32): Handle MVE architecture.
1342 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1344 2019-05-10 Nick Clifton <nickc@redhat.com>
1347 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1348 end of the table prematurely.
1350 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1352 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1355 2019-05-11 Alan Modra <amodra@gmail.com>
1357 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1358 when -Mraw is in effect.
1360 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1362 * aarch64-dis-2.c: Regenerate.
1363 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1364 (OP_SVE_BBB): New variant set.
1365 (OP_SVE_DDDD): New variant set.
1366 (OP_SVE_HHH): New variant set.
1367 (OP_SVE_HHHU): New variant set.
1368 (OP_SVE_SSS): New variant set.
1369 (OP_SVE_SSSU): New variant set.
1370 (OP_SVE_SHH): New variant set.
1371 (OP_SVE_SBBU): New variant set.
1372 (OP_SVE_DSS): New variant set.
1373 (OP_SVE_DHHU): New variant set.
1374 (OP_SVE_VMV_HSD_BHS): New variant set.
1375 (OP_SVE_VVU_HSD_BHS): New variant set.
1376 (OP_SVE_VVVU_SD_BH): New variant set.
1377 (OP_SVE_VVVU_BHSD): New variant set.
1378 (OP_SVE_VVV_QHD_DBS): New variant set.
1379 (OP_SVE_VVV_HSD_BHS): New variant set.
1380 (OP_SVE_VVV_HSD_BHS2): New variant set.
1381 (OP_SVE_VVV_BHS_HSD): New variant set.
1382 (OP_SVE_VV_BHS_HSD): New variant set.
1383 (OP_SVE_VVV_SD): New variant set.
1384 (OP_SVE_VVU_BHS_HSD): New variant set.
1385 (OP_SVE_VZVV_SD): New variant set.
1386 (OP_SVE_VZVV_BH): New variant set.
1387 (OP_SVE_VZV_SD): New variant set.
1388 (aarch64_opcode_table): Add sve2 instructions.
1390 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1392 * aarch64-asm-2.c: Regenerated.
1393 * aarch64-dis-2.c: Regenerated.
1394 * aarch64-opc-2.c: Regenerated.
1395 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1396 for SVE_SHLIMM_UNPRED_22.
1397 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1398 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1401 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1403 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1404 sve_size_tsz_bhs iclass encode.
1405 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1406 sve_size_tsz_bhs iclass decode.
1408 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1410 * aarch64-asm-2.c: Regenerated.
1411 * aarch64-dis-2.c: Regenerated.
1412 * aarch64-opc-2.c: Regenerated.
1413 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1414 for SVE_Zm4_11_INDEX.
1415 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1416 (fields): Handle SVE_i2h field.
1417 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1418 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1420 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1422 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1423 sve_shift_tsz_bhsd iclass encode.
1424 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1425 sve_shift_tsz_bhsd iclass decode.
1427 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1429 * aarch64-asm-2.c: Regenerated.
1430 * aarch64-dis-2.c: Regenerated.
1431 * aarch64-opc-2.c: Regenerated.
1432 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1433 (aarch64_encode_variant_using_iclass): Handle
1434 sve_shift_tsz_hsd iclass encode.
1435 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1436 sve_shift_tsz_hsd iclass decode.
1437 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1438 for SVE_SHRIMM_UNPRED_22.
1439 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1440 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1443 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1445 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1446 sve_size_013 iclass encode.
1447 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1448 sve_size_013 iclass decode.
1450 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1452 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1453 sve_size_bh iclass encode.
1454 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1455 sve_size_bh iclass decode.
1457 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1459 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1460 sve_size_sd2 iclass encode.
1461 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1462 sve_size_sd2 iclass decode.
1463 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1464 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1466 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1468 * aarch64-asm-2.c: Regenerated.
1469 * aarch64-dis-2.c: Regenerated.
1470 * aarch64-opc-2.c: Regenerated.
1471 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1473 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1474 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1476 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1478 * aarch64-asm-2.c: Regenerated.
1479 * aarch64-dis-2.c: Regenerated.
1480 * aarch64-opc-2.c: Regenerated.
1481 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1482 for SVE_Zm3_11_INDEX.
1483 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1484 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1485 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1487 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1489 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1491 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1492 sve_size_hsd2 iclass encode.
1493 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1494 sve_size_hsd2 iclass decode.
1495 * aarch64-opc.c (fields): Handle SVE_size field.
1496 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1498 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1500 * aarch64-asm-2.c: Regenerated.
1501 * aarch64-dis-2.c: Regenerated.
1502 * aarch64-opc-2.c: Regenerated.
1503 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1505 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1506 (fields): Handle SVE_rot3 field.
1507 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1508 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1510 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1512 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1515 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1518 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1519 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1520 aarch64_feature_sve2bitperm): New feature sets.
1521 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1522 for feature set addresses.
1523 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1524 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1526 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1527 Faraz Shahbazker <fshahbazker@wavecomp.com>
1529 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1530 argument and set ASE_EVA_R6 appropriately.
1531 (set_default_mips_dis_options): Pass ISA to above.
1532 (parse_mips_dis_option): Likewise.
1533 * mips-opc.c (EVAR6): New macro.
1534 (mips_builtin_opcodes): Add llwpe, scwpe.
1536 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1538 * aarch64-asm-2.c: Regenerated.
1539 * aarch64-dis-2.c: Regenerated.
1540 * aarch64-opc-2.c: Regenerated.
1541 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1542 AARCH64_OPND_TME_UIMM16.
1543 (aarch64_print_operand): Likewise.
1544 * aarch64-tbl.h (QL_IMM_NIL): New.
1547 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1549 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1551 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1553 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1554 Faraz Shahbazker <fshahbazker@wavecomp.com>
1556 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1558 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1560 * s12z-opc.h: Add extern "C" bracketing to help
1561 users who wish to use this interface in c++ code.
1563 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1565 * s12z-opc.c (bm_decode): Handle bit map operations with the
1568 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1570 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1571 specifier. Add entries for VLDR and VSTR of system registers.
1572 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1573 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1574 of %J and %K format specifier.
1576 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1578 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1579 Add new entries for VSCCLRM instruction.
1580 (print_insn_coprocessor): Handle new %C format control code.
1582 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1584 * arm-dis.c (enum isa): New enum.
1585 (struct sopcode32): New structure.
1586 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1587 set isa field of all current entries to ANY.
1588 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1589 Only match an entry if its isa field allows the current mode.
1591 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1593 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1595 (print_insn_thumb32): Add logic to print %n CLRM register list.
1597 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1599 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1602 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1604 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1605 (print_insn_thumb32): Edit the switch case for %Z.
1607 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1609 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1611 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1613 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1615 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1617 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1619 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1621 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1622 Arm register with r13 and r15 unpredictable.
1623 (thumb32_opcodes): New instructions for bfx and bflx.
1625 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1627 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1629 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1631 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1633 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1635 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1637 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1639 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1641 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1643 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1644 "optr". ("operator" is a reserved word in c++).
1646 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1648 * aarch64-opc.c (aarch64_print_operand): Add case for
1650 (verify_constraints): Likewise.
1651 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1652 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1653 to accept Rt|SP as first operand.
1654 (AARCH64_OPERANDS): Add new Rt_SP.
1655 * aarch64-asm-2.c: Regenerated.
1656 * aarch64-dis-2.c: Regenerated.
1657 * aarch64-opc-2.c: Regenerated.
1659 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1661 * aarch64-asm-2.c: Regenerated.
1662 * aarch64-dis-2.c: Likewise.
1663 * aarch64-opc-2.c: Likewise.
1664 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1666 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1668 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1670 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1672 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1673 * i386-init.h: Regenerated.
1675 2019-04-07 Alan Modra <amodra@gmail.com>
1677 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1678 op_separator to control printing of spaces, comma and parens
1679 rather than need_comma, need_paren and spaces vars.
1681 2019-04-07 Alan Modra <amodra@gmail.com>
1684 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1685 (print_insn_neon, print_insn_arm): Likewise.
1687 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1689 * i386-dis-evex.h (evex_table): Updated to support BF16
1691 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1692 and EVEX_W_0F3872_P_3.
1693 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1694 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1695 * i386-opc.h (enum): Add CpuAVX512_BF16.
1696 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1697 * i386-opc.tbl: Add AVX512 BF16 instructions.
1698 * i386-init.h: Regenerated.
1699 * i386-tbl.h: Likewise.
1701 2019-04-05 Alan Modra <amodra@gmail.com>
1703 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1704 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1705 to favour printing of "-" branch hint when using the "y" bit.
1706 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1708 2019-04-05 Alan Modra <amodra@gmail.com>
1710 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1711 opcode until first operand is output.
1713 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1716 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1717 (valid_bo_post_v2): Add support for 'at' branch hints.
1718 (insert_bo): Only error on branch on ctr.
1719 (get_bo_hint_mask): New function.
1720 (insert_boe): Add new 'branch_taken' formal argument. Add support
1721 for inserting 'at' branch hints.
1722 (extract_boe): Add new 'branch_taken' formal argument. Add support
1723 for extracting 'at' branch hints.
1724 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1725 (BOE): Delete operand.
1726 (BOM, BOP): New operands.
1728 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1729 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1730 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1731 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1732 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1733 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1734 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1735 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1736 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1737 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1738 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1739 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1740 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1741 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1742 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1743 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1744 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1745 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1746 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1747 bttarl+>: New extended mnemonics.
1749 2019-03-28 Alan Modra <amodra@gmail.com>
1752 * ppc-opc.c (BTF): Define.
1753 (powerpc_opcodes): Use for mtfsb*.
1754 * ppc-dis.c (print_insn_powerpc): Print fields with both
1755 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1757 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1759 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1760 (mapping_symbol_for_insn): Implement new algorithm.
1761 (print_insn): Remove duplicate code.
1763 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1765 * aarch64-dis.c (print_insn_aarch64):
1768 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1770 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1773 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1775 * aarch64-dis.c (last_stop_offset): New.
1776 (print_insn_aarch64): Use stop_offset.
1778 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1781 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1783 * i386-init.h: Regenerated.
1785 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1788 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1789 vmovdqu16, vmovdqu32 and vmovdqu64.
1790 * i386-tbl.h: Regenerated.
1792 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1794 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1795 from vstrszb, vstrszh, and vstrszf.
1797 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1799 * s390-opc.txt: Add instruction descriptions.
1801 2019-02-08 Jim Wilson <jimw@sifive.com>
1803 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1806 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1808 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1810 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1813 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1814 * aarch64-opc.c (verify_elem_sd): New.
1815 (fields): Add FLD_sz entr.
1816 * aarch64-tbl.h (_SIMD_INSN): New.
1817 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1818 fmulx scalar and vector by element isns.
1820 2019-02-07 Nick Clifton <nickc@redhat.com>
1822 * po/sv.po: Updated Swedish translation.
1824 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1826 * s390-mkopc.c (main): Accept arch13 as cpu string.
1827 * s390-opc.c: Add new instruction formats and instruction opcode
1829 * s390-opc.txt: Add new arch13 instructions.
1831 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1833 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1834 (aarch64_opcode): Change encoding for stg, stzg
1836 * aarch64-asm-2.c: Regenerated.
1837 * aarch64-dis-2.c: Regenerated.
1838 * aarch64-opc-2.c: Regenerated.
1840 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1842 * aarch64-asm-2.c: Regenerated.
1843 * aarch64-dis-2.c: Likewise.
1844 * aarch64-opc-2.c: Likewise.
1845 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1847 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1848 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1850 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1851 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1852 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1853 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1854 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1855 case for ldstgv_indexed.
1856 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1857 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1858 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1859 * aarch64-asm-2.c: Regenerated.
1860 * aarch64-dis-2.c: Regenerated.
1861 * aarch64-opc-2.c: Regenerated.
1863 2019-01-23 Nick Clifton <nickc@redhat.com>
1865 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1867 2019-01-21 Nick Clifton <nickc@redhat.com>
1869 * po/de.po: Updated German translation.
1870 * po/uk.po: Updated Ukranian translation.
1872 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1873 * mips-dis.c (mips_arch_choices): Fix typo in
1874 gs464, gs464e and gs264e descriptors.
1876 2019-01-19 Nick Clifton <nickc@redhat.com>
1878 * configure: Regenerate.
1879 * po/opcodes.pot: Regenerate.
1881 2018-06-24 Nick Clifton <nickc@redhat.com>
1883 2.32 branch created.
1885 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1887 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1889 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1892 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1894 * configure: Regenerate.
1896 2019-01-07 Alan Modra <amodra@gmail.com>
1898 * configure: Regenerate.
1899 * po/POTFILES.in: Regenerate.
1901 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1903 * s12z-opc.c: New file.
1904 * s12z-opc.h: New file.
1905 * s12z-dis.c: Removed all code not directly related to display
1906 of instructions. Used the interface provided by the new files
1908 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1909 * Makefile.in: Regenerate.
1910 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1911 * configure: Regenerate.
1913 2019-01-01 Alan Modra <amodra@gmail.com>
1915 Update year range in copyright notice of all files.
1917 For older changes see ChangeLog-2018
1919 Copyright (C) 2019 Free Software Foundation, Inc.
1921 Copying and distribution of this file, with or without modification,
1922 are permitted in any medium without royalty provided the copyright
1923 notice and this notice are preserved.
1929 version-control: never