opcodes/ChangeLog

   1 2011-09-27  David S. Miller  <davem@davemloft.net>
   2
   3         * sparc-opc.c (sparc_opcodes): Fix random instruction to write
   4         to a float instead of an integer register.
   5
   6 2011-09-26  David S. Miller  <davem@davemloft.net>
   7
   8         * sparc-opc.c (sparc_opcodes): Add integer multiply-add
   9         instructions.
  10
  11 2011-09-21  David S. Miller  <davem@davemloft.net>
  12
  13         * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
  14         bits.  Fix "fchksm16" mnemonic.
  15
  16 2011-09-08  Mark Fortescue <mark@mtfhpc.demon.co.uk>
  17
  18         The changes below bring 'mov' and 'ticc' instructions into line
  19         with the V8 SPARC Architecture Manual.
  20         * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
  21         * sparc-opc.c (sparc_opcodes): Add alias entries for
  22         'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
  23         'mov regrs2,%wim' and 'mov regrs2,%tbr'.
  24         * sparc-opc.c (sparc_opcodes): Move/Change entries for
  25         'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
  26         and 'mov imm,%tbr'.
  27         * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
  28         mov aliases.
  29
  30         * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
  31         This has been reported as being accepted by the Sun assmebler.
  32
  33 2011-09-08  David S. Miller  <davem@davemloft.net>
  34
  35         * sparc-opc.c (pdistn): Destination is integer not float register.
  36
  37 2011-09-07  Andreas Schwab  <schwab@linux-m68k.org>
  38
  39         PR gas/13145
  40         * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
  41
  42 2011-08-26  Nick Clifton  <nickc@redhat.com>
  43
  44         * po/es.po: Updated Spanish translation.
  45
  46 2011-08-22  Nick Clifton  <nickc@redhat.com>
  47
  48         * Makefile.am (CPUDIR): Redfine to point to top level cpu
  49         directory.
  50         (stamp-frv): Use CPUDIR.
  51         (stamp-iq2000): Likewise.
  52         (stamp-lm32): Likewise.
  53         (stamp-m32c): Likewise.
  54         (stamp-mt): Likewise.
  55         (stamp-xc16x): Likewise.
  56         * Makefile.in: Regenerate.
  57
  58 2011-08-09  Chao-ying Fu  <fu@mips.com>
  59             Maciej W. Rozycki  <macro@codesourcery.com>
  60
  61         * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
  62         and "mips64r2".
  63         (print_insn_args, print_insn_micromips): Handle MCU.
  64         * micromips-opc.c (MC): New macro.
  65         (micromips_opcodes): Add "aclr", "aset" and "iret".
  66         * mips-opc.c (MC): New macro.
  67         (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
  68
  69 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
  70
  71         * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
  72         (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
  73         (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
  74         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
  75         (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
  76         (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
  77         (WR_s): Update macro.
  78         (micromips_opcodes): Update register use flags of: "addiu",
  79         "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
  80         "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
  81         "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
  82         "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
  83         "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
  84         "swm" and "xor" instructions.
  85
  86 2011-08-05  David S. Miller  <davem@davemloft.net>
  87
  88         * sparc-dis.c (v9a_ast_reg_names): Add "cps".
  89         (X_RS3): New macro.
  90         (print_insn_sparc): Handle '4', '5', and '(' format codes.
  91         Accept %asr numbers below 28.
  92         * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
  93         instructions.
  94
  95 2011-08-02  Quentin Neill  <quentin.neill@amd.com>
  96
  97         * i386-dis.c (xop_table): Remove spurious bextr insn.
  98
  99 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 100
 101         PR ld/13048
 102         * i386-dis.c (print_insn): Optimize info->mach check.
 103
 104 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 105
 106         PR gas/13046
 107         * i386-opc.tbl: Add Disp32S to 64bit call.
 108         * i386-tbl.h: Regenerated.
 109
 110 2011-07-24  Chao-ying Fu  <fu@mips.com>
 111             Maciej W. Rozycki  <macro@codesourcery.com>
 112
 113         * micromips-opc.c: New file.
 114         * mips-dis.c (micromips_to_32_reg_b_map): New array.
 115         (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
 116         (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
 117         (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
 118         (micromips_to_32_reg_q_map): Likewise.
 119         (micromips_imm_b_map, micromips_imm_c_map): Likewise.
 120         (micromips_ase): New variable.
 121         (is_micromips): New function.
 122         (set_default_mips_dis_options): Handle microMIPS ASE.
 123         (print_insn_micromips): New function.
 124         (is_compressed_mode_p): Likewise.
 125         (_print_insn_mips): Handle microMIPS instructions.
 126         * Makefile.am (CFILES): Add micromips-opc.c.
 127         * configure.in (bfd_mips_arch): Add micromips-opc.lo.
 128         * Makefile.in: Regenerate.
 129         * configure: Regenerate.
 130
 131         * mips-dis.c (micromips_to_32_reg_h_map): New variable.
 132         (micromips_to_32_reg_i_map): Likewise.
 133         (micromips_to_32_reg_m_map): Likewise.
 134         (micromips_to_32_reg_n_map): New macro.
 135
 136 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 137
 138         * mips-opc.c (NODS): New macro.
 139         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 140         (DSP_VOLA): Likewise.
 141         (mips_builtin_opcodes): Add NODS annotation to "deret" and
 142         "eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
 143         place of TRAP for "wait", "waiti" and "yield".
 144         * mips16-opc.c (NODS): New macro.
 145         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 146         (mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
 147         "restore" and "save".
 148
 149 2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         * configure.in: Handle bfd_k1om_arch.
 152         * configure: Regenerated.
 153
 154         * disassemble.c (disassembler): Handle bfd_k1om_arch.
 155
 156         * i386-dis.c (print_insn): Handle bfd_mach_k1om and
 157         bfd_mach_k1om_intel_syntax.
 158
 159         * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
 160         ~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
 161         (cpu_flags): Add CpuK1OM.
 162
 163         * i386-opc.h (CpuK1OM): New.
 164         (i386_cpu_flags): Add cpuk1om.
 165
 166         * i386-init.h: Regenerated.
 167         * i386-tbl.h: Likewise.
 168
 169 2011-07-12  Nick Clifton  <nickc@redhat.com>
 170
 171         * arm-dis.c (print_insn_arm): Revert previous, undocumented,
 172         accidental change.
 173
 174 2011-07-01  Nick Clifton  <nickc@redhat.com>
 175
 176         PR binutils/12329
 177         * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
 178         insns using post-increment addressing.
 179
 180 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 181
 182         * i386-dis.c (vex_len_table): Update rorxS.
 183
 184 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 185
 186         AVX Programming Reference (June, 2011)
 187         * i386-dis.c (vex_len_table): Correct rorxS.
 188
 189         * i386-opc.tbl: Correct rorx.
 190         * i386-tbl.h: Regenerated.
 191
 192 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
 193
 194         * tilegx-opc.c (find_opcode): Replace "index" with "i".
 195         * tilepro-opc.c (find_opcode): Likewise.
 196
 197 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
 198
 199         * mips16-opc.c (jalrc, jrc): Move earlier in file.
 200
 201 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 202
 203         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
 204         PREFIX_VEX_0F388E.
 205
 206 2011-06-17  Andreas Schwab  <schwab@redhat.com>
 207
 208         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
 209         (MOSTLYCLEANFILES): ... here.
 210         * Makefile.in: Regenerate.
 211
 212 2011-06-14  Alan Modra  <amodra@gmail.com>
 213
 214         * Makefile.in: Regenerate.
 215
 216 2011-06-13  Walter Lee  <walt@tilera.com>
 217
 218         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
 219         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
 220         * Makefile.in: Regenerate.
 221         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
 222         * configure: Regenerate.
 223         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
 224         * po/POTFILES.in: Regenerate.
 225         * tilegx-dis.c: New file.
 226         * tilegx-opc.c: New file.
 227         * tilepro-dis.c: New file.
 228         * tilepro-opc.c: New file.
 229
 230 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         AVX Programming Reference (June, 2011)
 233         * i386-dis.c (XMGatherQ): New.
 234         * i386-dis.c (EXxmm_mb): New.
 235         (EXxmm_mb): Likewise.
 236         (EXxmm_mw): Likewise.
 237         (EXxmm_md): Likewise.
 238         (EXxmm_mq): Likewise.
 239         (EXxmmdw): Likewise.
 240         (EXxmmqd): Likewise.
 241         (VexGatherQ): Likewise.
 242         (MVexVSIBDWpX): Likewise.
 243         (MVexVSIBQWpX): Likewise.
 244         (xmm_mb_mode): Likewise.
 245         (xmm_mw_mode): Likewise.
 246         (xmm_md_mode): Likewise.
 247         (xmm_mq_mode): Likewise.
 248         (xmmdw_mode): Likewise.
 249         (xmmqd_mode): Likewise.
 250         (ymmxmm_mode): Likewise.
 251         (vex_vsib_d_w_dq_mode): Likewise.
 252         (vex_vsib_q_w_dq_mode): Likewise.
 253         (MOD_VEX_0F385A_PREFIX_2): Likewise.
 254         (MOD_VEX_0F388C_PREFIX_2): Likewise.
 255         (MOD_VEX_0F388E_PREFIX_2): Likewise.
 256         (PREFIX_0F3882): Likewise.
 257         (PREFIX_VEX_0F3816): Likewise.
 258         (PREFIX_VEX_0F3836): Likewise.
 259         (PREFIX_VEX_0F3845): Likewise.
 260         (PREFIX_VEX_0F3846): Likewise.
 261         (PREFIX_VEX_0F3847): Likewise.
 262         (PREFIX_VEX_0F3858): Likewise.
 263         (PREFIX_VEX_0F3859): Likewise.
 264         (PREFIX_VEX_0F385A): Likewise.
 265         (PREFIX_VEX_0F3878): Likewise.
 266         (PREFIX_VEX_0F3879): Likewise.
 267         (PREFIX_VEX_0F388C): Likewise.
 268         (PREFIX_VEX_0F388E): Likewise.
 269         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
 270         (PREFIX_VEX_0F38F5): Likewise.
 271         (PREFIX_VEX_0F38F6): Likewise.
 272         (PREFIX_VEX_0F3A00): Likewise.
 273         (PREFIX_VEX_0F3A01): Likewise.
 274         (PREFIX_VEX_0F3A02): Likewise.
 275         (PREFIX_VEX_0F3A38): Likewise.
 276         (PREFIX_VEX_0F3A39): Likewise.
 277         (PREFIX_VEX_0F3A46): Likewise.
 278         (PREFIX_VEX_0F3AF0): Likewise.
 279         (VEX_LEN_0F3816_P_2): Likewise.
 280         (VEX_LEN_0F3819_P_2): Likewise.
 281         (VEX_LEN_0F3836_P_2): Likewise.
 282         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 283         (VEX_LEN_0F38F5_P_0): Likewise.
 284         (VEX_LEN_0F38F5_P_1): Likewise.
 285         (VEX_LEN_0F38F5_P_3): Likewise.
 286         (VEX_LEN_0F38F6_P_3): Likewise.
 287         (VEX_LEN_0F38F7_P_1): Likewise.
 288         (VEX_LEN_0F38F7_P_2): Likewise.
 289         (VEX_LEN_0F38F7_P_3): Likewise.
 290         (VEX_LEN_0F3A00_P_2): Likewise.
 291         (VEX_LEN_0F3A01_P_2): Likewise.
 292         (VEX_LEN_0F3A38_P_2): Likewise.
 293         (VEX_LEN_0F3A39_P_2): Likewise.
 294         (VEX_LEN_0F3A46_P_2): Likewise.
 295         (VEX_LEN_0F3AF0_P_3): Likewise.
 296         (VEX_W_0F3816_P_2): Likewise.
 297         (VEX_W_0F3818_P_2): Likewise.
 298         (VEX_W_0F3819_P_2): Likewise.
 299         (VEX_W_0F3836_P_2): Likewise.
 300         (VEX_W_0F3846_P_2): Likewise.
 301         (VEX_W_0F3858_P_2): Likewise.
 302         (VEX_W_0F3859_P_2): Likewise.
 303         (VEX_W_0F385A_P_2_M_0): Likewise.
 304         (VEX_W_0F3878_P_2): Likewise.
 305         (VEX_W_0F3879_P_2): Likewise.
 306         (VEX_W_0F3A00_P_2): Likewise.
 307         (VEX_W_0F3A01_P_2): Likewise.
 308         (VEX_W_0F3A02_P_2): Likewise.
 309         (VEX_W_0F3A38_P_2): Likewise.
 310         (VEX_W_0F3A39_P_2): Likewise.
 311         (VEX_W_0F3A46_P_2): Likewise.
 312         (MOD_VEX_0F3818_PREFIX_2): Removed.
 313         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 314         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 315         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 316         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 317         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 318         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 319         (VEX_LEN_0F3A0E_P_2): Likewise.
 320         (VEX_LEN_0F3A0F_P_2): Likewise.
 321         (VEX_LEN_0F3A42_P_2): Likewise.
 322         (VEX_LEN_0F3A4C_P_2): Likewise.
 323         (VEX_W_0F3818_P_2_M_0): Likewise.
 324         (VEX_W_0F3819_P_2_M_0): Likewise.
 325         (prefix_table): Updated.
 326         (three_byte_table): Likewise.
 327         (vex_table): Likewise.
 328         (vex_len_table): Likewise.
 329         (vex_w_table): Likewise.
 330         (mod_table): Likewise.
 331         (putop): Handle "LW".
 332         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 333         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 334         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 335         (OP_EX): Likewise.
 336         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 337         vex_vsib_q_w_dq_mode.
 338         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 339         (OP_VEX): Likewise.
 340
 341         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 342         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 343         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 344         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 345         (opcode_modifiers): Add VecSIB.
 346
 347         * i386-opc.h (CpuAVX2): New.
 348         (CpuBMI2): Likewise.
 349         (CpuLZCNT): Likewise.
 350         (CpuINVPCID): Likewise.
 351         (VecSIB128): Likewise.
 352         (VecSIB256): Likewise.
 353         (VecSIB): Likewise.
 354         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 355         (i386_opcode_modifier): Add vecsib.
 356
 357         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 358         * i386-init.h: Regenerated.
 359         * i386-tbl.h: Likewise.
 360
 361 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 362
 363         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 364         * i386-init.h: Regenerated.
 365
 366 2011-06-03  Nick Clifton  <nickc@redhat.com>
 367
 368         PR binutils/12752
 369         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 370         computing address offsets.
 371         (print_arm_address): Likewise.
 372         (print_insn_arm): Likewise.
 373         (print_insn_thumb16): Likewise.
 374         (print_insn_thumb32): Likewise.
 375
 376 2011-06-02  Jie Zhang <jie@codesourcery.com>
 377             Nathan Sidwell <nathan@codesourcery.com>
 378             Maciej Rozycki <macro@codesourcery.com>
 379
 380         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 381         as address offset.
 382         (print_arm_address): Likewise. Elide positive #0 appropriately.
 383         (print_insn_arm): Likewise.
 384
 385 2011-06-02  Nick Clifton  <nickc@redhat.com>
 386
 387         PR gas/12752
 388         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 389         passed to print_address_func.
 390
 391 2011-06-02  Nick Clifton  <nickc@redhat.com>
 392
 393         * arm-dis.c: Fix spelling mistakes.
 394         * op/opcodes.pot: Regenerate.
 395
 396 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 397
 398         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 399         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 400         * s390-opc.txt: Fix cxr instruction type.
 401
 402 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 403
 404         * s390-opc.c: Add new instruction types marking register pair
 405         operands.
 406         * s390-opc.txt: Match instructions having register pair operands
 407         to the new instruction types.
 408
 409 2011-05-19  Nick Clifton  <nickc@redhat.com>
 410
 411         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 412         operands.
 413
 414 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 415
 416         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 417         * i386-init.h: Regenerated.
 418
 419 2011-04-27  Nick Clifton  <nickc@redhat.com>
 420
 421         * po/da.po: Updated Danish translation.
 422
 423 2011-04-26  Anton Blanchard  <anton@samba.org>
 424
 425         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 426
 427 2011-04-21  DJ Delorie  <dj@redhat.com>
 428
 429         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 430         * rx-decode.c: Regenerate.
 431
 432 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 433
 434         * i386-init.h: Regenerated.
 435
 436 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 437
 438         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 439         from bdver1 flags.
 440
 441 2011-04-13  Nick Clifton  <nickc@redhat.com>
 442
 443         * v850-dis.c (disassemble): Always print a closing square brace if
 444         an opening square brace was printed.
 445
 446 2011-04-12  Nick Clifton  <nickc@redhat.com>
 447
 448         PR binutils/12534
 449         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 450         patterns.
 451         (print_insn_thumb32): Handle %L.
 452
 453 2011-04-11  Julian Brown  <julian@codesourcery.com>
 454
 455         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 456         (print_insn_thumb32): Add APSR bitmask support.
 457
 458 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 459
 460         * arm-dis.c (print_insn): init vars moved into private_data structure.
 461
 462 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 463
 464         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 465
 466 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 467
 468         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 469         post-increment to support LPM Z+ instruction. Add support for 'E'
 470         constraint for DES instruction.
 471         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 472
 473 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 474
 475         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 476
 477 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 478
 479         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 480         Use branch types instead.
 481         (print_insn): Likewise.
 482
 483 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 484
 485         * mips-opc.c (mips_builtin_opcodes): Correct register use
 486         annotation of "alnv.ps".
 487
 488 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 489
 490         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 491
 492 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 493
 494         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 495
 496 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 497
 498         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 499
 500 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 501
 502         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 503         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 504         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 505         exception, end_of_registers, msize, memory, bfd_mach.
 506         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 507         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 508         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 509         (get_allreg): Change to new defines.  Fallback to abort().
 510
 511 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 512
 513         * bfin-dis.c: Add whitespace/parenthesis where needed.
 514
 515 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 516
 517         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 518         than 7.
 519
 520 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 521
 522         * configure: Regenerate.
 523
 524 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 525
 526         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 527
 528 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 529
 530         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 531         dregs only when P is set, and dregs_lo otherwise.
 532
 533 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 534
 535         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 536
 537 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 538
 539         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 540
 541 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 542
 543         * bfin-dis.c (machine_registers): Delete REG_GP.
 544         (reg_names): Delete "GP".
 545         (decode_allregs): Change REG_GP to REG_LASTREG.
 546
 547 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 548
 549         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 550         M_IH, M_IU): Delete.
 551
 552 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 553
 554         * bfin-dis.c (reg_names): Add const.
 555         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 556         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 557         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 558         decode_counters, decode_allregs): Likewise.
 559
 560 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 561
 562         * i386-dis.c (OP_J): Parenthesize expression to prevent
 563         truncated addresses.
 564         (print_insn): Fix indentation off-by-one.
 565
 566 2011-02-01  Nick Clifton  <nickc@redhat.com>
 567
 568         * po/da.po: Updated Danish translation.
 569
 570 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 571
 572         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 573
 574 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 575
 576         * i386-dis.c (sIbT): New.
 577         (b_T_mode): Likewise.
 578         (dis386): Replace sIb with sIbT on "pushT".
 579         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 580         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 581
 582 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 583
 584         * i386-init.h: Regenerated.
 585         * i386-tbl.h: Regenerated
 586
 587 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 588
 589         * i386-dis.c (REG_XOP_TBM_01): New.
 590         (REG_XOP_TBM_02): New.
 591         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 592         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 593         entries, and add bextr instruction.
 594
 595         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 596         (cpu_flags): Add CpuTBM.
 597
 598         * i386-opc.h (CpuTBM) New.
 599         (i386_cpu_flags): Add bit cputbm.
 600
 601         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 602         blcs, blsfill, blsic, t1mskc, and tzmsk.
 603
 604 2011-01-12  DJ Delorie  <dj@redhat.com>
 605
 606         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 607
 608 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 609
 610         * mips-dis.c (print_insn_args): Adjust the value to print the real
 611         offset for "+c" argument.
 612
 613 2011-01-10  Nick Clifton  <nickc@redhat.com>
 614
 615         * po/da.po: Updated Danish translation.
 616
 617 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 618
 619         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 620
 621 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 622
 623         * i386-dis.c (REG_VEX_38F3): New.
 624         (PREFIX_0FBC): Likewise.
 625         (PREFIX_VEX_38F2): Likewise.
 626         (PREFIX_VEX_38F3_REG_1): Likewise.
 627         (PREFIX_VEX_38F3_REG_2): Likewise.
 628         (PREFIX_VEX_38F3_REG_3): Likewise.
 629         (PREFIX_VEX_38F7): Likewise.
 630         (VEX_LEN_38F2_P_0): Likewise.
 631         (VEX_LEN_38F3_R_1_P_0): Likewise.
 632         (VEX_LEN_38F3_R_2_P_0): Likewise.
 633         (VEX_LEN_38F3_R_3_P_0): Likewise.
 634         (VEX_LEN_38F7_P_0): Likewise.
 635         (dis386_twobyte): Use PREFIX_0FBC.
 636         (reg_table): Add REG_VEX_38F3.
 637         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 638         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 639         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 640         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 641         PREFIX_VEX_38F7.
 642         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 643         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 644         VEX_LEN_38F7_P_0.
 645
 646         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 647         (cpu_flags): Add CpuBMI.
 648
 649         * i386-opc.h (CpuBMI): New.
 650         (i386_cpu_flags): Add cpubmi.
 651
 652         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 653         * i386-init.h: Regenerated.
 654         * i386-tbl.h: Likewise.
 655
 656 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 657
 658         * i386-dis.c (VexGdq): New.
 659         (OP_VEX): Handle dq_mode.
 660
 661 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 662
 663         * i386-gen.c (process_copyright): Update copyright to 2011.
 664
 665 For older changes see ChangeLog-2010
 666 \f
 667 Local Variables:
 668 mode: change-log
 669 left-margin: 8
 670 fill-column: 74
 671 version-control: never
 672 End: