1 2018-08-01 Alan Modra <amodra@gmail.com>
3 * po/POTFILES.in: Regenerate.
5 2018-07-31 Nick Clifton <nickc@redhat.com>
7 * po/sv.po: Updated Swedish translation.
9 2018-07-31 Jan Beulich <jbeulich@suse.com>
11 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
12 * i386-init.h, i386-tbl.h: Re-generate.
14 2018-07-31 Jan Beulich <jbeulich@suse.com>
16 * i386-opc.h (ZEROING_MASKING) Rename to ...
17 (DYNAMIC_MASKING): ... this. Adjust comment.
18 * i386-opc.tbl (MaskingMorZ): Define.
19 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
20 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
21 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
22 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
23 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
24 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
25 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
26 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
27 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
29 2018-07-31 Jan Beulich <jbeulich@suse.com>
31 * i386-opc.tbl: Use element rather than vector size for AVX512*
33 * i386-tbl.h: Re-generate.
35 2018-07-31 Jan Beulich <jbeulich@suse.com>
37 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
38 (cpu_flags): Drop CpuVREX.
39 * i386-opc.h (CpuVREX): Delete.
40 (union i386_cpu_flags): Remove cpuvrex.
41 * i386-init.h, i386-tbl.h: Re-generate.
43 2018-07-30 Jim Wilson <jimw@sifive.com>
45 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
47 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
49 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
51 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
52 * Makefile.in: Regenerated.
53 * configure.ac: Add C-SKY.
54 * configure: Regenerated.
55 * csky-dis.c: New file.
56 * csky-opc.h: New file.
57 * disassemble.c (ARCH_csky): Define.
58 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
59 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
61 2018-07-27 Alan Modra <amodra@gmail.com>
63 * ppc-opc.c (insert_sprbat): Correct function parameter and
65 (extract_sprbat): Likewise, variable too.
67 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
68 Alan Modra <amodra@gmail.com>
70 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
71 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
72 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
73 support disjointed BAT.
74 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
75 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
76 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
78 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
79 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
81 * i386-gen.c (adjust_broadcast_modifier): New function.
82 (process_i386_opcode_modifier): Add an argument for operands.
83 Adjust the Broadcast value based on operands.
84 (output_i386_opcode): Pass operand_types to
85 process_i386_opcode_modifier.
86 (process_i386_opcodes): Pass NULL as operands to
87 process_i386_opcode_modifier.
88 * i386-opc.h (BYTE_BROADCAST): New.
89 (WORD_BROADCAST): Likewise.
90 (DWORD_BROADCAST): Likewise.
91 (QWORD_BROADCAST): Likewise.
92 (i386_opcode_modifier): Expand broadcast to 3 bits.
93 * i386-tbl.h: Regenerated.
95 2018-07-24 Alan Modra <amodra@gmail.com>
98 * or1k-desc.h: Regenerate.
100 2018-07-24 Jan Beulich <jbeulich@suse.com>
102 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
103 vcvtusi2ss, and vcvtusi2sd.
104 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
105 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
106 * i386-tbl.h: Re-generate.
108 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
110 * arc-opc.c (extract_w6): Fix extending the sign.
112 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
114 * arc-tbl.h (vewt): Allow it for ARC EM family.
116 2018-07-23 Alan Modra <amodra@gmail.com>
119 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
120 opcode variants for mtspr/mfspr encodings.
122 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
123 Maciej W. Rozycki <macro@mips.com>
125 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
126 loongson3a descriptors.
127 (parse_mips_ase_option): Handle -M loongson-mmi option.
128 (print_mips_disassembler_options): Document -M loongson-mmi.
129 * mips-opc.c (LMMI): New macro.
130 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
133 2018-07-19 Jan Beulich <jbeulich@suse.com>
135 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
136 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
137 IgnoreSize and [XYZ]MMword where applicable.
138 * i386-tbl.h: Re-generate.
140 2018-07-19 Jan Beulich <jbeulich@suse.com>
142 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
143 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
144 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
145 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
146 * i386-tbl.h: Re-generate.
148 2018-07-19 Jan Beulich <jbeulich@suse.com>
150 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
151 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
152 VPCLMULQDQ templates into their respective AVX512VL counterparts
153 where possible, using Disp8ShiftVL and CheckRegSize instead of
154 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
155 * i386-tbl.h: Re-generate.
157 2018-07-19 Jan Beulich <jbeulich@suse.com>
159 * i386-opc.tbl: Fold AVX512DQ templates into their respective
160 AVX512VL counterparts where possible, using Disp8ShiftVL and
161 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
162 IgnoreSize) as appropriate.
163 * i386-tbl.h: Re-generate.
165 2018-07-19 Jan Beulich <jbeulich@suse.com>
167 * i386-opc.tbl: Fold AVX512BW templates into their respective
168 AVX512VL counterparts where possible, using Disp8ShiftVL and
169 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
170 IgnoreSize) as appropriate.
171 * i386-tbl.h: Re-generate.
173 2018-07-19 Jan Beulich <jbeulich@suse.com>
175 * i386-opc.tbl: Fold AVX512CD templates into their respective
176 AVX512VL counterparts where possible, using Disp8ShiftVL and
177 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
178 IgnoreSize) as appropriate.
179 * i386-tbl.h: Re-generate.
181 2018-07-19 Jan Beulich <jbeulich@suse.com>
183 * i386-opc.h (DISP8_SHIFT_VL): New.
184 * i386-opc.tbl (Disp8ShiftVL): Define.
185 (various): Fold AVX512VL templates into their respective
186 AVX512F counterparts where possible, using Disp8ShiftVL and
187 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
188 IgnoreSize) as appropriate.
189 * i386-tbl.h: Re-generate.
191 2018-07-19 Jan Beulich <jbeulich@suse.com>
193 * Makefile.am: Change dependencies and rule for
194 $(srcdir)/i386-init.h.
195 * Makefile.in: Re-generate.
196 * i386-gen.c (process_i386_opcodes): New local variable
197 "marker". Drop opening of input file. Recognize marker and line
199 * i386-opc.tbl (OPCODE_I386_H): Define.
200 (i386-opc.h): Include it.
203 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
206 * i386-opc.h (Byte): Update comments.
215 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
217 * i386-tbl.h: Regenerated.
219 2018-07-12 Sudakshina Das <sudi.das@arm.com>
221 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
222 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
223 * aarch64-asm-2.c: Regenerate.
224 * aarch64-dis-2.c: Regenerate.
225 * aarch64-opc-2.c: Regenerate.
227 2018-07-12 Tamar Christina <tamar.christina@arm.com>
230 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
231 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
232 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
233 sqdmulh, sqrdmulh): Use Em16.
235 2018-07-11 Sudakshina Das <sudi.das@arm.com>
237 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
238 csdb together with them.
239 (thumb32_opcodes): Likewise.
241 2018-07-11 Jan Beulich <jbeulich@suse.com>
243 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
244 requiring 32-bit registers as operands 2 and 3. Improve
246 (mwait, mwaitx): Fold templates. Improve comments.
247 OPERAND_TYPE_INOUTPORTREG.
248 * i386-tbl.h: Re-generate.
250 2018-07-11 Jan Beulich <jbeulich@suse.com>
252 * i386-gen.c (operand_type_init): Remove
253 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
254 OPERAND_TYPE_INOUTPORTREG.
255 * i386-init.h: Re-generate.
257 2018-07-11 Jan Beulich <jbeulich@suse.com>
259 * i386-opc.tbl (wrssd, wrussd): Add Dword.
260 (wrssq, wrussq): Add Qword.
261 * i386-tbl.h: Re-generate.
263 2018-07-11 Jan Beulich <jbeulich@suse.com>
265 * i386-opc.h: Rename OTMax to OTNum.
266 (OTNumOfUints): Adjust calculation.
267 (OTUnused): Directly alias to OTNum.
269 2018-07-09 Maciej W. Rozycki <macro@mips.com>
271 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
273 (lea_reg_xys): Likewise.
274 (print_insn_loop_primitive): Rename `reg' local variable to
277 2018-07-06 Tamar Christina <tamar.christina@arm.com>
280 * aarch64-tbl.h (ldarh): Fix disassembly mask.
282 2018-07-06 Tamar Christina <tamar.christina@arm.com>
285 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
286 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
288 2018-07-02 Maciej W. Rozycki <macro@mips.com>
291 * mips-dis.c (mips_option_arg_t): New enumeration.
292 (mips_options): New variable.
293 (disassembler_options_mips): New function.
294 (print_mips_disassembler_options): Reimplement in terms of
295 `disassembler_options_mips'.
296 * arm-dis.c (disassembler_options_arm): Adapt to using the
297 `disasm_options_and_args_t' structure.
298 * ppc-dis.c (disassembler_options_powerpc): Likewise.
299 * s390-dis.c (disassembler_options_s390): Likewise.
301 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
303 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
305 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
306 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
307 * testsuite/ld-arm/tls-longplt.d: Likewise.
309 2018-06-29 Tamar Christina <tamar.christina@arm.com>
312 * aarch64-asm-2.c: Regenerate.
313 * aarch64-dis-2.c: Likewise.
314 * aarch64-opc-2.c: Likewise.
315 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
316 * aarch64-opc.c (operand_general_constraint_met_p,
317 aarch64_print_operand): Likewise.
318 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
319 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
321 (AARCH64_OPERANDS): Add Em2.
323 2018-06-26 Nick Clifton <nickc@redhat.com>
325 * po/uk.po: Updated Ukranian translation.
326 * po/de.po: Updated German translation.
327 * po/pt_BR.po: Updated Brazilian Portuguese translation.
329 2018-06-26 Nick Clifton <nickc@redhat.com>
331 * nfp-dis.c: Fix spelling mistake.
333 2018-06-24 Nick Clifton <nickc@redhat.com>
335 * configure: Regenerate.
336 * po/opcodes.pot: Regenerate.
338 2018-06-24 Nick Clifton <nickc@redhat.com>
342 2018-06-19 Tamar Christina <tamar.christina@arm.com>
344 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
345 * aarch64-asm-2.c: Regenerate.
346 * aarch64-dis-2.c: Likewise.
348 2018-06-21 Maciej W. Rozycki <macro@mips.com>
350 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
351 `-M ginv' option description.
353 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
356 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
359 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
361 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
362 * configure.ac: Remove AC_PREREQ.
363 * Makefile.in: Re-generate.
364 * aclocal.m4: Re-generate.
365 * configure: Re-generate.
367 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
369 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
370 mips64r6 descriptors.
371 (parse_mips_ase_option): Handle -Mginv option.
372 (print_mips_disassembler_options): Document -Mginv.
373 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
375 (mips_opcodes): Define ginvi and ginvt.
377 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
378 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
380 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
381 * mips-opc.c (CRC, CRC64): New macros.
382 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
383 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
386 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
389 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
390 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
392 2018-06-06 Alan Modra <amodra@gmail.com>
394 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
395 setjmp. Move init for some other vars later too.
397 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
399 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
400 (dis_private): Add new fields for property section tracking.
401 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
402 (xtensa_instruction_fits): New functions.
403 (fetch_data): Bump minimal fetch size to 4.
404 (print_insn_xtensa): Make struct dis_private static.
405 Load and prepare property table on section change.
406 Don't disassemble literals. Don't disassemble instructions that
407 cross property table boundaries.
409 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
411 * configure: Regenerated.
413 2018-06-01 Jan Beulich <jbeulich@suse.com>
415 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
416 * i386-tbl.h: Re-generate.
418 2018-06-01 Jan Beulich <jbeulich@suse.com>
420 * i386-opc.tbl (sldt, str): Add NoRex64.
421 * i386-tbl.h: Re-generate.
423 2018-06-01 Jan Beulich <jbeulich@suse.com>
425 * i386-opc.tbl (invpcid): Add Oword.
426 * i386-tbl.h: Re-generate.
428 2018-06-01 Alan Modra <amodra@gmail.com>
430 * sysdep.h (_bfd_error_handler): Don't declare.
431 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
432 * rl78-decode.opc: Likewise.
433 * msp430-decode.c: Regenerate.
434 * rl78-decode.c: Regenerate.
436 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
438 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
439 * i386-init.h : Regenerated.
441 2018-05-25 Alan Modra <amodra@gmail.com>
443 * Makefile.in: Regenerate.
444 * po/POTFILES.in: Regenerate.
446 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
448 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
449 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
450 (insert_bab, extract_bab, insert_btab, extract_btab,
451 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
452 (BAT, BBA VBA RBS XB6S): Delete macros.
453 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
454 (BB, BD, RBX, XC6): Update for new macros.
455 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
456 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
457 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
458 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
460 2018-05-18 John Darrington <john@darrington.wattle.id.au>
462 * Makefile.am: Add support for s12z architecture.
463 * configure.ac: Likewise.
464 * disassemble.c: Likewise.
465 * disassemble.h: Likewise.
466 * Makefile.in: Regenerate.
467 * configure: Regenerate.
468 * s12z-dis.c: New file.
471 2018-05-18 Alan Modra <amodra@gmail.com>
473 * nfp-dis.c: Don't #include libbfd.h.
474 (init_nfp3200_priv): Use bfd_get_section_contents.
475 (nit_nfp6000_mecsr_sec): Likewise.
477 2018-05-17 Nick Clifton <nickc@redhat.com>
479 * po/zh_CN.po: Updated simplified Chinese translation.
481 2018-05-16 Tamar Christina <tamar.christina@arm.com>
484 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
485 * aarch64-dis-2.c: Regenerate.
487 2018-05-15 Tamar Christina <tamar.christina@arm.com>
490 * aarch64-asm.c (opintl.h): Include.
491 (aarch64_ins_sysreg): Enforce read/write constraints.
492 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
493 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
494 (F_REG_READ, F_REG_WRITE): New.
495 * aarch64-opc.c (aarch64_print_operand): Generate notes for
497 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
498 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
499 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
500 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
501 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
502 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
503 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
504 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
505 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
506 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
507 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
508 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
509 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
510 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
511 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
512 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
513 msr (F_SYS_WRITE), mrs (F_SYS_READ).
515 2018-05-15 Tamar Christina <tamar.christina@arm.com>
518 * aarch64-dis.c (no_notes: New.
519 (parse_aarch64_dis_option): Support notes.
520 (aarch64_decode_insn, print_operands): Likewise.
521 (print_aarch64_disassembler_options): Document notes.
522 * aarch64-opc.c (aarch64_print_operand): Support notes.
524 2018-05-15 Tamar Christina <tamar.christina@arm.com>
527 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
528 and take error struct.
529 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
530 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
531 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
532 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
533 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
534 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
535 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
536 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
537 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
538 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
539 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
540 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
541 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
542 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
543 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
544 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
545 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
546 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
547 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
548 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
549 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
550 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
551 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
552 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
553 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
554 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
555 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
556 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
557 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
558 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
559 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
560 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
561 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
562 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
563 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
564 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
565 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
566 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
567 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
568 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
569 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
570 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
571 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
572 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
573 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
574 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
575 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
576 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
577 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
578 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
579 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
580 (determine_disassembling_preference, aarch64_decode_insn,
581 print_insn_aarch64_word, print_insn_data): Take errors struct.
582 (print_insn_aarch64): Use errors.
583 * aarch64-asm-2.c: Regenerate.
584 * aarch64-dis-2.c: Regenerate.
585 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
586 boolean in aarch64_insert_operan.
587 (print_operand_extractor): Likewise.
588 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
590 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
592 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
594 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
596 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
598 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
600 * cr16-opc.c (cr16_instruction): Comment typo fix.
601 * hppa-dis.c (print_insn_hppa): Likewise.
603 2018-05-08 Jim Wilson <jimw@sifive.com>
605 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
606 (match_c_slli64, match_srxi_as_c_srxi): New.
607 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
608 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
609 <c.slli, c.srli, c.srai>: Use match_s_slli.
610 <c.slli64, c.srli64, c.srai64>: New.
612 2018-05-08 Alan Modra <amodra@gmail.com>
614 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
615 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
616 partition opcode space for index lookup.
618 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
620 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
621 <insn_length>: ...with this. Update usage.
622 Remove duplicate call to *info->memory_error_func.
624 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
625 H.J. Lu <hongjiu.lu@intel.com>
627 * i386-dis.c (Gva): New.
628 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
629 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
630 (prefix_table): New instructions (see prefix above).
631 (mod_table): New instructions (see prefix above).
632 (OP_G): Handle va_mode.
633 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
635 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
636 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
637 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
638 * i386-opc.tbl: Add movidir{i,64b}.
639 * i386-init.h: Regenerated.
640 * i386-tbl.h: Likewise.
642 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
644 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
646 * i386-opc.h (AddrPrefixOp0): Renamed to ...
647 (AddrPrefixOpReg): This.
648 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
649 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
651 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
653 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
654 (vle_num_opcodes): Likewise.
655 (spe2_num_opcodes): Likewise.
656 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
658 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
659 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
662 2018-05-01 Tamar Christina <tamar.christina@arm.com>
664 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
666 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
668 Makefile.am: Added nfp-dis.c.
669 configure.ac: Added bfd_nfp_arch.
670 disassemble.h: Added print_insn_nfp prototype.
671 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
672 nfp-dis.c: New, for NFP support.
673 po/POTFILES.in: Added nfp-dis.c to the list.
674 Makefile.in: Regenerate.
675 configure: Regenerate.
677 2018-04-26 Jan Beulich <jbeulich@suse.com>
679 * i386-opc.tbl: Fold various non-memory operand AVX512VL
680 templates into their base ones.
681 * i386-tlb.h: Re-generate.
683 2018-04-26 Jan Beulich <jbeulich@suse.com>
685 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
686 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
687 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
688 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
689 * i386-init.h: Re-generate.
691 2018-04-26 Jan Beulich <jbeulich@suse.com>
693 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
694 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
695 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
696 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
698 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
700 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
702 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
703 cpuregzmm, and cpuregmask.
704 * i386-init.h: Re-generate.
705 * i386-tbl.h: Re-generate.
707 2018-04-26 Jan Beulich <jbeulich@suse.com>
709 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
710 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
711 * i386-init.h: Re-generate.
713 2018-04-26 Jan Beulich <jbeulich@suse.com>
715 * i386-gen.c (VexImmExt): Delete.
716 * i386-opc.h (VexImmExt, veximmext): Delete.
717 * i386-opc.tbl: Drop all VexImmExt uses.
718 * i386-tlb.h: Re-generate.
720 2018-04-25 Jan Beulich <jbeulich@suse.com>
722 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
724 * i386-tlb.h: Re-generate.
726 2018-04-25 Tamar Christina <tamar.christina@arm.com>
728 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
730 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
732 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
734 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
735 (cpu_flags): Add CpuCLDEMOTE.
736 * i386-init.h: Regenerate.
737 * i386-opc.h (enum): Add CpuCLDEMOTE,
738 (i386_cpu_flags): Add cpucldemote.
739 * i386-opc.tbl: Add cldemote.
740 * i386-tbl.h: Regenerate.
742 2018-04-16 Alan Modra <amodra@gmail.com>
744 * Makefile.am: Remove sh5 and sh64 support.
745 * configure.ac: Likewise.
746 * disassemble.c: Likewise.
747 * disassemble.h: Likewise.
748 * sh-dis.c: Likewise.
749 * sh64-dis.c: Delete.
750 * sh64-opc.c: Delete.
751 * sh64-opc.h: Delete.
752 * Makefile.in: Regenerate.
753 * configure: Regenerate.
754 * po/POTFILES.in: Regenerate.
756 2018-04-16 Alan Modra <amodra@gmail.com>
758 * Makefile.am: Remove w65 support.
759 * configure.ac: Likewise.
760 * disassemble.c: Likewise.
761 * disassemble.h: Likewise.
764 * Makefile.in: Regenerate.
765 * configure: Regenerate.
766 * po/POTFILES.in: Regenerate.
768 2018-04-16 Alan Modra <amodra@gmail.com>
770 * configure.ac: Remove we32k support.
771 * configure: Regenerate.
773 2018-04-16 Alan Modra <amodra@gmail.com>
775 * Makefile.am: Remove m88k support.
776 * configure.ac: Likewise.
777 * disassemble.c: Likewise.
778 * disassemble.h: Likewise.
779 * m88k-dis.c: Delete.
780 * Makefile.in: Regenerate.
781 * configure: Regenerate.
782 * po/POTFILES.in: Regenerate.
784 2018-04-16 Alan Modra <amodra@gmail.com>
786 * Makefile.am: Remove i370 support.
787 * configure.ac: Likewise.
788 * disassemble.c: Likewise.
789 * disassemble.h: Likewise.
790 * i370-dis.c: Delete.
791 * i370-opc.c: Delete.
792 * Makefile.in: Regenerate.
793 * configure: Regenerate.
794 * po/POTFILES.in: Regenerate.
796 2018-04-16 Alan Modra <amodra@gmail.com>
798 * Makefile.am: Remove h8500 support.
799 * configure.ac: Likewise.
800 * disassemble.c: Likewise.
801 * disassemble.h: Likewise.
802 * h8500-dis.c: Delete.
803 * h8500-opc.h: Delete.
804 * Makefile.in: Regenerate.
805 * configure: Regenerate.
806 * po/POTFILES.in: Regenerate.
808 2018-04-16 Alan Modra <amodra@gmail.com>
810 * configure.ac: Remove tahoe support.
811 * configure: Regenerate.
813 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
815 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
817 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
819 * i386-tbl.h: Regenerated.
821 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
823 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
824 PREFIX_MOD_1_0FAE_REG_6.
826 (OP_E_register): Use va_mode.
827 * i386-dis-evex.h (prefix_table):
828 New instructions (see prefixes above).
829 * i386-gen.c (cpu_flag_init): Add WAITPKG.
830 (cpu_flags): Likewise.
831 * i386-opc.h (enum): Likewise.
832 (i386_cpu_flags): Likewise.
833 * i386-opc.tbl: Add umonitor, umwait, tpause.
834 * i386-init.h: Regenerate.
835 * i386-tbl.h: Likewise.
837 2018-04-11 Alan Modra <amodra@gmail.com>
839 * opcodes/i860-dis.c: Delete.
840 * opcodes/i960-dis.c: Delete.
841 * Makefile.am: Remove i860 and i960 support.
842 * configure.ac: Likewise.
843 * disassemble.c: Likewise.
844 * disassemble.h: Likewise.
845 * Makefile.in: Regenerate.
846 * configure: Regenerate.
847 * po/POTFILES.in: Regenerate.
849 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
852 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
854 (print_insn): Clear vex instead of vex.evex.
856 2018-04-04 Nick Clifton <nickc@redhat.com>
858 * po/es.po: Updated Spanish translation.
860 2018-03-28 Jan Beulich <jbeulich@suse.com>
862 * i386-gen.c (opcode_modifiers): Delete VecESize.
863 * i386-opc.h (VecESize): Delete.
864 (struct i386_opcode_modifier): Delete vecesize.
865 * i386-opc.tbl: Drop VecESize.
866 * i386-tlb.h: Re-generate.
868 2018-03-28 Jan Beulich <jbeulich@suse.com>
870 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
871 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
872 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
873 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
874 * i386-tlb.h: Re-generate.
876 2018-03-28 Jan Beulich <jbeulich@suse.com>
878 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
880 * i386-tlb.h: Re-generate.
882 2018-03-28 Jan Beulich <jbeulich@suse.com>
884 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
885 (vex_len_table): Drop Y for vcvt*2si.
886 (putop): Replace plain 'Y' handling by abort().
888 2018-03-28 Nick Clifton <nickc@redhat.com>
891 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
892 instructions with only a base address register.
893 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
894 handle AARHC64_OPND_SVE_ADDR_R.
895 (aarch64_print_operand): Likewise.
896 * aarch64-asm-2.c: Regenerate.
897 * aarch64_dis-2.c: Regenerate.
898 * aarch64-opc-2.c: Regenerate.
900 2018-03-22 Jan Beulich <jbeulich@suse.com>
902 * i386-opc.tbl: Drop VecESize from register only insn forms and
903 memory forms not allowing broadcast.
904 * i386-tlb.h: Re-generate.
906 2018-03-22 Jan Beulich <jbeulich@suse.com>
908 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
909 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
910 sha256*): Drop Disp<N>.
912 2018-03-22 Jan Beulich <jbeulich@suse.com>
914 * i386-dis.c (EbndS, bnd_swap_mode): New.
915 (prefix_table): Use EbndS.
916 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
917 * i386-opc.tbl (bndmov): Move misplaced Load.
918 * i386-tlb.h: Re-generate.
920 2018-03-22 Jan Beulich <jbeulich@suse.com>
922 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
923 templates allowing memory operands and folded ones for register
925 * i386-tlb.h: Re-generate.
927 2018-03-22 Jan Beulich <jbeulich@suse.com>
929 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
930 256-bit templates. Drop redundant leftover Disp<N>.
931 * i386-tlb.h: Re-generate.
933 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
935 * riscv-opc.c (riscv_insn_types): New.
937 2018-03-13 Nick Clifton <nickc@redhat.com>
939 * po/pt_BR.po: Updated Brazilian Portuguese translation.
941 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
943 * i386-opc.tbl: Add Optimize to clr.
944 * i386-tbl.h: Regenerated.
946 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
948 * i386-gen.c (opcode_modifiers): Remove OldGcc.
949 * i386-opc.h (OldGcc): Removed.
950 (i386_opcode_modifier): Remove oldgcc.
951 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
952 instructions for old (<= 2.8.1) versions of gcc.
953 * i386-tbl.h: Regenerated.
955 2018-03-08 Jan Beulich <jbeulich@suse.com>
957 * i386-opc.h (EVEXDYN): New.
958 * i386-opc.tbl: Fold various AVX512VL templates.
959 * i386-tlb.h: Re-generate.
961 2018-03-08 Jan Beulich <jbeulich@suse.com>
963 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
964 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
965 vpexpandd, vpexpandq): Fold AFX512VF templates.
966 * i386-tlb.h: Re-generate.
968 2018-03-08 Jan Beulich <jbeulich@suse.com>
970 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
971 Fold 128- and 256-bit VEX-encoded templates.
972 * i386-tlb.h: Re-generate.
974 2018-03-08 Jan Beulich <jbeulich@suse.com>
976 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
977 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
978 vpexpandd, vpexpandq): Fold AVX512F templates.
979 * i386-tlb.h: Re-generate.
981 2018-03-08 Jan Beulich <jbeulich@suse.com>
983 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
984 64-bit templates. Drop Disp<N>.
985 * i386-tlb.h: Re-generate.
987 2018-03-08 Jan Beulich <jbeulich@suse.com>
989 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
990 and 256-bit templates.
991 * i386-tlb.h: Re-generate.
993 2018-03-08 Jan Beulich <jbeulich@suse.com>
995 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
996 * i386-tlb.h: Re-generate.
998 2018-03-08 Jan Beulich <jbeulich@suse.com>
1000 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1002 * i386-tlb.h: Re-generate.
1004 2018-03-08 Jan Beulich <jbeulich@suse.com>
1006 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1007 * i386-tlb.h: Re-generate.
1009 2018-03-08 Jan Beulich <jbeulich@suse.com>
1011 * i386-gen.c (opcode_modifiers): Delete FloatD.
1012 * i386-opc.h (FloatD): Delete.
1013 (struct i386_opcode_modifier): Delete floatd.
1014 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1016 * i386-tlb.h: Re-generate.
1018 2018-03-08 Jan Beulich <jbeulich@suse.com>
1020 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1022 2018-03-08 Jan Beulich <jbeulich@suse.com>
1024 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1025 * i386-tlb.h: Re-generate.
1027 2018-03-08 Jan Beulich <jbeulich@suse.com>
1029 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1031 * i386-tlb.h: Re-generate.
1033 2018-03-07 Alan Modra <amodra@gmail.com>
1035 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1037 * disassemble.h (print_insn_rs6000): Delete.
1038 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1039 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1040 (print_insn_rs6000): Delete.
1042 2018-03-03 Alan Modra <amodra@gmail.com>
1044 * sysdep.h (opcodes_error_handler): Define.
1045 (_bfd_error_handler): Declare.
1046 * Makefile.am: Remove stray #.
1047 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1049 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1050 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1051 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1052 opcodes_error_handler to print errors. Standardize error messages.
1053 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1054 and include opintl.h.
1055 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1056 * i386-gen.c: Standardize error messages.
1057 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1058 * Makefile.in: Regenerate.
1059 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1060 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1061 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1062 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1063 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1064 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1065 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1066 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1067 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1068 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1069 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1070 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1071 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1073 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1075 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1076 vpsub[bwdq] instructions.
1077 * i386-tbl.h: Regenerated.
1079 2018-03-01 Alan Modra <amodra@gmail.com>
1081 * configure.ac (ALL_LINGUAS): Sort.
1082 * configure: Regenerate.
1084 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1086 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1087 macro by assignements.
1089 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1092 * i386-gen.c (opcode_modifiers): Add Optimize.
1093 * i386-opc.h (Optimize): New enum.
1094 (i386_opcode_modifier): Add optimize.
1095 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1096 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1097 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1098 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1099 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1101 * i386-tbl.h: Regenerated.
1103 2018-02-26 Alan Modra <amodra@gmail.com>
1105 * crx-dis.c (getregliststring): Allocate a large enough buffer
1106 to silence false positive gcc8 warning.
1108 2018-02-22 Shea Levy <shea@shealevy.com>
1110 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1112 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1114 * i386-opc.tbl: Add {rex},
1115 * i386-tbl.h: Regenerated.
1117 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1119 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1120 (mips16_opcodes): Replace `M' with `m' for "restore".
1122 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1124 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1126 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1128 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1129 variable to `function_index'.
1131 2018-02-13 Nick Clifton <nickc@redhat.com>
1134 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1135 about truncation of printing.
1137 2018-02-12 Henry Wong <henry@stuffedcow.net>
1139 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1141 2018-02-05 Nick Clifton <nickc@redhat.com>
1143 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1145 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1147 * i386-dis.c (enum): Add pconfig.
1148 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1149 (cpu_flags): Add CpuPCONFIG.
1150 * i386-opc.h (enum): Add CpuPCONFIG.
1151 (i386_cpu_flags): Add cpupconfig.
1152 * i386-opc.tbl: Add PCONFIG instruction.
1153 * i386-init.h: Regenerate.
1154 * i386-tbl.h: Likewise.
1156 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1158 * i386-dis.c (enum): Add PREFIX_0F09.
1159 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1160 (cpu_flags): Add CpuWBNOINVD.
1161 * i386-opc.h (enum): Add CpuWBNOINVD.
1162 (i386_cpu_flags): Add cpuwbnoinvd.
1163 * i386-opc.tbl: Add WBNOINVD instruction.
1164 * i386-init.h: Regenerate.
1165 * i386-tbl.h: Likewise.
1167 2018-01-17 Jim Wilson <jimw@sifive.com>
1169 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1171 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1173 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1174 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1175 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1176 (cpu_flags): Add CpuIBT, CpuSHSTK.
1177 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1178 (i386_cpu_flags): Add cpuibt, cpushstk.
1179 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1180 * i386-init.h: Regenerate.
1181 * i386-tbl.h: Likewise.
1183 2018-01-16 Nick Clifton <nickc@redhat.com>
1185 * po/pt_BR.po: Updated Brazilian Portugese translation.
1186 * po/de.po: Updated German translation.
1188 2018-01-15 Jim Wilson <jimw@sifive.com>
1190 * riscv-opc.c (match_c_nop): New.
1191 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1193 2018-01-15 Nick Clifton <nickc@redhat.com>
1195 * po/uk.po: Updated Ukranian translation.
1197 2018-01-13 Nick Clifton <nickc@redhat.com>
1199 * po/opcodes.pot: Regenerated.
1201 2018-01-13 Nick Clifton <nickc@redhat.com>
1203 * configure: Regenerate.
1205 2018-01-13 Nick Clifton <nickc@redhat.com>
1207 2.30 branch created.
1209 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1211 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1212 * i386-tbl.h: Regenerate.
1214 2018-01-10 Jan Beulich <jbeulich@suse.com>
1216 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1217 * i386-tbl.h: Re-generate.
1219 2018-01-10 Jan Beulich <jbeulich@suse.com>
1221 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1222 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1223 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1224 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1225 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1226 Disp8MemShift of AVX512VL forms.
1227 * i386-tbl.h: Re-generate.
1229 2018-01-09 Jim Wilson <jimw@sifive.com>
1231 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1232 then the hi_addr value is zero.
1234 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1236 * arm-dis.c (arm_opcodes): Add csdb.
1237 (thumb32_opcodes): Add csdb.
1239 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1241 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1242 * aarch64-asm-2.c: Regenerate.
1243 * aarch64-dis-2.c: Regenerate.
1244 * aarch64-opc-2.c: Regenerate.
1246 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1249 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1250 Remove AVX512 vmovd with 64-bit operands.
1251 * i386-tbl.h: Regenerated.
1253 2018-01-05 Jim Wilson <jimw@sifive.com>
1255 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1258 2018-01-03 Alan Modra <amodra@gmail.com>
1260 Update year range in copyright notice of all files.
1262 2018-01-02 Jan Beulich <jbeulich@suse.com>
1264 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1265 and OPERAND_TYPE_REGZMM entries.
1267 For older changes see ChangeLog-2017
1269 Copyright (C) 2018 Free Software Foundation, Inc.
1271 Copying and distribution of this file, with or without modification,
1272 are permitted in any medium without royalty provided the copyright
1273 notice and this notice are preserved.
1279 version-control: never