opcodes/ChangeLog

   1 2004-07-11  Andreas Schwab  <schwab@suse.de>
   2
   3         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
   4
   5 2004-07-09  Andreas Schwab  <schwab@suse.de>
   6
   7         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
   8
   9 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
  10
  11         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
  12         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
  13         (crx-dis.lo): New target.
  14         (crx-opc.lo): Likewise.
  15         * Makefile.in: Regenerate.
  16         * configure.in: Handle bfd_crx_arch.
  17         * configure: Regenerate.
  18         * crx-dis.c: New file.
  19         * crx-opc.c: New file.
  20         * disassemble.c (ARCH_crx): Define.
  21         (disassembler): Handle ARCH_crx.
  22
  23 2004-06-29  James E Wilson  <wilson@specifixinc.com>
  24
  25         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
  26         * ia64-asmtab.c: Regnerate.
  27
  28 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
  29
  30         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
  31         (extract_fxm): Don't test dialect.
  32         (XFXFXM_MASK): Include the power4 bit.
  33         (XFXM): Add p4 param.
  34         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
  35
  36 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
  37
  38         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
  39         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
  40
  41 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
  42
  43         * ppc-opc.c (BH, XLBH_MASK): Define.
  44         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
  45
  46 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
  47
  48         * i386-dis.c (x_mode): Comment.
  49         (two_source_ops): File scope.
  50         (float_mem): Correct fisttpll and fistpll.
  51         (float_mem_mode): New table.
  52         (dofloat): Use it.
  53         (OP_E): Correct intel mode PTR output.
  54         (ptr_reg): Use open_char and close_char.
  55         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
  56         operands.  Set two_source_ops.
  57
  58 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
  59
  60         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
  61         instead of _raw_size.
  62
  63 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
  64
  65         * ia64-gen.c (in_iclass): Handle more postinc st
  66         and ld variants.
  67         * ia64-asmtab.c: Rebuilt.
  68
  69 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
  70
  71         * s390-opc.txt: Correct architecture mask for some opcodes.
  72         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
  73         in the esa mode as well.
  74
  75 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
  76
  77         * sh-dis.c (target_arch): Make unsigned.
  78         (print_insn_sh): Replace (most of) switch with a call to
  79         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
  80         * sh-opc.h: Redefine architecture flags values.
  81         Add sh3-nommu architecture.
  82         Reorganise <arch>_up macros so they make more visual sense.
  83         (SH_MERGE_ARCH_SET): Define new macro.
  84         (SH_VALID_BASE_ARCH_SET): Likewise.
  85         (SH_VALID_MMU_ARCH_SET): Likewise.
  86         (SH_VALID_CO_ARCH_SET): Likewise.
  87         (SH_VALID_ARCH_SET): Likewise.
  88         (SH_MERGE_ARCH_SET_VALID): Likewise.
  89         (SH_ARCH_SET_HAS_FPU): Likewise.
  90         (SH_ARCH_SET_HAS_DSP): Likewise.
  91         (SH_ARCH_UNKNOWN_ARCH): Likewise.
  92         (sh_get_arch_from_bfd_mach): Add prototype.
  93         (sh_get_arch_up_from_bfd_mach): Likewise.
  94         (sh_get_bfd_mach_from_arch_set): Likewise.
  95         (sh_merge_bfd_arc): Likewise.
  96
  97 2004-05-24  Peter Barada  <peter@the-baradas.com>
  98
  99         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 100         into new match_insn_m68k function.  Loop over canidate
 101         matches and select first that completely matches.
 102         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 103         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 104         to verify addressing for MAC/EMAC.
 105         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 106         reigster halves since 'fpu' and 'spl' look misleading.
 107         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 108         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 109         first, tighten up match masks.
 110         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 111         'size' from special case code in print_insn_m68k to
 112         determine decode size of insns.
 113
 114 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 115
 116         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 117         well as when -mpower4.
 118
 119 2004-05-13  Nick Clifton  <nickc@redhat.com>
 120
 121         * po/fr.po: Updated French translation.
 122
 123 2004-05-05  Peter Barada  <peter@the-baradas.com>
 124
 125         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 126         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 127         * m68k-op.c: Switch from ColdFire chips to core variants.
 128
 129 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 130
 131         PR 147.
 132         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 133
 134 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 135
 136         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 137         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 138
 139 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 140
 141         * sh-dis.c (print_insn_sh): Print the value in constant pool
 142         as a symbol if it looks like a symbol.
 143
 144 2004-04-22  Peter Barada <peter@the-baradas.com>
 145
 146         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 147         appropriate ColdFire architectures.
 148         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 149         mask addressing.
 150         Add EMAC instructions, fix MAC instructions. Remove
 151         macmw/macml/msacmw/msacml instructions since mask addressing now
 152         supported.
 153
 154 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 155
 156         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 157         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 158         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 159         macro.  Adjust all users.
 160
 161 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 162
 163         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 164         separately.
 165
 166 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 167
 168         * m32r-asm.c: Regenerate.
 169
 170 2004-03-29  Stan Shebs  <shebs@apple.com>
 171
 172         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 173         used.
 174
 175 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 176
 177         * aclocal.m4: Regenerate.
 178         * config.in: Regenerate.
 179         * configure: Regenerate.
 180         * po/POTFILES.in: Regenerate.
 181         * po/opcodes.pot: Regenerate.
 182
 183 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 184
 185         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 186         PPC_OPERANDS_GPR_0.
 187         * ppc-opc.c (RA0): Define.
 188         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 189         (RAOPT): Rename from RAO.  Update all uses.
 190         (powerpc_opcodes): Use RA0 as appropriate.
 191
 192 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 193
 194         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 195
 196 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 197
 198         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 199
 200 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 201
 202         * i386-dis.c (GRPPLOCK): Delete.
 203         (grps): Delete GRPPLOCK entry.
 204
 205 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 206
 207         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 208         (M, Mp): Use OP_M.
 209         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 210         (GRPPADLCK): Define.
 211         (dis386): Use NOP_Fixup on "nop".
 212         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 213         (twobyte_has_modrm): Set for 0xa7.
 214         (padlock_table): Delete.  Move to..
 215         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 216         and clflush.
 217         (print_insn): Revert PADLOCK_SPECIAL code.
 218         (OP_E): Delete sfence, lfence, mfence checks.
 219
 220 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 221
 222         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 223         (INVLPG_Fixup): New function.
 224         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 225
 226 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 227
 228         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 229         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 230         (padlock_table): New struct with PadLock instructions.
 231         (print_insn): Handle PADLOCK_SPECIAL.
 232
 233 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 234
 235         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 236         (OP_E): Twiddle clflush to sfence here.
 237
 238 2004-03-08  Nick Clifton  <nickc@redhat.com>
 239
 240         * po/de.po: Updated German translation.
 241
 242 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 243
 244         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 245         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 246         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 247         accordingly.
 248
 249 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 250
 251         * frv-asm.c: Regenerate.
 252         * frv-desc.c: Regenerate.
 253         * frv-desc.h: Regenerate.
 254         * frv-dis.c: Regenerate.
 255         * frv-ibld.c: Regenerate.
 256         * frv-opc.c: Regenerate.
 257         * frv-opc.h: Regenerate.
 258
 259 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 260
 261         * frv-desc.c, frv-opc.c: Regenerate.
 262
 263 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 264
 265         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 266
 267 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 268
 269         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 270         Also correct mistake in the comment.
 271
 272 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 273
 274         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 275         ensure that double registers have even numbers.
 276         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 277         that reserved instruction 0xfffd does not decode the same
 278         as 0xfdfd (ftrv).
 279         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 280         REG_N refers to a double register.
 281         Add REG_N_B01 nibble type and use it instead of REG_NM
 282         in ftrv.
 283         Adjust the bit patterns in a few comments.
 284
 285 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 286
 287         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 288
 289 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 290
 291         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 292
 293 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 294
 295         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 296
 297 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 298
 299         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 300         mtivor32, mtivor33, mtivor34.
 301
 302 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 303
 304         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 305
 306 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 307
 308         * arm-opc.h Maverick accumulator register opcode fixes.
 309
 310 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 311
 312         * m32r-dis.c: Regenerate.
 313
 314 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 315
 316         * sh-opc.h (sh_table): "fsrra", not "fssra".
 317
 318 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 319
 320         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 321         contraints.
 322
 323 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 324
 325         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 326
 327 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 328
 329         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 330         1.  Don't print scale factor on AT&T mode when index missing.
 331
 332 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 333
 334         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 335         when loaded into XR registers.
 336
 337 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 338
 339         * frv-desc.h: Regenerate.
 340         * frv-desc.c: Regenerate.
 341         * frv-opc.c: Regenerate.
 342
 343 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 344
 345         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 346
 347 2004-01-09  Paul Brook  <paul@codesourcery.com>
 348
 349         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 350         specific opcodes.
 351
 352 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 353
 354         * Makefile.am (libopcodes_la_DEPENDENCIES)
 355         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 356         comment about the problem.
 357         * Makefile.in: Regenerate.
 358
 359 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 360
 361         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 362         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 363         cut&paste errors in shifting/truncating numerical operands.
 364         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 365         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 366         (parse_uslo16): Likewise.
 367         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 368         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 369         (parse_s12): Likewise.
 370         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 371         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 372         (parse_uslo16): Likewise.
 373         (parse_uhi16): Parse gothi and gotfuncdeschi.
 374         (parse_d12): Parse got12 and gotfuncdesc12.
 375         (parse_s12): Likewise.
 376
 377 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 378
 379         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 380         instruction which looks similar to an 'rla' instruction.
 381
 382 For older changes see ChangeLog-0203
 383 \f
 384 Local Variables:
 385 mode: change-log
 386 left-margin: 8
 387 fill-column: 74
 388 version-control: never
 389 End: