1 2016-07-01 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
4 (movzb): Adjust to cover all permitted suffixes.
6 * i386-tbl.h: Re-generate.
8 2016-07-01 Jan Beulich <jbeulich@suse.com>
10 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
11 (lgdt): Remove Tbyte from non-64-bit variant.
12 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
13 xsaves64, xsavec64): Remove Disp16.
14 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
15 Remove Disp32S from non-64-bit variants. Remove Disp16 from
17 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
18 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
19 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
21 * i386-tbl.h: Re-generate.
23 2016-07-01 Jan Beulich <jbeulich@suse.com>
25 * i386-opc.tbl (xlat): Remove RepPrefixOk.
26 * i386-tbl.h: Re-generate.
28 2016-06-30 Yao Qi <yao.qi@linaro.org>
30 * arm-dis.c (print_insn): Fix typo in comment.
32 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
34 * aarch64-opc.c (operand_general_constraint_met_p): Check the
35 range of ldst_elemlist operands.
36 (print_register_list): Use PRIi64 to print the index.
37 (aarch64_print_operand): Likewise.
39 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
41 * mcore-opc.h: Remove sentinal.
42 * mcore-dis.c (print_insn_mcore): Adjust.
44 2016-06-23 Graham Markall <graham.markall@embecosm.com>
46 * arc-opc.c: Correct description of availability of NPS400
49 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
51 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
52 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
53 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
55 <setb>: Change to a VX form instruction.
56 (insert_sh6): Add support for rldixor.
57 (extract_sh6): Likewise.
59 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
61 * arc-ext.h: Wrap in extern C.
63 2016-06-21 Graham Markall <graham.markall@embecosm.com>
65 * arc-dis.c (arc_insn_length): Add comment on instruction length.
66 Use same method for determining instruction length on ARC700 and
68 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
69 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
70 with the NPS400 subclass.
71 * arc-opc.c: Likewise.
73 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
75 * sparc-opc.c (rdasr): New macro.
81 (sparc_opcodes): Use the macros above to fix and expand the
82 definition of read/write instructions from/to
83 asr/privileged/hyperprivileged instructions.
84 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
85 %hva_mask_nz. Prefer softint_set and softint_clear over
86 set_softint and clear_softint.
87 (print_insn_sparc): Support %ver in Rd.
89 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
91 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
92 architecture according to the hardware capabilities they require.
94 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
96 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
97 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
98 bfd_mach_sparc_v9{c,d,e,v,m}.
99 * sparc-opc.c (MASK_V9C): Define.
100 (MASK_V9D): Likewise.
101 (MASK_V9E): Likewise.
102 (MASK_V9V): Likewise.
103 (MASK_V9M): Likewise.
104 (v6): Add MASK_V9{C,D,E,V,M}.
105 (v6notlet): Likewise.
109 (v9andleon): Likewise.
117 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
119 2016-06-15 Nick Clifton <nickc@redhat.com>
121 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
122 constants to match expected behaviour.
123 (nds32_parse_opcode): Likewise. Also for whitespace.
125 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
127 * arc-opc.c (extract_rhv1): Extract value from insn.
129 2016-06-14 Graham Markall <graham.markall@embecosm.com>
131 * arc-nps400-tbl.h: Add ldbit instruction.
132 * arc-opc.c: Add flag classes required for ldbit.
134 2016-06-14 Graham Markall <graham.markall@embecosm.com>
136 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
137 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
138 support the above instructions.
140 2016-06-14 Graham Markall <graham.markall@embecosm.com>
142 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
143 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
144 csma, cbba, zncv, and hofs.
145 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
146 support the above instructions.
148 2016-06-06 Graham Markall <graham.markall@embecosm.com>
150 * arc-nps400-tbl.h: Add andab and orab instructions.
152 2016-06-06 Graham Markall <graham.markall@embecosm.com>
154 * arc-nps400-tbl.h: Add addl-like instructions.
156 2016-06-06 Graham Markall <graham.markall@embecosm.com>
158 * arc-nps400-tbl.h: Add mxb and imxb instructions.
160 2016-06-06 Graham Markall <graham.markall@embecosm.com>
162 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
165 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
167 * s390-dis.c (option_use_insn_len_bits_p): New file scope
169 (init_disasm): Handle new command line option "insnlength".
170 (print_s390_disassembler_options): Mention new option in help
172 (print_insn_s390): Use the encoded insn length when dumping
173 unknown instructions.
175 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
177 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
178 to the address and set as symbol address for LDS/ STS immediate operands.
180 2016-06-07 Alan Modra <amodra@gmail.com>
182 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
183 cpu for "vle" to e500.
184 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
185 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
186 (PPCNONE): Delete, substitute throughout.
187 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
188 except for major opcode 4 and 31.
189 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
191 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
193 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
194 ARM_EXT_RAS in relevant entries.
196 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
199 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
202 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
205 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
207 Add comments for '&'.
208 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
210 (intel_operand_size): Handle indir_v_mode.
211 (OP_E_register): Likewise.
212 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
213 64-bit indirect call/jmp for AMD64.
214 * i386-tbl.h: Regenerated
216 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
218 * arc-dis.c (struct arc_operand_iterator): New structure.
219 (find_format_from_table): All the old content from find_format,
220 with some minor adjustments, and parameter renaming.
221 (find_format_long_instructions): New function.
222 (find_format): Rewritten.
223 (arc_insn_length): Add LSB parameter.
224 (extract_operand_value): New function.
225 (operand_iterator_next): New function.
226 (print_insn_arc): Use new functions to find opcode, and iterator
228 * arc-opc.c (insert_nps_3bit_dst_short): New function.
229 (extract_nps_3bit_dst_short): New function.
230 (insert_nps_3bit_src2_short): New function.
231 (extract_nps_3bit_src2_short): New function.
232 (insert_nps_bitop1_size): New function.
233 (extract_nps_bitop1_size): New function.
234 (insert_nps_bitop2_size): New function.
235 (extract_nps_bitop2_size): New function.
236 (insert_nps_bitop_mod4_msb): New function.
237 (extract_nps_bitop_mod4_msb): New function.
238 (insert_nps_bitop_mod4_lsb): New function.
239 (extract_nps_bitop_mod4_lsb): New function.
240 (insert_nps_bitop_dst_pos3_pos4): New function.
241 (extract_nps_bitop_dst_pos3_pos4): New function.
242 (insert_nps_bitop_ins_ext): New function.
243 (extract_nps_bitop_ins_ext): New function.
244 (arc_operands): Add new operands.
245 (arc_long_opcodes): New global array.
246 (arc_num_long_opcodes): New global.
247 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
249 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
251 * nds32-asm.h: Add extern "C".
252 * sh-opc.h: Likewise.
254 2016-06-01 Graham Markall <graham.markall@embecosm.com>
256 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
257 0,b,limm to the rflt instruction.
259 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
261 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
264 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
267 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
268 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
269 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
270 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
271 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
272 * i386-init.h: Regenerated.
274 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
277 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
278 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
279 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
280 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
281 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
282 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
283 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
284 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
285 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
286 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
287 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
288 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
289 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
290 CpuRegMask for AVX512.
291 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
293 (set_bitfield_from_cpu_flag_init): New function.
294 (set_bitfield): Remove const on f. Call
295 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
296 * i386-opc.h (CpuRegMMX): New.
297 (CpuRegXMM): Likewise.
298 (CpuRegYMM): Likewise.
299 (CpuRegZMM): Likewise.
300 (CpuRegMask): Likewise.
301 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
303 * i386-init.h: Regenerated.
304 * i386-tbl.h: Likewise.
306 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
309 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
310 (opcode_modifiers): Add AMD64 and Intel64.
311 (main): Properly verify CpuMax.
312 * i386-opc.h (CpuAMD64): Removed.
313 (CpuIntel64): Likewise.
314 (CpuMax): Set to CpuNo64.
315 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
318 (i386_opcode_modifier): Add amd64 and intel64.
319 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
321 * i386-init.h: Regenerated.
322 * i386-tbl.h: Likewise.
324 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
327 * i386-gen.c (main): Fail if CpuMax is incorrect.
328 * i386-opc.h (CpuMax): Set to CpuIntel64.
329 * i386-tbl.h: Regenerated.
331 2016-05-27 Nick Clifton <nickc@redhat.com>
334 * msp430-dis.c (msp430dis_read_two_bytes): New function.
335 (msp430dis_opcode_unsigned): New function.
336 (msp430dis_opcode_signed): New function.
337 (msp430_singleoperand): Use the new opcode reading functions.
338 Only disassenmble bytes if they were successfully read.
339 (msp430_doubleoperand): Likewise.
340 (msp430_branchinstr): Likewise.
341 (msp430x_callx_instr): Likewise.
342 (print_insn_msp430): Check that it is safe to read bytes before
343 attempting disassembly. Use the new opcode reading functions.
345 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
347 * ppc-opc.c (CY): New define. Document it.
348 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
350 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
352 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
353 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
354 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
355 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
357 * i386-init.h: Regenerated.
359 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
362 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
363 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
364 * i386-init.h: Regenerated.
366 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
368 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
369 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
370 * i386-init.h: Regenerated.
372 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
374 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
376 (print_insn_arc): Set insn_type information.
377 * arc-opc.c (C_CC): Add F_CLASS_COND.
378 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
379 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
380 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
381 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
382 (brne, brne_s, jeq_s, jne_s): Likewise.
384 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
386 * arc-tbl.h (neg): New instruction variant.
388 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
390 * arc-dis.c (find_format, find_format, get_auxreg)
391 (print_insn_arc): Changed.
392 * arc-ext.h (INSERT_XOP): Likewise.
394 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
396 * tic54x-dis.c (sprint_mmr): Adjust.
397 * tic54x-opc.c: Likewise.
399 2016-05-19 Alan Modra <amodra@gmail.com>
401 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
403 2016-05-19 Alan Modra <amodra@gmail.com>
405 * ppc-opc.c: Formatting.
406 (NSISIGNOPT): Define.
407 (powerpc_opcodes <subis>): Use NSISIGNOPT.
409 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
411 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
412 replacing references to `micromips_ase' throughout.
413 (_print_insn_mips): Don't use file-level microMIPS annotation to
414 determine the disassembly mode with the symbol table.
416 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
418 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
420 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
422 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
424 * mips-opc.c (D34): New macro.
425 (mips_builtin_opcodes): Define bposge32c for DSPr3.
427 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
429 * i386-dis.c (prefix_table): Add RDPID instruction.
430 * i386-gen.c (cpu_flag_init): Add RDPID flag.
431 (cpu_flags): Add RDPID bitfield.
432 * i386-opc.h (enum): Add RDPID element.
433 (i386_cpu_flags): Add RDPID field.
434 * i386-opc.tbl: Add RDPID instruction.
435 * i386-init.h: Regenerate.
436 * i386-tbl.h: Regenerate.
438 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
440 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
441 branch type of a symbol.
442 (print_insn): Likewise.
444 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
446 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
447 Mainline Security Extensions instructions.
448 (thumb_opcodes): Add entries for narrow ARMv8-M Security
449 Extensions instructions.
450 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
452 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
455 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
457 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
459 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
461 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
462 (arcExtMap_genOpcode): Likewise.
463 * arc-opc.c (arg_32bit_rc): Define new variable.
464 (arg_32bit_u6): Likewise.
465 (arg_32bit_limm): Likewise.
467 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
469 * aarch64-gen.c (VERIFIER): Define.
470 * aarch64-opc.c (VERIFIER): Define.
471 (verify_ldpsw): Use static linkage.
472 * aarch64-opc.h (verify_ldpsw): Remove.
473 * aarch64-tbl.h: Use VERIFIER for verifiers.
475 2016-04-28 Nick Clifton <nickc@redhat.com>
478 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
479 * aarch64-opc.c (verify_ldpsw): New function.
480 * aarch64-opc.h (verify_ldpsw): New prototype.
481 * aarch64-tbl.h: Add initialiser for verifier field.
482 (LDPSW): Set verifier to verify_ldpsw.
484 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
488 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
489 smaller than address size.
491 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
493 * alpha-dis.c: Regenerate.
494 * crx-dis.c: Likewise.
495 * disassemble.c: Likewise.
496 * epiphany-opc.c: Likewise.
497 * fr30-opc.c: Likewise.
498 * frv-opc.c: Likewise.
499 * ip2k-opc.c: Likewise.
500 * iq2000-opc.c: Likewise.
501 * lm32-opc.c: Likewise.
502 * lm32-opinst.c: Likewise.
503 * m32c-opc.c: Likewise.
504 * m32r-opc.c: Likewise.
505 * m32r-opinst.c: Likewise.
506 * mep-opc.c: Likewise.
507 * mt-opc.c: Likewise.
508 * or1k-opc.c: Likewise.
509 * or1k-opinst.c: Likewise.
510 * tic80-opc.c: Likewise.
511 * xc16x-opc.c: Likewise.
512 * xstormy16-opc.c: Likewise.
514 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
516 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
517 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
518 calcsd, and calcxd instructions.
519 * arc-opc.c (insert_nps_bitop_size): Delete.
520 (extract_nps_bitop_size): Delete.
521 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
522 (extract_nps_qcmp_m3): Define.
523 (extract_nps_qcmp_m2): Define.
524 (extract_nps_qcmp_m1): Define.
525 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
526 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
527 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
528 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
529 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
532 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
534 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
536 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
538 * Makefile.in: Regenerated with automake 1.11.6.
539 * aclocal.m4: Likewise.
541 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
543 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
545 * arc-opc.c (insert_nps_cmem_uimm16): New function.
546 (extract_nps_cmem_uimm16): New function.
547 (arc_operands): Add NPS_XLDST_UIMM16 operand.
549 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
551 * arc-dis.c (arc_insn_length): New function.
552 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
553 (find_format): Change insnLen parameter to unsigned.
555 2016-04-13 Nick Clifton <nickc@redhat.com>
558 * v850-opc.c (v850_opcodes): Correct masks for long versions of
559 the LD.B and LD.BU instructions.
561 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
563 * arc-dis.c (find_format): Check for extension flags.
564 (print_flags): New function.
565 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
567 * arc-ext.c (arcExtMap_coreRegName): Use
568 LAST_EXTENSION_CORE_REGISTER.
569 (arcExtMap_coreReadWrite): Likewise.
570 (dump_ARC_extmap): Update printing.
571 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
572 (arc_aux_regs): Add cpu field.
573 * arc-regs.h: Add cpu field, lower case name aux registers.
575 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
577 * arc-tbl.h: Add rtsc, sleep with no arguments.
579 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
581 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
583 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
584 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
585 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
586 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
587 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
588 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
589 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
590 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
591 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
592 (arc_opcode arc_opcodes): Null terminate the array.
593 (arc_num_opcodes): Remove.
594 * arc-ext.h (INSERT_XOP): Define.
595 (extInstruction_t): Likewise.
596 (arcExtMap_instName): Delete.
597 (arcExtMap_insn): New function.
598 (arcExtMap_genOpcode): Likewise.
599 * arc-ext.c (ExtInstruction): Remove.
600 (create_map): Zero initialize instruction fields.
601 (arcExtMap_instName): Remove.
602 (arcExtMap_insn): New function.
603 (dump_ARC_extmap): More info while debuging.
604 (arcExtMap_genOpcode): New function.
605 * arc-dis.c (find_format): New function.
606 (print_insn_arc): Use find_format.
607 (arc_get_disassembler): Enable dump_ARC_extmap only when
610 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
612 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
613 instruction bits out.
615 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
617 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
618 * arc-opc.c (arc_flag_operands): Add new flags.
619 (arc_flag_classes): Add new classes.
621 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
623 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
625 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
627 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
628 encode1, rflt, crc16, and crc32 instructions.
629 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
630 (arc_flag_classes): Add C_NPS_R.
631 (insert_nps_bitop_size_2b): New function.
632 (extract_nps_bitop_size_2b): Likewise.
633 (insert_nps_bitop_uimm8): Likewise.
634 (extract_nps_bitop_uimm8): Likewise.
635 (arc_operands): Add new operand entries.
637 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
639 * arc-regs.h: Add a new subclass field. Add double assist
640 accumulator register values.
641 * arc-tbl.h: Use DPA subclass to mark the double assist
642 instructions. Use DPX/SPX subclas to mark the FPX instructions.
643 * arc-opc.c (RSP): Define instead of SP.
644 (arc_aux_regs): Add the subclass field.
646 2016-04-05 Jiong Wang <jiong.wang@arm.com>
648 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
650 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
652 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
655 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
657 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
658 issues. No functional changes.
660 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
662 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
663 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
664 (RTT): Remove duplicate.
665 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
666 (PCT_CONFIG*): Remove.
667 (D1L, D1H, D2H, D2L): Define.
669 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
671 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
673 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
675 * arc-tbl.h (invld07): Remove.
676 * arc-ext-tbl.h: New file.
677 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
678 * arc-opc.c (arc_opcodes): Add ext-tbl include.
680 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
682 Fix -Wstack-usage warnings.
683 * aarch64-dis.c (print_operands): Substitute size.
684 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
686 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
688 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
689 to get a proper diagnostic when an invalid ASR register is used.
691 2016-03-22 Nick Clifton <nickc@redhat.com>
693 * configure: Regenerate.
695 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
697 * arc-nps400-tbl.h: New file.
698 * arc-opc.c: Add top level comment.
699 (insert_nps_3bit_dst): New function.
700 (extract_nps_3bit_dst): New function.
701 (insert_nps_3bit_src2): New function.
702 (extract_nps_3bit_src2): New function.
703 (insert_nps_bitop_size): New function.
704 (extract_nps_bitop_size): New function.
705 (arc_flag_operands): Add nps400 entries.
706 (arc_flag_classes): Add nps400 entries.
707 (arc_operands): Add nps400 entries.
708 (arc_opcodes): Add nps400 include.
710 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
712 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
713 the new class enum values.
715 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
717 * arc-dis.c (print_insn_arc): Handle nps400.
719 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
721 * arc-opc.c (BASE): Delete.
723 2016-03-18 Nick Clifton <nickc@redhat.com>
726 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
727 of MOV insn that aliases an ORR insn.
729 2016-03-16 Jiong Wang <jiong.wang@arm.com>
731 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
733 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
735 * mcore-opc.h: Add const qualifiers.
736 * microblaze-opc.h (struct op_code_struct): Likewise.
737 * sh-opc.h: Likewise.
738 * tic4x-dis.c (tic4x_print_indirect): Likewise.
739 (tic4x_print_op): Likewise.
741 2016-03-02 Alan Modra <amodra@gmail.com>
743 * or1k-desc.h: Regenerate.
744 * fr30-ibld.c: Regenerate.
745 * rl78-decode.c: Regenerate.
747 2016-03-01 Nick Clifton <nickc@redhat.com>
750 * rl78-dis.c (print_insn_rl78_common): Fix typo.
752 2016-02-24 Renlin Li <renlin.li@arm.com>
754 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
755 (print_insn_coprocessor): Support fp16 instructions.
757 2016-02-24 Renlin Li <renlin.li@arm.com>
759 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
762 2016-02-24 Renlin Li <renlin.li@arm.com>
764 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
765 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
767 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
769 * i386-dis.c (print_insn): Parenthesize expression to prevent
773 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
774 Janek van Oirschot <jvanoirs@synopsys.com>
776 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
779 2016-02-04 Nick Clifton <nickc@redhat.com>
782 * msp430-dis.c (print_insn_msp430): Add a special case for
783 decoding an RRC instruction with the ZC bit set in the extension
786 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
788 * cgen-ibld.in (insert_normal): Rework calculation of shift.
789 * epiphany-ibld.c: Regenerate.
790 * fr30-ibld.c: Regenerate.
791 * frv-ibld.c: Regenerate.
792 * ip2k-ibld.c: Regenerate.
793 * iq2000-ibld.c: Regenerate.
794 * lm32-ibld.c: Regenerate.
795 * m32c-ibld.c: Regenerate.
796 * m32r-ibld.c: Regenerate.
797 * mep-ibld.c: Regenerate.
798 * mt-ibld.c: Regenerate.
799 * or1k-ibld.c: Regenerate.
800 * xc16x-ibld.c: Regenerate.
801 * xstormy16-ibld.c: Regenerate.
803 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
805 * epiphany-dis.c: Regenerated from latest cpu files.
807 2016-02-01 Michael McConville <mmcco@mykolab.com>
809 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
812 2016-01-25 Renlin Li <renlin.li@arm.com>
814 * arm-dis.c (mapping_symbol_for_insn): New function.
815 (find_ifthen_state): Call mapping_symbol_for_insn().
817 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
819 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
820 of MSR UAO immediate operand.
822 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
824 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
827 2016-01-17 Alan Modra <amodra@gmail.com>
829 * configure: Regenerate.
831 2016-01-14 Nick Clifton <nickc@redhat.com>
833 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
834 instructions that can support stack pointer operations.
835 * rl78-decode.c: Regenerate.
836 * rl78-dis.c: Fix display of stack pointer in MOVW based
839 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
841 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
842 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
843 erxtatus_el1 and erxaddr_el1.
845 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
847 * arm-dis.c (arm_opcodes): Add "esb".
848 (thumb_opcodes): Likewise.
850 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
852 * ppc-opc.c <xscmpnedp>: Delete.
853 <xvcmpnedp>: Likewise.
854 <xvcmpnedp.>: Likewise.
855 <xvcmpnesp>: Likewise.
856 <xvcmpnesp.>: Likewise.
858 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
861 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
864 2016-01-01 Alan Modra <amodra@gmail.com>
866 Update year range in copyright notice of all files.
868 For older changes see ChangeLog-2015
870 Copyright (C) 2016 Free Software Foundation, Inc.
872 Copying and distribution of this file, with or without modification,
873 are permitted in any medium without royalty provided the copyright
874 notice and this notice are preserved.
880 version-control: never