1 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
3 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
4 integer immediate operands.
5 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
6 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
7 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
8 * aarch64-opc.c (fields): Add corresponding entries.
9 (operand_general_constraint_met_p): Handle the new SVE integer
11 (aarch64_print_operand): Likewise.
12 (aarch64_sve_dupm_mov_immediate_p): New function.
13 * aarch64-opc-2.c: Regenerate.
14 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
15 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
16 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
17 (aarch64_ins_limm): ...here.
18 (aarch64_ins_inv_limm): New function.
19 (aarch64_ins_sve_aimm): Likewise.
20 (aarch64_ins_sve_asimm): Likewise.
21 (aarch64_ins_sve_limm_mov): Likewise.
22 (aarch64_ins_sve_shlimm): Likewise.
23 (aarch64_ins_sve_shrimm): Likewise.
24 * aarch64-asm-2.c: Regenerate.
25 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
26 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
27 * aarch64-dis.c (decode_limm): New function, split out from...
28 (aarch64_ext_limm): ...here.
29 (aarch64_ext_inv_limm): New function.
30 (decode_sve_aimm): Likewise.
31 (aarch64_ext_sve_aimm): Likewise.
32 (aarch64_ext_sve_asimm): Likewise.
33 (aarch64_ext_sve_limm_mov): Likewise.
34 (aarch64_top_bit): Likewise.
35 (aarch64_ext_sve_shlimm): Likewise.
36 (aarch64_ext_sve_shrimm): Likewise.
37 * aarch64-dis-2.c: Regenerate.
39 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
41 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
43 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
44 the AARCH64_MOD_MUL_VL entry.
45 (value_aligned_p): Cope with non-power-of-two alignments.
46 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
47 (print_immediate_offset_address): Likewise.
48 (aarch64_print_operand): Likewise.
49 * aarch64-opc-2.c: Regenerate.
50 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
51 (ins_sve_addr_ri_s9xvl): New inserters.
52 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
53 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
54 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
55 * aarch64-asm-2.c: Regenerate.
56 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
57 (ext_sve_addr_ri_s9xvl): New extractors.
58 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
59 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
60 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
61 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
62 * aarch64-dis-2.c: Regenerate.
64 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
66 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
68 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
69 (FLD_SVE_xs_22): New aarch64_field_kinds.
70 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
71 (get_operand_specific_data): New function.
72 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
73 FLD_SVE_xs_14 and FLD_SVE_xs_22.
74 (operand_general_constraint_met_p): Handle the new SVE address
77 (get_addr_sve_reg_name): New function.
78 (aarch64_print_operand): Handle the new SVE address operands.
79 * aarch64-opc-2.c: Regenerate.
80 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
81 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
82 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
83 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
84 (aarch64_ins_sve_addr_rr_lsl): Likewise.
85 (aarch64_ins_sve_addr_rz_xtw): Likewise.
86 (aarch64_ins_sve_addr_zi_u5): Likewise.
87 (aarch64_ins_sve_addr_zz): Likewise.
88 (aarch64_ins_sve_addr_zz_lsl): Likewise.
89 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
90 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
91 * aarch64-asm-2.c: Regenerate.
92 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
93 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
94 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
95 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
96 (aarch64_ext_sve_addr_ri_u6): Likewise.
97 (aarch64_ext_sve_addr_rr_lsl): Likewise.
98 (aarch64_ext_sve_addr_rz_xtw): Likewise.
99 (aarch64_ext_sve_addr_zi_u5): Likewise.
100 (aarch64_ext_sve_addr_zz): Likewise.
101 (aarch64_ext_sve_addr_zz_lsl): Likewise.
102 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
103 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
104 * aarch64-dis-2.c: Regenerate.
106 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
108 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
109 AARCH64_OPND_SVE_PATTERN_SCALED.
110 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
111 * aarch64-opc.c (fields): Add a corresponding entry.
112 (set_multiplier_out_of_range_error): New function.
113 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
114 (operand_general_constraint_met_p): Handle
115 AARCH64_OPND_SVE_PATTERN_SCALED.
116 (print_register_offset_address): Use PRIi64 to print the
118 (aarch64_print_operand): Likewise. Handle
119 AARCH64_OPND_SVE_PATTERN_SCALED.
120 * aarch64-opc-2.c: Regenerate.
121 * aarch64-asm.h (ins_sve_scale): New inserter.
122 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
123 * aarch64-asm-2.c: Regenerate.
124 * aarch64-dis.h (ext_sve_scale): New inserter.
125 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
126 * aarch64-dis-2.c: Regenerate.
128 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
130 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
131 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
132 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
133 (FLD_SVE_prfop): Likewise.
134 * aarch64-opc.c: Include libiberty.h.
135 (aarch64_sve_pattern_array): New variable.
136 (aarch64_sve_prfop_array): Likewise.
137 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
138 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
139 AARCH64_OPND_SVE_PRFOP.
140 * aarch64-asm-2.c: Regenerate.
141 * aarch64-dis-2.c: Likewise.
142 * aarch64-opc-2.c: Likewise.
144 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
146 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
147 AARCH64_OPND_QLF_P_[ZM].
148 (aarch64_print_operand): Print /z and /m where appropriate.
150 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
152 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
153 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
154 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
155 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
156 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
157 * aarch64-opc.c (fields): Add corresponding entries here.
158 (operand_general_constraint_met_p): Check that SVE register lists
159 have the correct length. Check the ranges of SVE index registers.
160 Check for cases where p8-p15 are used in 3-bit predicate fields.
161 (aarch64_print_operand): Handle the new SVE operands.
162 * aarch64-opc-2.c: Regenerate.
163 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
164 * aarch64-asm.c (aarch64_ins_sve_index): New function.
165 (aarch64_ins_sve_reglist): Likewise.
166 * aarch64-asm-2.c: Regenerate.
167 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
168 * aarch64-dis.c (aarch64_ext_sve_index): New function.
169 (aarch64_ext_sve_reglist): Likewise.
170 * aarch64-dis-2.c: Regenerate.
172 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
174 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
175 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
176 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
177 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
180 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
182 * aarch64-opc.c (get_offset_int_reg_name): New function.
183 (print_immediate_offset_address): Likewise.
184 (print_register_offset_address): Take the base and offset
185 registers as parameters.
186 (aarch64_print_operand): Update caller accordingly. Use
187 print_immediate_offset_address.
189 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
191 * aarch64-opc.c (BANK): New macro.
192 (R32, R64): Take a register number as argument
195 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
197 * aarch64-opc.c (print_register_list): Add a prefix parameter.
198 (aarch64_print_operand): Update accordingly.
200 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
202 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
204 * aarch64-asm.h (ins_fpimm): New inserter.
205 * aarch64-asm.c (aarch64_ins_fpimm): New function.
206 * aarch64-asm-2.c: Regenerate.
207 * aarch64-dis.h (ext_fpimm): New extractor.
208 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
209 (aarch64_ext_fpimm): New function.
210 * aarch64-dis-2.c: Regenerate.
212 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
214 * aarch64-asm.c: Include libiberty.h.
215 (insert_fields): New function.
216 (aarch64_ins_imm): Use it.
217 * aarch64-dis.c (extract_fields): New function.
218 (aarch64_ext_imm): Use it.
220 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
222 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
223 with an esize parameter.
224 (operand_general_constraint_met_p): Update accordingly.
225 Fix misindented code.
226 * aarch64-asm.c (aarch64_ins_limm): Update call to
227 aarch64_logical_immediate_p.
229 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
231 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
233 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
235 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
237 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
239 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
241 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
243 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
244 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
245 xor3>: Delete mnemonics.
246 <cp_abort>: Rename mnemonic from ...
247 <cpabort>: ...to this.
248 <setb>: Change to a X form instruction.
249 <sync>: Change to 1 operand form.
250 <copy>: Delete mnemonic.
251 <copy_first>: Rename mnemonic from ...
253 <paste, paste.>: Delete mnemonics.
254 <paste_last>: Rename mnemonic from ...
255 <paste.>: ...to this.
257 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
259 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
261 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
263 * s390-mkopc.c (main): Support alternate arch strings.
265 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
267 * s390-opc.txt: Fix kmctr instruction type.
269 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
271 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
272 * i386-init.h: Regenerated.
274 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
276 * opcodes/arc-dis.c (print_insn_arc): Changed.
278 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
280 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
283 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
285 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
286 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
287 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
289 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
291 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
292 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
293 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
294 PREFIX_MOD_3_0FAE_REG_4.
295 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
296 PREFIX_MOD_3_0FAE_REG_4.
297 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
298 (cpu_flags): Add CpuPTWRITE.
299 * i386-opc.h (CpuPTWRITE): New.
300 (i386_cpu_flags): Add cpuptwrite.
301 * i386-opc.tbl: Add ptwrite instruction.
302 * i386-init.h: Regenerated.
303 * i386-tbl.h: Likewise.
305 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
307 * arc-dis.h: Wrap around in extern "C".
309 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
311 * aarch64-tbl.h (V8_2_INSN): New macro.
312 (aarch64_opcode_table): Use it.
314 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
316 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
317 CORE_INSN, __FP_INSN and SIMD_INSN.
319 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
321 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
322 (aarch64_opcode_table): Update uses accordingly.
324 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
325 Kwok Cheung Yeung <kcy@codesourcery.com>
328 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
329 'e_cmplwi' to 'e_cmpli' instead.
330 (OPVUPRT, OPVUPRT_MASK): Define.
331 (powerpc_opcodes): Add E200Z4 insns.
332 (vle_opcodes): Add context save/restore insns.
334 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
336 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
337 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
340 2016-07-27 Graham Markall <graham.markall@embecosm.com>
342 * arc-nps400-tbl.h: Change block comments to GNU format.
343 * arc-dis.c: Add new globals addrtypenames,
344 addrtypenames_max, and addtypeunknown.
345 (get_addrtype): New function.
346 (print_insn_arc): Print colons and address types when
348 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
349 define insert and extract functions for all address types.
350 (arc_operands): Add operands for colon and all address
352 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
353 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
354 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
355 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
356 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
357 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
359 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
361 * configure: Regenerated.
363 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
365 * arc-dis.c (skipclass): New structure.
366 (decodelist): New variable.
367 (is_compatible_p): New function.
368 (new_element): Likewise.
369 (skip_class_p): Likewise.
370 (find_format_from_table): Use skip_class_p function.
371 (find_format): Decode first the extension instructions.
372 (print_insn_arc): Select either ARCEM or ARCHS based on elf
374 (parse_option): New function.
375 (parse_disassembler_options): Likewise.
376 (print_arc_disassembler_options): Likewise.
377 (print_insn_arc): Use parse_disassembler_options function. Proper
378 select ARCv2 cpu variant.
379 * disassemble.c (disassembler_usage): Add ARC disassembler
382 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
384 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
385 annotation from the "nal" entry and reorder it beyond "bltzal".
387 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
389 * sparc-opc.c (ldtxa): New macro.
390 (sparc_opcodes): Use the macro defined above to add entries for
391 the LDTXA instructions.
392 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
395 2016-07-07 James Bowman <james.bowman@ftdichip.com>
397 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
400 2016-07-01 Jan Beulich <jbeulich@suse.com>
402 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
403 (movzb): Adjust to cover all permitted suffixes.
405 * i386-tbl.h: Re-generate.
407 2016-07-01 Jan Beulich <jbeulich@suse.com>
409 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
410 (lgdt): Remove Tbyte from non-64-bit variant.
411 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
412 xsaves64, xsavec64): Remove Disp16.
413 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
414 Remove Disp32S from non-64-bit variants. Remove Disp16 from
416 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
417 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
418 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
420 * i386-tbl.h: Re-generate.
422 2016-07-01 Jan Beulich <jbeulich@suse.com>
424 * i386-opc.tbl (xlat): Remove RepPrefixOk.
425 * i386-tbl.h: Re-generate.
427 2016-06-30 Yao Qi <yao.qi@linaro.org>
429 * arm-dis.c (print_insn): Fix typo in comment.
431 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
433 * aarch64-opc.c (operand_general_constraint_met_p): Check the
434 range of ldst_elemlist operands.
435 (print_register_list): Use PRIi64 to print the index.
436 (aarch64_print_operand): Likewise.
438 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
440 * mcore-opc.h: Remove sentinal.
441 * mcore-dis.c (print_insn_mcore): Adjust.
443 2016-06-23 Graham Markall <graham.markall@embecosm.com>
445 * arc-opc.c: Correct description of availability of NPS400
448 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
450 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
451 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
452 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
453 xor3>: New mnemonics.
454 <setb>: Change to a VX form instruction.
455 (insert_sh6): Add support for rldixor.
456 (extract_sh6): Likewise.
458 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
460 * arc-ext.h: Wrap in extern C.
462 2016-06-21 Graham Markall <graham.markall@embecosm.com>
464 * arc-dis.c (arc_insn_length): Add comment on instruction length.
465 Use same method for determining instruction length on ARC700 and
467 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
468 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
469 with the NPS400 subclass.
470 * arc-opc.c: Likewise.
472 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
474 * sparc-opc.c (rdasr): New macro.
480 (sparc_opcodes): Use the macros above to fix and expand the
481 definition of read/write instructions from/to
482 asr/privileged/hyperprivileged instructions.
483 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
484 %hva_mask_nz. Prefer softint_set and softint_clear over
485 set_softint and clear_softint.
486 (print_insn_sparc): Support %ver in Rd.
488 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
490 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
491 architecture according to the hardware capabilities they require.
493 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
495 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
496 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
497 bfd_mach_sparc_v9{c,d,e,v,m}.
498 * sparc-opc.c (MASK_V9C): Define.
499 (MASK_V9D): Likewise.
500 (MASK_V9E): Likewise.
501 (MASK_V9V): Likewise.
502 (MASK_V9M): Likewise.
503 (v6): Add MASK_V9{C,D,E,V,M}.
504 (v6notlet): Likewise.
508 (v9andleon): Likewise.
516 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
518 2016-06-15 Nick Clifton <nickc@redhat.com>
520 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
521 constants to match expected behaviour.
522 (nds32_parse_opcode): Likewise. Also for whitespace.
524 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
526 * arc-opc.c (extract_rhv1): Extract value from insn.
528 2016-06-14 Graham Markall <graham.markall@embecosm.com>
530 * arc-nps400-tbl.h: Add ldbit instruction.
531 * arc-opc.c: Add flag classes required for ldbit.
533 2016-06-14 Graham Markall <graham.markall@embecosm.com>
535 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
536 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
537 support the above instructions.
539 2016-06-14 Graham Markall <graham.markall@embecosm.com>
541 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
542 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
543 csma, cbba, zncv, and hofs.
544 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
545 support the above instructions.
547 2016-06-06 Graham Markall <graham.markall@embecosm.com>
549 * arc-nps400-tbl.h: Add andab and orab instructions.
551 2016-06-06 Graham Markall <graham.markall@embecosm.com>
553 * arc-nps400-tbl.h: Add addl-like instructions.
555 2016-06-06 Graham Markall <graham.markall@embecosm.com>
557 * arc-nps400-tbl.h: Add mxb and imxb instructions.
559 2016-06-06 Graham Markall <graham.markall@embecosm.com>
561 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
564 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
566 * s390-dis.c (option_use_insn_len_bits_p): New file scope
568 (init_disasm): Handle new command line option "insnlength".
569 (print_s390_disassembler_options): Mention new option in help
571 (print_insn_s390): Use the encoded insn length when dumping
572 unknown instructions.
574 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
576 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
577 to the address and set as symbol address for LDS/ STS immediate operands.
579 2016-06-07 Alan Modra <amodra@gmail.com>
581 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
582 cpu for "vle" to e500.
583 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
584 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
585 (PPCNONE): Delete, substitute throughout.
586 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
587 except for major opcode 4 and 31.
588 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
590 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
592 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
593 ARM_EXT_RAS in relevant entries.
595 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
598 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
601 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
604 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
606 Add comments for '&'.
607 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
609 (intel_operand_size): Handle indir_v_mode.
610 (OP_E_register): Likewise.
611 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
612 64-bit indirect call/jmp for AMD64.
613 * i386-tbl.h: Regenerated
615 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
617 * arc-dis.c (struct arc_operand_iterator): New structure.
618 (find_format_from_table): All the old content from find_format,
619 with some minor adjustments, and parameter renaming.
620 (find_format_long_instructions): New function.
621 (find_format): Rewritten.
622 (arc_insn_length): Add LSB parameter.
623 (extract_operand_value): New function.
624 (operand_iterator_next): New function.
625 (print_insn_arc): Use new functions to find opcode, and iterator
627 * arc-opc.c (insert_nps_3bit_dst_short): New function.
628 (extract_nps_3bit_dst_short): New function.
629 (insert_nps_3bit_src2_short): New function.
630 (extract_nps_3bit_src2_short): New function.
631 (insert_nps_bitop1_size): New function.
632 (extract_nps_bitop1_size): New function.
633 (insert_nps_bitop2_size): New function.
634 (extract_nps_bitop2_size): New function.
635 (insert_nps_bitop_mod4_msb): New function.
636 (extract_nps_bitop_mod4_msb): New function.
637 (insert_nps_bitop_mod4_lsb): New function.
638 (extract_nps_bitop_mod4_lsb): New function.
639 (insert_nps_bitop_dst_pos3_pos4): New function.
640 (extract_nps_bitop_dst_pos3_pos4): New function.
641 (insert_nps_bitop_ins_ext): New function.
642 (extract_nps_bitop_ins_ext): New function.
643 (arc_operands): Add new operands.
644 (arc_long_opcodes): New global array.
645 (arc_num_long_opcodes): New global.
646 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
648 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
650 * nds32-asm.h: Add extern "C".
651 * sh-opc.h: Likewise.
653 2016-06-01 Graham Markall <graham.markall@embecosm.com>
655 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
656 0,b,limm to the rflt instruction.
658 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
660 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
663 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
666 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
667 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
668 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
669 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
670 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
671 * i386-init.h: Regenerated.
673 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
676 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
677 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
678 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
679 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
680 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
681 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
682 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
683 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
684 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
685 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
686 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
687 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
688 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
689 CpuRegMask for AVX512.
690 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
692 (set_bitfield_from_cpu_flag_init): New function.
693 (set_bitfield): Remove const on f. Call
694 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
695 * i386-opc.h (CpuRegMMX): New.
696 (CpuRegXMM): Likewise.
697 (CpuRegYMM): Likewise.
698 (CpuRegZMM): Likewise.
699 (CpuRegMask): Likewise.
700 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
702 * i386-init.h: Regenerated.
703 * i386-tbl.h: Likewise.
705 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
708 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
709 (opcode_modifiers): Add AMD64 and Intel64.
710 (main): Properly verify CpuMax.
711 * i386-opc.h (CpuAMD64): Removed.
712 (CpuIntel64): Likewise.
713 (CpuMax): Set to CpuNo64.
714 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
717 (i386_opcode_modifier): Add amd64 and intel64.
718 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
720 * i386-init.h: Regenerated.
721 * i386-tbl.h: Likewise.
723 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
726 * i386-gen.c (main): Fail if CpuMax is incorrect.
727 * i386-opc.h (CpuMax): Set to CpuIntel64.
728 * i386-tbl.h: Regenerated.
730 2016-05-27 Nick Clifton <nickc@redhat.com>
733 * msp430-dis.c (msp430dis_read_two_bytes): New function.
734 (msp430dis_opcode_unsigned): New function.
735 (msp430dis_opcode_signed): New function.
736 (msp430_singleoperand): Use the new opcode reading functions.
737 Only disassenmble bytes if they were successfully read.
738 (msp430_doubleoperand): Likewise.
739 (msp430_branchinstr): Likewise.
740 (msp430x_callx_instr): Likewise.
741 (print_insn_msp430): Check that it is safe to read bytes before
742 attempting disassembly. Use the new opcode reading functions.
744 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
746 * ppc-opc.c (CY): New define. Document it.
747 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
749 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
751 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
752 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
753 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
754 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
756 * i386-init.h: Regenerated.
758 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
761 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
762 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
763 * i386-init.h: Regenerated.
765 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
767 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
768 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
769 * i386-init.h: Regenerated.
771 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
773 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
775 (print_insn_arc): Set insn_type information.
776 * arc-opc.c (C_CC): Add F_CLASS_COND.
777 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
778 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
779 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
780 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
781 (brne, brne_s, jeq_s, jne_s): Likewise.
783 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
785 * arc-tbl.h (neg): New instruction variant.
787 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
789 * arc-dis.c (find_format, find_format, get_auxreg)
790 (print_insn_arc): Changed.
791 * arc-ext.h (INSERT_XOP): Likewise.
793 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
795 * tic54x-dis.c (sprint_mmr): Adjust.
796 * tic54x-opc.c: Likewise.
798 2016-05-19 Alan Modra <amodra@gmail.com>
800 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
802 2016-05-19 Alan Modra <amodra@gmail.com>
804 * ppc-opc.c: Formatting.
805 (NSISIGNOPT): Define.
806 (powerpc_opcodes <subis>): Use NSISIGNOPT.
808 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
810 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
811 replacing references to `micromips_ase' throughout.
812 (_print_insn_mips): Don't use file-level microMIPS annotation to
813 determine the disassembly mode with the symbol table.
815 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
817 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
819 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
821 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
823 * mips-opc.c (D34): New macro.
824 (mips_builtin_opcodes): Define bposge32c for DSPr3.
826 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
828 * i386-dis.c (prefix_table): Add RDPID instruction.
829 * i386-gen.c (cpu_flag_init): Add RDPID flag.
830 (cpu_flags): Add RDPID bitfield.
831 * i386-opc.h (enum): Add RDPID element.
832 (i386_cpu_flags): Add RDPID field.
833 * i386-opc.tbl: Add RDPID instruction.
834 * i386-init.h: Regenerate.
835 * i386-tbl.h: Regenerate.
837 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
839 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
840 branch type of a symbol.
841 (print_insn): Likewise.
843 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
845 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
846 Mainline Security Extensions instructions.
847 (thumb_opcodes): Add entries for narrow ARMv8-M Security
848 Extensions instructions.
849 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
851 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
854 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
856 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
858 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
860 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
861 (arcExtMap_genOpcode): Likewise.
862 * arc-opc.c (arg_32bit_rc): Define new variable.
863 (arg_32bit_u6): Likewise.
864 (arg_32bit_limm): Likewise.
866 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
868 * aarch64-gen.c (VERIFIER): Define.
869 * aarch64-opc.c (VERIFIER): Define.
870 (verify_ldpsw): Use static linkage.
871 * aarch64-opc.h (verify_ldpsw): Remove.
872 * aarch64-tbl.h: Use VERIFIER for verifiers.
874 2016-04-28 Nick Clifton <nickc@redhat.com>
877 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
878 * aarch64-opc.c (verify_ldpsw): New function.
879 * aarch64-opc.h (verify_ldpsw): New prototype.
880 * aarch64-tbl.h: Add initialiser for verifier field.
881 (LDPSW): Set verifier to verify_ldpsw.
883 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
887 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
888 smaller than address size.
890 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
892 * alpha-dis.c: Regenerate.
893 * crx-dis.c: Likewise.
894 * disassemble.c: Likewise.
895 * epiphany-opc.c: Likewise.
896 * fr30-opc.c: Likewise.
897 * frv-opc.c: Likewise.
898 * ip2k-opc.c: Likewise.
899 * iq2000-opc.c: Likewise.
900 * lm32-opc.c: Likewise.
901 * lm32-opinst.c: Likewise.
902 * m32c-opc.c: Likewise.
903 * m32r-opc.c: Likewise.
904 * m32r-opinst.c: Likewise.
905 * mep-opc.c: Likewise.
906 * mt-opc.c: Likewise.
907 * or1k-opc.c: Likewise.
908 * or1k-opinst.c: Likewise.
909 * tic80-opc.c: Likewise.
910 * xc16x-opc.c: Likewise.
911 * xstormy16-opc.c: Likewise.
913 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
915 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
916 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
917 calcsd, and calcxd instructions.
918 * arc-opc.c (insert_nps_bitop_size): Delete.
919 (extract_nps_bitop_size): Delete.
920 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
921 (extract_nps_qcmp_m3): Define.
922 (extract_nps_qcmp_m2): Define.
923 (extract_nps_qcmp_m1): Define.
924 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
925 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
926 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
927 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
928 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
931 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
933 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
935 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
937 * Makefile.in: Regenerated with automake 1.11.6.
938 * aclocal.m4: Likewise.
940 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
942 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
944 * arc-opc.c (insert_nps_cmem_uimm16): New function.
945 (extract_nps_cmem_uimm16): New function.
946 (arc_operands): Add NPS_XLDST_UIMM16 operand.
948 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
950 * arc-dis.c (arc_insn_length): New function.
951 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
952 (find_format): Change insnLen parameter to unsigned.
954 2016-04-13 Nick Clifton <nickc@redhat.com>
957 * v850-opc.c (v850_opcodes): Correct masks for long versions of
958 the LD.B and LD.BU instructions.
960 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
962 * arc-dis.c (find_format): Check for extension flags.
963 (print_flags): New function.
964 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
966 * arc-ext.c (arcExtMap_coreRegName): Use
967 LAST_EXTENSION_CORE_REGISTER.
968 (arcExtMap_coreReadWrite): Likewise.
969 (dump_ARC_extmap): Update printing.
970 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
971 (arc_aux_regs): Add cpu field.
972 * arc-regs.h: Add cpu field, lower case name aux registers.
974 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
976 * arc-tbl.h: Add rtsc, sleep with no arguments.
978 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
980 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
982 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
983 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
984 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
985 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
986 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
987 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
988 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
989 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
990 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
991 (arc_opcode arc_opcodes): Null terminate the array.
992 (arc_num_opcodes): Remove.
993 * arc-ext.h (INSERT_XOP): Define.
994 (extInstruction_t): Likewise.
995 (arcExtMap_instName): Delete.
996 (arcExtMap_insn): New function.
997 (arcExtMap_genOpcode): Likewise.
998 * arc-ext.c (ExtInstruction): Remove.
999 (create_map): Zero initialize instruction fields.
1000 (arcExtMap_instName): Remove.
1001 (arcExtMap_insn): New function.
1002 (dump_ARC_extmap): More info while debuging.
1003 (arcExtMap_genOpcode): New function.
1004 * arc-dis.c (find_format): New function.
1005 (print_insn_arc): Use find_format.
1006 (arc_get_disassembler): Enable dump_ARC_extmap only when
1009 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1011 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1012 instruction bits out.
1014 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1016 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1017 * arc-opc.c (arc_flag_operands): Add new flags.
1018 (arc_flag_classes): Add new classes.
1020 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1022 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1024 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1026 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1027 encode1, rflt, crc16, and crc32 instructions.
1028 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1029 (arc_flag_classes): Add C_NPS_R.
1030 (insert_nps_bitop_size_2b): New function.
1031 (extract_nps_bitop_size_2b): Likewise.
1032 (insert_nps_bitop_uimm8): Likewise.
1033 (extract_nps_bitop_uimm8): Likewise.
1034 (arc_operands): Add new operand entries.
1036 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1038 * arc-regs.h: Add a new subclass field. Add double assist
1039 accumulator register values.
1040 * arc-tbl.h: Use DPA subclass to mark the double assist
1041 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1042 * arc-opc.c (RSP): Define instead of SP.
1043 (arc_aux_regs): Add the subclass field.
1045 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1047 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1049 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1051 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1054 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1056 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1057 issues. No functional changes.
1059 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1061 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1062 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1063 (RTT): Remove duplicate.
1064 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1065 (PCT_CONFIG*): Remove.
1066 (D1L, D1H, D2H, D2L): Define.
1068 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1070 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1072 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1074 * arc-tbl.h (invld07): Remove.
1075 * arc-ext-tbl.h: New file.
1076 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1077 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1079 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1081 Fix -Wstack-usage warnings.
1082 * aarch64-dis.c (print_operands): Substitute size.
1083 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1085 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1087 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1088 to get a proper diagnostic when an invalid ASR register is used.
1090 2016-03-22 Nick Clifton <nickc@redhat.com>
1092 * configure: Regenerate.
1094 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1096 * arc-nps400-tbl.h: New file.
1097 * arc-opc.c: Add top level comment.
1098 (insert_nps_3bit_dst): New function.
1099 (extract_nps_3bit_dst): New function.
1100 (insert_nps_3bit_src2): New function.
1101 (extract_nps_3bit_src2): New function.
1102 (insert_nps_bitop_size): New function.
1103 (extract_nps_bitop_size): New function.
1104 (arc_flag_operands): Add nps400 entries.
1105 (arc_flag_classes): Add nps400 entries.
1106 (arc_operands): Add nps400 entries.
1107 (arc_opcodes): Add nps400 include.
1109 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1111 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1112 the new class enum values.
1114 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1116 * arc-dis.c (print_insn_arc): Handle nps400.
1118 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1120 * arc-opc.c (BASE): Delete.
1122 2016-03-18 Nick Clifton <nickc@redhat.com>
1125 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1126 of MOV insn that aliases an ORR insn.
1128 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1130 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1132 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1134 * mcore-opc.h: Add const qualifiers.
1135 * microblaze-opc.h (struct op_code_struct): Likewise.
1136 * sh-opc.h: Likewise.
1137 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1138 (tic4x_print_op): Likewise.
1140 2016-03-02 Alan Modra <amodra@gmail.com>
1142 * or1k-desc.h: Regenerate.
1143 * fr30-ibld.c: Regenerate.
1144 * rl78-decode.c: Regenerate.
1146 2016-03-01 Nick Clifton <nickc@redhat.com>
1149 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1151 2016-02-24 Renlin Li <renlin.li@arm.com>
1153 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1154 (print_insn_coprocessor): Support fp16 instructions.
1156 2016-02-24 Renlin Li <renlin.li@arm.com>
1158 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1159 vminnm, vrint(mpna).
1161 2016-02-24 Renlin Li <renlin.li@arm.com>
1163 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1164 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1166 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1168 * i386-dis.c (print_insn): Parenthesize expression to prevent
1169 truncated addresses.
1172 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1173 Janek van Oirschot <jvanoirs@synopsys.com>
1175 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1178 2016-02-04 Nick Clifton <nickc@redhat.com>
1181 * msp430-dis.c (print_insn_msp430): Add a special case for
1182 decoding an RRC instruction with the ZC bit set in the extension
1185 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1187 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1188 * epiphany-ibld.c: Regenerate.
1189 * fr30-ibld.c: Regenerate.
1190 * frv-ibld.c: Regenerate.
1191 * ip2k-ibld.c: Regenerate.
1192 * iq2000-ibld.c: Regenerate.
1193 * lm32-ibld.c: Regenerate.
1194 * m32c-ibld.c: Regenerate.
1195 * m32r-ibld.c: Regenerate.
1196 * mep-ibld.c: Regenerate.
1197 * mt-ibld.c: Regenerate.
1198 * or1k-ibld.c: Regenerate.
1199 * xc16x-ibld.c: Regenerate.
1200 * xstormy16-ibld.c: Regenerate.
1202 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1204 * epiphany-dis.c: Regenerated from latest cpu files.
1206 2016-02-01 Michael McConville <mmcco@mykolab.com>
1208 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1211 2016-01-25 Renlin Li <renlin.li@arm.com>
1213 * arm-dis.c (mapping_symbol_for_insn): New function.
1214 (find_ifthen_state): Call mapping_symbol_for_insn().
1216 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1218 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1219 of MSR UAO immediate operand.
1221 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1223 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1224 instruction support.
1226 2016-01-17 Alan Modra <amodra@gmail.com>
1228 * configure: Regenerate.
1230 2016-01-14 Nick Clifton <nickc@redhat.com>
1232 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1233 instructions that can support stack pointer operations.
1234 * rl78-decode.c: Regenerate.
1235 * rl78-dis.c: Fix display of stack pointer in MOVW based
1238 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1240 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1241 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1242 erxtatus_el1 and erxaddr_el1.
1244 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1246 * arm-dis.c (arm_opcodes): Add "esb".
1247 (thumb_opcodes): Likewise.
1249 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1251 * ppc-opc.c <xscmpnedp>: Delete.
1252 <xvcmpnedp>: Likewise.
1253 <xvcmpnedp.>: Likewise.
1254 <xvcmpnesp>: Likewise.
1255 <xvcmpnesp.>: Likewise.
1257 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1260 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1263 2016-01-01 Alan Modra <amodra@gmail.com>
1265 Update year range in copyright notice of all files.
1267 For older changes see ChangeLog-2015
1269 Copyright (C) 2016 Free Software Foundation, Inc.
1271 Copying and distribution of this file, with or without modification,
1272 are permitted in any medium without royalty provided the copyright
1273 notice and this notice are preserved.
1279 version-control: never