1 2018-07-19 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.h (DISP8_SHIFT_VL): New.
4 * i386-opc.tbl (Disp8ShiftVL): Define.
5 (various): Fold AVX512VL templates into their respective
6 AVX512F counterparts where possible, using Disp8ShiftVL and
7 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
8 IgnoreSize) as appropriate.
9 * i386-tbl.h: Re-generate.
11 2018-07-19 Jan Beulich <jbeulich@suse.com>
13 * Makefile.am: Change dependencies and rule for
14 $(srcdir)/i386-init.h.
15 * Makefile.in: Re-generate.
16 * i386-gen.c (process_i386_opcodes): New local variable
17 "marker". Drop opening of input file. Recognize marker and line
19 * i386-opc.tbl (OPCODE_I386_H): Define.
20 (i386-opc.h): Include it.
23 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
26 * i386-opc.h (Byte): Update comments.
35 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
37 * i386-tbl.h: Regenerated.
39 2018-07-12 Sudakshina Das <sudi.das@arm.com>
41 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
42 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
43 * aarch64-asm-2.c: Regenerate.
44 * aarch64-dis-2.c: Regenerate.
45 * aarch64-opc-2.c: Regenerate.
47 2018-07-12 Tamar Christina <tamar.christina@arm.com>
50 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
51 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
52 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
53 sqdmulh, sqrdmulh): Use Em16.
55 2018-07-11 Sudakshina Das <sudi.das@arm.com>
57 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
58 csdb together with them.
59 (thumb32_opcodes): Likewise.
61 2018-07-11 Jan Beulich <jbeulich@suse.com>
63 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
64 requiring 32-bit registers as operands 2 and 3. Improve
66 (mwait, mwaitx): Fold templates. Improve comments.
67 OPERAND_TYPE_INOUTPORTREG.
68 * i386-tbl.h: Re-generate.
70 2018-07-11 Jan Beulich <jbeulich@suse.com>
72 * i386-gen.c (operand_type_init): Remove
73 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
74 OPERAND_TYPE_INOUTPORTREG.
75 * i386-init.h: Re-generate.
77 2018-07-11 Jan Beulich <jbeulich@suse.com>
79 * i386-opc.tbl (wrssd, wrussd): Add Dword.
80 (wrssq, wrussq): Add Qword.
81 * i386-tbl.h: Re-generate.
83 2018-07-11 Jan Beulich <jbeulich@suse.com>
85 * i386-opc.h: Rename OTMax to OTNum.
86 (OTNumOfUints): Adjust calculation.
87 (OTUnused): Directly alias to OTNum.
89 2018-07-09 Maciej W. Rozycki <macro@mips.com>
91 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
93 (lea_reg_xys): Likewise.
94 (print_insn_loop_primitive): Rename `reg' local variable to
97 2018-07-06 Tamar Christina <tamar.christina@arm.com>
100 * aarch64-tbl.h (ldarh): Fix disassembly mask.
102 2018-07-06 Tamar Christina <tamar.christina@arm.com>
105 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
106 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
108 2018-07-02 Maciej W. Rozycki <macro@mips.com>
111 * mips-dis.c (mips_option_arg_t): New enumeration.
112 (mips_options): New variable.
113 (disassembler_options_mips): New function.
114 (print_mips_disassembler_options): Reimplement in terms of
115 `disassembler_options_mips'.
116 * arm-dis.c (disassembler_options_arm): Adapt to using the
117 `disasm_options_and_args_t' structure.
118 * ppc-dis.c (disassembler_options_powerpc): Likewise.
119 * s390-dis.c (disassembler_options_s390): Likewise.
121 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
123 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
125 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
126 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
127 * testsuite/ld-arm/tls-longplt.d: Likewise.
129 2018-06-29 Tamar Christina <tamar.christina@arm.com>
132 * aarch64-asm-2.c: Regenerate.
133 * aarch64-dis-2.c: Likewise.
134 * aarch64-opc-2.c: Likewise.
135 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
136 * aarch64-opc.c (operand_general_constraint_met_p,
137 aarch64_print_operand): Likewise.
138 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
139 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
141 (AARCH64_OPERANDS): Add Em2.
143 2018-06-26 Nick Clifton <nickc@redhat.com>
145 * po/uk.po: Updated Ukranian translation.
146 * po/de.po: Updated German translation.
147 * po/pt_BR.po: Updated Brazilian Portuguese translation.
149 2018-06-26 Nick Clifton <nickc@redhat.com>
151 * nfp-dis.c: Fix spelling mistake.
153 2018-06-24 Nick Clifton <nickc@redhat.com>
155 * configure: Regenerate.
156 * po/opcodes.pot: Regenerate.
158 2018-06-24 Nick Clifton <nickc@redhat.com>
162 2018-06-19 Tamar Christina <tamar.christina@arm.com>
164 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
165 * aarch64-asm-2.c: Regenerate.
166 * aarch64-dis-2.c: Likewise.
168 2018-06-21 Maciej W. Rozycki <macro@mips.com>
170 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
171 `-M ginv' option description.
173 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
176 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
179 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
181 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
182 * configure.ac: Remove AC_PREREQ.
183 * Makefile.in: Re-generate.
184 * aclocal.m4: Re-generate.
185 * configure: Re-generate.
187 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
189 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
190 mips64r6 descriptors.
191 (parse_mips_ase_option): Handle -Mginv option.
192 (print_mips_disassembler_options): Document -Mginv.
193 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
195 (mips_opcodes): Define ginvi and ginvt.
197 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
198 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
200 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
201 * mips-opc.c (CRC, CRC64): New macros.
202 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
203 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
206 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
209 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
210 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
212 2018-06-06 Alan Modra <amodra@gmail.com>
214 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
215 setjmp. Move init for some other vars later too.
217 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
219 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
220 (dis_private): Add new fields for property section tracking.
221 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
222 (xtensa_instruction_fits): New functions.
223 (fetch_data): Bump minimal fetch size to 4.
224 (print_insn_xtensa): Make struct dis_private static.
225 Load and prepare property table on section change.
226 Don't disassemble literals. Don't disassemble instructions that
227 cross property table boundaries.
229 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
231 * configure: Regenerated.
233 2018-06-01 Jan Beulich <jbeulich@suse.com>
235 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
236 * i386-tbl.h: Re-generate.
238 2018-06-01 Jan Beulich <jbeulich@suse.com>
240 * i386-opc.tbl (sldt, str): Add NoRex64.
241 * i386-tbl.h: Re-generate.
243 2018-06-01 Jan Beulich <jbeulich@suse.com>
245 * i386-opc.tbl (invpcid): Add Oword.
246 * i386-tbl.h: Re-generate.
248 2018-06-01 Alan Modra <amodra@gmail.com>
250 * sysdep.h (_bfd_error_handler): Don't declare.
251 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
252 * rl78-decode.opc: Likewise.
253 * msp430-decode.c: Regenerate.
254 * rl78-decode.c: Regenerate.
256 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
258 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
259 * i386-init.h : Regenerated.
261 2018-05-25 Alan Modra <amodra@gmail.com>
263 * Makefile.in: Regenerate.
264 * po/POTFILES.in: Regenerate.
266 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
268 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
269 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
270 (insert_bab, extract_bab, insert_btab, extract_btab,
271 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
272 (BAT, BBA VBA RBS XB6S): Delete macros.
273 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
274 (BB, BD, RBX, XC6): Update for new macros.
275 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
276 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
277 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
278 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
280 2018-05-18 John Darrington <john@darrington.wattle.id.au>
282 * Makefile.am: Add support for s12z architecture.
283 * configure.ac: Likewise.
284 * disassemble.c: Likewise.
285 * disassemble.h: Likewise.
286 * Makefile.in: Regenerate.
287 * configure: Regenerate.
288 * s12z-dis.c: New file.
291 2018-05-18 Alan Modra <amodra@gmail.com>
293 * nfp-dis.c: Don't #include libbfd.h.
294 (init_nfp3200_priv): Use bfd_get_section_contents.
295 (nit_nfp6000_mecsr_sec): Likewise.
297 2018-05-17 Nick Clifton <nickc@redhat.com>
299 * po/zh_CN.po: Updated simplified Chinese translation.
301 2018-05-16 Tamar Christina <tamar.christina@arm.com>
304 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
305 * aarch64-dis-2.c: Regenerate.
307 2018-05-15 Tamar Christina <tamar.christina@arm.com>
310 * aarch64-asm.c (opintl.h): Include.
311 (aarch64_ins_sysreg): Enforce read/write constraints.
312 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
313 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
314 (F_REG_READ, F_REG_WRITE): New.
315 * aarch64-opc.c (aarch64_print_operand): Generate notes for
317 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
318 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
319 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
320 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
321 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
322 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
323 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
324 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
325 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
326 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
327 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
328 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
329 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
330 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
331 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
332 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
333 msr (F_SYS_WRITE), mrs (F_SYS_READ).
335 2018-05-15 Tamar Christina <tamar.christina@arm.com>
338 * aarch64-dis.c (no_notes: New.
339 (parse_aarch64_dis_option): Support notes.
340 (aarch64_decode_insn, print_operands): Likewise.
341 (print_aarch64_disassembler_options): Document notes.
342 * aarch64-opc.c (aarch64_print_operand): Support notes.
344 2018-05-15 Tamar Christina <tamar.christina@arm.com>
347 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
348 and take error struct.
349 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
350 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
351 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
352 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
353 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
354 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
355 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
356 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
357 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
358 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
359 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
360 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
361 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
362 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
363 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
364 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
365 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
366 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
367 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
368 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
369 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
370 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
371 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
372 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
373 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
374 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
375 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
376 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
377 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
378 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
379 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
380 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
381 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
382 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
383 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
384 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
385 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
386 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
387 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
388 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
389 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
390 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
391 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
392 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
393 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
394 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
395 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
396 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
397 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
398 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
399 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
400 (determine_disassembling_preference, aarch64_decode_insn,
401 print_insn_aarch64_word, print_insn_data): Take errors struct.
402 (print_insn_aarch64): Use errors.
403 * aarch64-asm-2.c: Regenerate.
404 * aarch64-dis-2.c: Regenerate.
405 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
406 boolean in aarch64_insert_operan.
407 (print_operand_extractor): Likewise.
408 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
410 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
412 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
414 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
416 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
418 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
420 * cr16-opc.c (cr16_instruction): Comment typo fix.
421 * hppa-dis.c (print_insn_hppa): Likewise.
423 2018-05-08 Jim Wilson <jimw@sifive.com>
425 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
426 (match_c_slli64, match_srxi_as_c_srxi): New.
427 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
428 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
429 <c.slli, c.srli, c.srai>: Use match_s_slli.
430 <c.slli64, c.srli64, c.srai64>: New.
432 2018-05-08 Alan Modra <amodra@gmail.com>
434 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
435 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
436 partition opcode space for index lookup.
438 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
440 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
441 <insn_length>: ...with this. Update usage.
442 Remove duplicate call to *info->memory_error_func.
444 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
445 H.J. Lu <hongjiu.lu@intel.com>
447 * i386-dis.c (Gva): New.
448 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
449 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
450 (prefix_table): New instructions (see prefix above).
451 (mod_table): New instructions (see prefix above).
452 (OP_G): Handle va_mode.
453 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
455 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
456 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
457 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
458 * i386-opc.tbl: Add movidir{i,64b}.
459 * i386-init.h: Regenerated.
460 * i386-tbl.h: Likewise.
462 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
464 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
466 * i386-opc.h (AddrPrefixOp0): Renamed to ...
467 (AddrPrefixOpReg): This.
468 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
469 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
471 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
473 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
474 (vle_num_opcodes): Likewise.
475 (spe2_num_opcodes): Likewise.
476 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
478 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
479 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
482 2018-05-01 Tamar Christina <tamar.christina@arm.com>
484 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
486 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
488 Makefile.am: Added nfp-dis.c.
489 configure.ac: Added bfd_nfp_arch.
490 disassemble.h: Added print_insn_nfp prototype.
491 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
492 nfp-dis.c: New, for NFP support.
493 po/POTFILES.in: Added nfp-dis.c to the list.
494 Makefile.in: Regenerate.
495 configure: Regenerate.
497 2018-04-26 Jan Beulich <jbeulich@suse.com>
499 * i386-opc.tbl: Fold various non-memory operand AVX512VL
500 templates into their base ones.
501 * i386-tlb.h: Re-generate.
503 2018-04-26 Jan Beulich <jbeulich@suse.com>
505 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
506 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
507 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
508 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
509 * i386-init.h: Re-generate.
511 2018-04-26 Jan Beulich <jbeulich@suse.com>
513 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
514 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
515 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
516 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
518 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
520 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
522 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
523 cpuregzmm, and cpuregmask.
524 * i386-init.h: Re-generate.
525 * i386-tbl.h: Re-generate.
527 2018-04-26 Jan Beulich <jbeulich@suse.com>
529 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
530 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
531 * i386-init.h: Re-generate.
533 2018-04-26 Jan Beulich <jbeulich@suse.com>
535 * i386-gen.c (VexImmExt): Delete.
536 * i386-opc.h (VexImmExt, veximmext): Delete.
537 * i386-opc.tbl: Drop all VexImmExt uses.
538 * i386-tlb.h: Re-generate.
540 2018-04-25 Jan Beulich <jbeulich@suse.com>
542 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
544 * i386-tlb.h: Re-generate.
546 2018-04-25 Tamar Christina <tamar.christina@arm.com>
548 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
550 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
552 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
554 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
555 (cpu_flags): Add CpuCLDEMOTE.
556 * i386-init.h: Regenerate.
557 * i386-opc.h (enum): Add CpuCLDEMOTE,
558 (i386_cpu_flags): Add cpucldemote.
559 * i386-opc.tbl: Add cldemote.
560 * i386-tbl.h: Regenerate.
562 2018-04-16 Alan Modra <amodra@gmail.com>
564 * Makefile.am: Remove sh5 and sh64 support.
565 * configure.ac: Likewise.
566 * disassemble.c: Likewise.
567 * disassemble.h: Likewise.
568 * sh-dis.c: Likewise.
569 * sh64-dis.c: Delete.
570 * sh64-opc.c: Delete.
571 * sh64-opc.h: Delete.
572 * Makefile.in: Regenerate.
573 * configure: Regenerate.
574 * po/POTFILES.in: Regenerate.
576 2018-04-16 Alan Modra <amodra@gmail.com>
578 * Makefile.am: Remove w65 support.
579 * configure.ac: Likewise.
580 * disassemble.c: Likewise.
581 * disassemble.h: Likewise.
584 * Makefile.in: Regenerate.
585 * configure: Regenerate.
586 * po/POTFILES.in: Regenerate.
588 2018-04-16 Alan Modra <amodra@gmail.com>
590 * configure.ac: Remove we32k support.
591 * configure: Regenerate.
593 2018-04-16 Alan Modra <amodra@gmail.com>
595 * Makefile.am: Remove m88k support.
596 * configure.ac: Likewise.
597 * disassemble.c: Likewise.
598 * disassemble.h: Likewise.
599 * m88k-dis.c: Delete.
600 * Makefile.in: Regenerate.
601 * configure: Regenerate.
602 * po/POTFILES.in: Regenerate.
604 2018-04-16 Alan Modra <amodra@gmail.com>
606 * Makefile.am: Remove i370 support.
607 * configure.ac: Likewise.
608 * disassemble.c: Likewise.
609 * disassemble.h: Likewise.
610 * i370-dis.c: Delete.
611 * i370-opc.c: Delete.
612 * Makefile.in: Regenerate.
613 * configure: Regenerate.
614 * po/POTFILES.in: Regenerate.
616 2018-04-16 Alan Modra <amodra@gmail.com>
618 * Makefile.am: Remove h8500 support.
619 * configure.ac: Likewise.
620 * disassemble.c: Likewise.
621 * disassemble.h: Likewise.
622 * h8500-dis.c: Delete.
623 * h8500-opc.h: Delete.
624 * Makefile.in: Regenerate.
625 * configure: Regenerate.
626 * po/POTFILES.in: Regenerate.
628 2018-04-16 Alan Modra <amodra@gmail.com>
630 * configure.ac: Remove tahoe support.
631 * configure: Regenerate.
633 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
635 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
637 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
639 * i386-tbl.h: Regenerated.
641 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
643 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
644 PREFIX_MOD_1_0FAE_REG_6.
646 (OP_E_register): Use va_mode.
647 * i386-dis-evex.h (prefix_table):
648 New instructions (see prefixes above).
649 * i386-gen.c (cpu_flag_init): Add WAITPKG.
650 (cpu_flags): Likewise.
651 * i386-opc.h (enum): Likewise.
652 (i386_cpu_flags): Likewise.
653 * i386-opc.tbl: Add umonitor, umwait, tpause.
654 * i386-init.h: Regenerate.
655 * i386-tbl.h: Likewise.
657 2018-04-11 Alan Modra <amodra@gmail.com>
659 * opcodes/i860-dis.c: Delete.
660 * opcodes/i960-dis.c: Delete.
661 * Makefile.am: Remove i860 and i960 support.
662 * configure.ac: Likewise.
663 * disassemble.c: Likewise.
664 * disassemble.h: Likewise.
665 * Makefile.in: Regenerate.
666 * configure: Regenerate.
667 * po/POTFILES.in: Regenerate.
669 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
672 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
674 (print_insn): Clear vex instead of vex.evex.
676 2018-04-04 Nick Clifton <nickc@redhat.com>
678 * po/es.po: Updated Spanish translation.
680 2018-03-28 Jan Beulich <jbeulich@suse.com>
682 * i386-gen.c (opcode_modifiers): Delete VecESize.
683 * i386-opc.h (VecESize): Delete.
684 (struct i386_opcode_modifier): Delete vecesize.
685 * i386-opc.tbl: Drop VecESize.
686 * i386-tlb.h: Re-generate.
688 2018-03-28 Jan Beulich <jbeulich@suse.com>
690 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
691 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
692 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
693 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
694 * i386-tlb.h: Re-generate.
696 2018-03-28 Jan Beulich <jbeulich@suse.com>
698 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
700 * i386-tlb.h: Re-generate.
702 2018-03-28 Jan Beulich <jbeulich@suse.com>
704 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
705 (vex_len_table): Drop Y for vcvt*2si.
706 (putop): Replace plain 'Y' handling by abort().
708 2018-03-28 Nick Clifton <nickc@redhat.com>
711 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
712 instructions with only a base address register.
713 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
714 handle AARHC64_OPND_SVE_ADDR_R.
715 (aarch64_print_operand): Likewise.
716 * aarch64-asm-2.c: Regenerate.
717 * aarch64_dis-2.c: Regenerate.
718 * aarch64-opc-2.c: Regenerate.
720 2018-03-22 Jan Beulich <jbeulich@suse.com>
722 * i386-opc.tbl: Drop VecESize from register only insn forms and
723 memory forms not allowing broadcast.
724 * i386-tlb.h: Re-generate.
726 2018-03-22 Jan Beulich <jbeulich@suse.com>
728 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
729 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
730 sha256*): Drop Disp<N>.
732 2018-03-22 Jan Beulich <jbeulich@suse.com>
734 * i386-dis.c (EbndS, bnd_swap_mode): New.
735 (prefix_table): Use EbndS.
736 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
737 * i386-opc.tbl (bndmov): Move misplaced Load.
738 * i386-tlb.h: Re-generate.
740 2018-03-22 Jan Beulich <jbeulich@suse.com>
742 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
743 templates allowing memory operands and folded ones for register
745 * i386-tlb.h: Re-generate.
747 2018-03-22 Jan Beulich <jbeulich@suse.com>
749 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
750 256-bit templates. Drop redundant leftover Disp<N>.
751 * i386-tlb.h: Re-generate.
753 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
755 * riscv-opc.c (riscv_insn_types): New.
757 2018-03-13 Nick Clifton <nickc@redhat.com>
759 * po/pt_BR.po: Updated Brazilian Portuguese translation.
761 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
763 * i386-opc.tbl: Add Optimize to clr.
764 * i386-tbl.h: Regenerated.
766 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
768 * i386-gen.c (opcode_modifiers): Remove OldGcc.
769 * i386-opc.h (OldGcc): Removed.
770 (i386_opcode_modifier): Remove oldgcc.
771 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
772 instructions for old (<= 2.8.1) versions of gcc.
773 * i386-tbl.h: Regenerated.
775 2018-03-08 Jan Beulich <jbeulich@suse.com>
777 * i386-opc.h (EVEXDYN): New.
778 * i386-opc.tbl: Fold various AVX512VL templates.
779 * i386-tlb.h: Re-generate.
781 2018-03-08 Jan Beulich <jbeulich@suse.com>
783 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
784 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
785 vpexpandd, vpexpandq): Fold AFX512VF templates.
786 * i386-tlb.h: Re-generate.
788 2018-03-08 Jan Beulich <jbeulich@suse.com>
790 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
791 Fold 128- and 256-bit VEX-encoded templates.
792 * i386-tlb.h: Re-generate.
794 2018-03-08 Jan Beulich <jbeulich@suse.com>
796 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
797 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
798 vpexpandd, vpexpandq): Fold AVX512F templates.
799 * i386-tlb.h: Re-generate.
801 2018-03-08 Jan Beulich <jbeulich@suse.com>
803 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
804 64-bit templates. Drop Disp<N>.
805 * i386-tlb.h: Re-generate.
807 2018-03-08 Jan Beulich <jbeulich@suse.com>
809 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
810 and 256-bit templates.
811 * i386-tlb.h: Re-generate.
813 2018-03-08 Jan Beulich <jbeulich@suse.com>
815 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
816 * i386-tlb.h: Re-generate.
818 2018-03-08 Jan Beulich <jbeulich@suse.com>
820 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
822 * i386-tlb.h: Re-generate.
824 2018-03-08 Jan Beulich <jbeulich@suse.com>
826 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
827 * i386-tlb.h: Re-generate.
829 2018-03-08 Jan Beulich <jbeulich@suse.com>
831 * i386-gen.c (opcode_modifiers): Delete FloatD.
832 * i386-opc.h (FloatD): Delete.
833 (struct i386_opcode_modifier): Delete floatd.
834 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
836 * i386-tlb.h: Re-generate.
838 2018-03-08 Jan Beulich <jbeulich@suse.com>
840 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
842 2018-03-08 Jan Beulich <jbeulich@suse.com>
844 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
845 * i386-tlb.h: Re-generate.
847 2018-03-08 Jan Beulich <jbeulich@suse.com>
849 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
851 * i386-tlb.h: Re-generate.
853 2018-03-07 Alan Modra <amodra@gmail.com>
855 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
857 * disassemble.h (print_insn_rs6000): Delete.
858 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
859 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
860 (print_insn_rs6000): Delete.
862 2018-03-03 Alan Modra <amodra@gmail.com>
864 * sysdep.h (opcodes_error_handler): Define.
865 (_bfd_error_handler): Declare.
866 * Makefile.am: Remove stray #.
867 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
869 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
870 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
871 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
872 opcodes_error_handler to print errors. Standardize error messages.
873 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
874 and include opintl.h.
875 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
876 * i386-gen.c: Standardize error messages.
877 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
878 * Makefile.in: Regenerate.
879 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
880 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
881 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
882 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
883 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
884 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
885 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
886 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
887 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
888 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
889 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
890 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
891 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
893 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
895 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
896 vpsub[bwdq] instructions.
897 * i386-tbl.h: Regenerated.
899 2018-03-01 Alan Modra <amodra@gmail.com>
901 * configure.ac (ALL_LINGUAS): Sort.
902 * configure: Regenerate.
904 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
906 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
907 macro by assignements.
909 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
912 * i386-gen.c (opcode_modifiers): Add Optimize.
913 * i386-opc.h (Optimize): New enum.
914 (i386_opcode_modifier): Add optimize.
915 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
916 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
917 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
918 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
919 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
921 * i386-tbl.h: Regenerated.
923 2018-02-26 Alan Modra <amodra@gmail.com>
925 * crx-dis.c (getregliststring): Allocate a large enough buffer
926 to silence false positive gcc8 warning.
928 2018-02-22 Shea Levy <shea@shealevy.com>
930 * disassemble.c (ARCH_riscv): Define if ARCH_all.
932 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
934 * i386-opc.tbl: Add {rex},
935 * i386-tbl.h: Regenerated.
937 2018-02-20 Maciej W. Rozycki <macro@mips.com>
939 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
940 (mips16_opcodes): Replace `M' with `m' for "restore".
942 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
944 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
946 2018-02-13 Maciej W. Rozycki <macro@mips.com>
948 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
949 variable to `function_index'.
951 2018-02-13 Nick Clifton <nickc@redhat.com>
954 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
955 about truncation of printing.
957 2018-02-12 Henry Wong <henry@stuffedcow.net>
959 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
961 2018-02-05 Nick Clifton <nickc@redhat.com>
963 * po/pt_BR.po: Updated Brazilian Portuguese translation.
965 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
967 * i386-dis.c (enum): Add pconfig.
968 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
969 (cpu_flags): Add CpuPCONFIG.
970 * i386-opc.h (enum): Add CpuPCONFIG.
971 (i386_cpu_flags): Add cpupconfig.
972 * i386-opc.tbl: Add PCONFIG instruction.
973 * i386-init.h: Regenerate.
974 * i386-tbl.h: Likewise.
976 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
978 * i386-dis.c (enum): Add PREFIX_0F09.
979 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
980 (cpu_flags): Add CpuWBNOINVD.
981 * i386-opc.h (enum): Add CpuWBNOINVD.
982 (i386_cpu_flags): Add cpuwbnoinvd.
983 * i386-opc.tbl: Add WBNOINVD instruction.
984 * i386-init.h: Regenerate.
985 * i386-tbl.h: Likewise.
987 2018-01-17 Jim Wilson <jimw@sifive.com>
989 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
991 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
993 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
994 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
995 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
996 (cpu_flags): Add CpuIBT, CpuSHSTK.
997 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
998 (i386_cpu_flags): Add cpuibt, cpushstk.
999 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1000 * i386-init.h: Regenerate.
1001 * i386-tbl.h: Likewise.
1003 2018-01-16 Nick Clifton <nickc@redhat.com>
1005 * po/pt_BR.po: Updated Brazilian Portugese translation.
1006 * po/de.po: Updated German translation.
1008 2018-01-15 Jim Wilson <jimw@sifive.com>
1010 * riscv-opc.c (match_c_nop): New.
1011 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1013 2018-01-15 Nick Clifton <nickc@redhat.com>
1015 * po/uk.po: Updated Ukranian translation.
1017 2018-01-13 Nick Clifton <nickc@redhat.com>
1019 * po/opcodes.pot: Regenerated.
1021 2018-01-13 Nick Clifton <nickc@redhat.com>
1023 * configure: Regenerate.
1025 2018-01-13 Nick Clifton <nickc@redhat.com>
1027 2.30 branch created.
1029 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1031 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1032 * i386-tbl.h: Regenerate.
1034 2018-01-10 Jan Beulich <jbeulich@suse.com>
1036 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1037 * i386-tbl.h: Re-generate.
1039 2018-01-10 Jan Beulich <jbeulich@suse.com>
1041 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1042 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1043 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1044 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1045 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1046 Disp8MemShift of AVX512VL forms.
1047 * i386-tbl.h: Re-generate.
1049 2018-01-09 Jim Wilson <jimw@sifive.com>
1051 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1052 then the hi_addr value is zero.
1054 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1056 * arm-dis.c (arm_opcodes): Add csdb.
1057 (thumb32_opcodes): Add csdb.
1059 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1061 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1062 * aarch64-asm-2.c: Regenerate.
1063 * aarch64-dis-2.c: Regenerate.
1064 * aarch64-opc-2.c: Regenerate.
1066 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1069 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1070 Remove AVX512 vmovd with 64-bit operands.
1071 * i386-tbl.h: Regenerated.
1073 2018-01-05 Jim Wilson <jimw@sifive.com>
1075 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1078 2018-01-03 Alan Modra <amodra@gmail.com>
1080 Update year range in copyright notice of all files.
1082 2018-01-02 Jan Beulich <jbeulich@suse.com>
1084 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1085 and OPERAND_TYPE_REGZMM entries.
1087 For older changes see ChangeLog-2017
1089 Copyright (C) 2018 Free Software Foundation, Inc.
1091 Copying and distribution of this file, with or without modification,
1092 are permitted in any medium without royalty provided the copyright
1093 notice and this notice are preserved.
1099 version-control: never