1 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
3 * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
4 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. Use new
5 MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers. Add
6 size and format initializers. Merge 'b' arguments into 'j'.
7 (NIOS2_NUM_OPCODES): Adjust definition.
8 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
9 (nios2_opcodes): Adjust.
10 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
11 * nios2-dis.c (INSNLEN): Update comment.
12 (nios2_hash_init, nios2_hash): Delete.
13 (OPCODE_HASH_SIZE): New.
14 (nios2_r1_extract_opcode): New.
15 (nios2_disassembler_state): New.
16 (nios2_r1_disassembler_state): New.
17 (nios2_init_opcode_hash): Add state parameter. Adjust to use it.
18 (nios2_find_opcode_hash): Use state object.
20 (nios2_print_insn_arg): Add op parameter. Use it to access
21 format. Remove 'b' case.
22 (nios2_disassemble): Remove special case for nop. Remove
23 hard-coded instruction size.
25 2014-10-21 Jan Beulich <jbeulich@suse.com>
27 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
29 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
31 * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
33 Annotate several instructions with the HWCAP2_VIS3B hwcap.
35 2014-10-15 Tristan Gingold <gingold@adacore.com>
37 * configure: Regenerate.
39 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
41 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
42 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
43 Annotate table with HWCAP2 bits.
44 Add instructions xmontmul, xmontsqr, xmpmul.
45 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
46 r,i,%mwait' and `rd %mwait,r' instructions.
47 Add rd/wr instructions for accessing the %mcdper ancillary state
49 (sparc-opcodes): Add sparc5/vis4.0 instructions:
50 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
51 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
52 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
53 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
54 fpsubus16, and faligndatai.
55 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
56 ancillary state register to the table.
57 (print_insn_sparc): Handle the %mcdper ancillary state register.
58 (print_insn_sparc): Handle new operand type '}'.
60 2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
62 * i386-dis.c (MOD_0F20): Removed.
66 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
68 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
69 (OP_R): Check mod/rm byte and call OP_E_register.
71 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
73 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
74 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
75 keyword_aridxi): Add audio ISA extension.
76 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
77 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
78 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
79 for nds32-dis.c using.
80 (build_opcode_syntax): Remove dead code.
81 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
82 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
83 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
85 * nds32-asm.h: Declare.
86 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
89 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
90 Matthew Fortune <matthew.fortune@imgtec.com>
92 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
94 (parse_mips_dis_option): Allow MSA and virtualization support for
96 (mips_print_arg_state): Add fields dest_regno and seen_dest.
97 (mips_seen_register): New function.
98 (print_insn_arg): Refactored code to use mips_seen_register
99 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
100 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
101 the register rather than aborting.
102 (print_insn_args): Add length argument. Add code to correctly
103 calculate the instruction address for pc relative instructions.
104 (validate_insn_args): New static function.
105 (print_insn_mips): Prevent jalx disassembling for r6. Use
107 (print_insn_micromips): Use validate_insn_args.
108 all the arguments are valid.
109 * mips-formats.h (PREV_CHECK): New define.
110 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
111 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
116 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
117 MIPS R6 instructions from MIPS R2 instructions.
119 2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
121 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
122 (putop): Handle "%LP".
124 2014-09-03 Jiong Wang <jiong.wang@arm.com>
126 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
127 * aarch64-dis-2.c: Update auto-generated file.
129 2014-09-03 Jiong Wang <jiong.wang@arm.com>
131 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
132 (aarch64_feature_lse): New feature added.
134 (aarch64_opcode_table): New LSE instructions added. Improve
135 descriptions for ldarb/ldarh/ldar.
136 (aarch64_opcode_table): Describe PAIRREG.
137 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
138 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
139 (aarch64_print_operand): Recognize PAIRREG.
140 (operand_general_constraint_met_p): Check reg pair constraints for CASP
142 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
143 (do_special_decoding): Recognize F_LSE_SZ.
144 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
146 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
148 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
149 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
150 "sdbbp", "syscall" and "wait".
152 2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
153 Maciej W. Rozycki <macro@codesourcery.com>
155 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
156 returned if the U bit is set.
158 2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
160 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
161 48-bit "li" encoding.
163 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
165 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
166 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
167 static functions, code was moved from...
168 (print_insn_s390): ...here.
169 (s390_extract_operand): Adjust comment. Change type of first
170 parameter from 'unsigned char *' to 'const bfd_byte *'.
171 (union operand_value): New.
172 (s390_extract_operand): Change return type to union operand_value.
173 Also avoid integer overflow in sign-extension.
174 (s390_print_insn_with_opcode): Adjust to changed return value from
175 s390_extract_operand(). Change "%i" printf format to "%u" for
177 (init_disasm): Simplify initialization of opc_index[]. This also
178 fixes an access after the last element of s390_opcodes[].
179 (print_insn_s390): Simplify the opcode search loop.
180 Check architecture mask against all searched opcodes, not just the
182 (s390_print_insn_with_opcode): Drop function pointer dereferences
184 (print_insn_s390): Likewise.
185 (s390_insn_length): Simplify formula for return value.
186 (s390_print_insn_with_opcode): Avoid special handling for the
187 separator before the first operand. Use new local variable
188 'flags' in place of 'operand->flags'.
190 2014-08-14 Mike Frysinger <vapier@gentoo.org>
192 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
193 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
194 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
195 Change assignment of 1 to priv->comment to TRUE.
196 (print_insn_bfin): Change legal to a bfd_boolean. Change
197 assignment of 0/1 with priv comment and parallel and legal
200 2014-08-14 Mike Frysinger <vapier@gentoo.org>
202 * bfin-dis.c (OUT): Define.
203 (decode_CC2stat_0): Declare new op_names array.
204 Replace multiple if statements with a single one.
206 2014-08-14 Mike Frysinger <vapier@gentoo.org>
208 * bfin-dis.c (struct private): Add iw0.
209 (_print_insn_bfin): Assign iw0 to priv.iw0.
210 (print_insn_bfin): Drop ifetch and use priv.iw0.
212 2014-08-13 Mike Frysinger <vapier@gentoo.org>
214 * bfin-dis.c (comment, parallel): Move from global scope ...
215 (struct private): ... to this new struct.
216 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
217 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
218 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
219 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
220 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
221 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
222 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
223 print_insn_bfin): Declare private struct. Use priv's comment and
226 2014-08-13 Mike Frysinger <vapier@gentoo.org>
228 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
229 (_print_insn_bfin): Add check for unaligned pc.
231 2014-08-13 Mike Frysinger <vapier@gentoo.org>
233 * bfin-dis.c (ifetch): New function.
234 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
237 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
239 * micromips-opc.c (COD): Rename throughout to...
240 (CM): New define, update to use INSN_COPROC_MOVE.
241 (LCD): Rename throughout to...
242 (LC): New define, update to use INSN_LOAD_COPROC.
243 * mips-opc.c: Likewise.
245 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
247 * micromips-opc.c (COD, LCD) New macros.
248 (cfc1, ctc1): Remove FP_S attribute.
249 (dmfc1, mfc1, mfhc1): Add LCD attribute.
250 (dmtc1, mtc1, mthc1): Add COD attribute.
251 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
253 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
254 Alexander Ivchenko <alexander.ivchenko@intel.com>
255 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
256 Sergey Lega <sergey.s.lega@intel.com>
257 Anna Tikhonova <anna.tikhonova@intel.com>
258 Ilya Tocar <ilya.tocar@intel.com>
259 Andrey Turetskiy <andrey.turetskiy@intel.com>
260 Ilya Verbin <ilya.verbin@intel.com>
261 Kirill Yukhin <kirill.yukhin@intel.com>
262 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
264 * i386-dis-evex.h: Updated.
265 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
266 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
267 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
268 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
270 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
271 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
272 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
273 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
274 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
275 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
276 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
277 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
278 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
279 (prefix_table): Add entries for new instructions.
280 (vex_len_table): Ditto.
281 (vex_w_table): Ditto.
282 (OP_E_memory): Update xmmq_mode handling.
283 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
284 (cpu_flags): Add CpuAVX512DQ.
285 * i386-init.h: Regenerared.
286 * i386-opc.h (CpuAVX512DQ): New.
287 (i386_cpu_flags): Add cpuavx512dq.
288 * i386-opc.tbl: Add AVX512DQ instructions.
289 * i386-tbl.h: Regenerate.
291 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
292 Alexander Ivchenko <alexander.ivchenko@intel.com>
293 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
294 Sergey Lega <sergey.s.lega@intel.com>
295 Anna Tikhonova <anna.tikhonova@intel.com>
296 Ilya Tocar <ilya.tocar@intel.com>
297 Andrey Turetskiy <andrey.turetskiy@intel.com>
298 Ilya Verbin <ilya.verbin@intel.com>
299 Kirill Yukhin <kirill.yukhin@intel.com>
300 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
302 * i386-dis-evex.h: Add new instructions (prefixes bellow).
303 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
304 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
305 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
306 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
307 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
308 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
309 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
310 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
311 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
312 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
313 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
314 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
315 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
316 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
317 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
318 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
319 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
320 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
321 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
322 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
323 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
324 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
325 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
326 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
327 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
328 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
329 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
330 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
331 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
332 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
333 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
334 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
335 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
336 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
337 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
338 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
339 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
340 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
341 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
342 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
343 (prefix_table): Add entries for new instructions.
345 (vex_len_table): Ditto.
346 (vex_w_table): Ditto.
347 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
348 mask_bd_mode handling.
349 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
351 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
353 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
354 (OP_EX): Add dqw_swap_mode handling.
355 (OP_VEX): Add mask_bd_mode handling.
356 (OP_Mask): Add mask_bd_mode handling.
357 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
358 (cpu_flags): Add CpuAVX512BW.
359 * i386-init.h: Regenerated.
360 * i386-opc.h (CpuAVX512BW): New.
361 (i386_cpu_flags): Add cpuavx512bw.
362 * i386-opc.tbl: Add AVX512BW instructions.
363 * i386-tbl.h: Regenerate.
365 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
366 Alexander Ivchenko <alexander.ivchenko@intel.com>
367 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
368 Sergey Lega <sergey.s.lega@intel.com>
369 Anna Tikhonova <anna.tikhonova@intel.com>
370 Ilya Tocar <ilya.tocar@intel.com>
371 Andrey Turetskiy <andrey.turetskiy@intel.com>
372 Ilya Verbin <ilya.verbin@intel.com>
373 Kirill Yukhin <kirill.yukhin@intel.com>
374 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
376 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
377 * i386-tbl.h: Regenerate.
379 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
380 Alexander Ivchenko <alexander.ivchenko@intel.com>
381 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
382 Sergey Lega <sergey.s.lega@intel.com>
383 Anna Tikhonova <anna.tikhonova@intel.com>
384 Ilya Tocar <ilya.tocar@intel.com>
385 Andrey Turetskiy <andrey.turetskiy@intel.com>
386 Ilya Verbin <ilya.verbin@intel.com>
387 Kirill Yukhin <kirill.yukhin@intel.com>
388 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
390 * i386-dis.c (intel_operand_size): Support 128/256 length in
391 vex_vsib_q_w_dq_mode.
392 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
393 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
394 (cpu_flags): Add CpuAVX512VL.
395 * i386-init.h: Regenerated.
396 * i386-opc.h (CpuAVX512VL): New.
397 (i386_cpu_flags): Add cpuavx512vl.
398 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
399 * i386-opc.tbl: Add AVX512VL instructions.
400 * i386-tbl.h: Regenerate.
402 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
404 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
405 * or1k-opinst.c: Regenerate.
407 2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
409 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
410 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
412 2014-07-04 Alan Modra <amodra@gmail.com>
414 * configure.ac: Rename from configure.in.
415 * Makefile.in: Regenerate.
416 * config.in: Regenerate.
418 2014-07-04 Alan Modra <amodra@gmail.com>
420 * configure.in: Include bfd/version.m4.
421 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
422 (BFD_VERSION): Delete.
423 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
424 * configure: Regenerate.
425 * Makefile.in: Regenerate.
427 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
428 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
429 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
430 Soundararajan <Sounderarajan.D@atmel.com>
432 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
433 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
434 machine is not avrtiny.
436 2014-06-26 Philippe De Muyter <phdm@macqel.be>
438 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
441 2014-06-12 Alan Modra <amodra@gmail.com>
443 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
444 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
446 2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
448 * i386-dis.c (fwait_prefix): New.
449 (ckprefix): Set fwait_prefix.
450 (print_insn): Properly print prefixes before fwait.
452 2014-06-07 Alan Modra <amodra@gmail.com>
454 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
456 2014-06-05 Joel Brobecker <brobecker@adacore.com>
458 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
459 bfd's development.sh.
460 * Makefile.in, configure: Regenerate.
462 2014-06-03 Nick Clifton <nickc@redhat.com>
464 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
465 decide when extended addressing is being used.
467 2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
469 * sparc-opc.c (cas): Disable for LEON.
472 2014-05-20 Alan Modra <amodra@gmail.com>
474 * m68k-dis.c: Don't include setjmp.h.
476 2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
478 * i386-dis.c (ADDR16_PREFIX): Removed.
479 (ADDR32_PREFIX): Likewise.
480 (DATA16_PREFIX): Likewise.
481 (DATA32_PREFIX): Likewise.
482 (prefix_name): Updated.
483 (print_insn): Simplify data and address size prefixes processing.
485 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
487 * or1k-desc.c: Regenerated.
488 * or1k-desc.h: Likewise.
489 * or1k-opc.c: Likewise.
490 * or1k-opc.h: Likewise.
491 * or1k-opinst.c: Likewise.
493 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
495 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
500 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
502 (parse_mips_dis_option): Update MSA and virtualization support to
503 allow mips64r3 and mips64r5.
505 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
507 * mips-opc.c (G3): Remove I4.
509 2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
512 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
513 (end_codep): Likewise.
514 (mandatory_prefix): Likewise.
515 (active_seg_prefix): Likewise.
516 (ckprefix): Set active_seg_prefix to the active segment register
518 (seg_prefix): Removed.
519 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
520 for prefix index. Ignore the index if it is invalid and the
521 mandatory prefix isn't required.
522 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
523 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
524 in used_prefixes here. Don't print unused prefixes. Check
525 active_seg_prefix for the active segment register prefix.
526 Restore the DFLAG bit in sizeflag if the data size prefix is
527 unused. Check the unused mandatory PREFIX_XXX prefixes
528 (append_seg): Only print the segment register which gets used.
529 (OP_E_memory): Check active_seg_prefix for the segment register
532 (OP_OFF64): Likewise.
533 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
535 2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
538 * config.in: Regenerated.
539 * configure: Likewise.
540 * configure.in: Check if sigsetjmp is available.
541 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
542 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
543 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
544 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
545 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
546 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
547 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
548 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
549 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
550 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
551 (OPCODES_SIGSETJMP): Likewise.
552 (OPCODES_SIGLONGJMP): Likewise.
553 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
554 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
555 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
556 * xtensa-dis.c (dis_private): Replace jmp_buf with
558 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
559 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
560 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
561 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
562 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
564 2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
567 * i386-dis.c (print_insn): Handle prefixes before fwait.
569 2014-04-26 Alan Modra <amodra@gmail.com>
571 * po/POTFILES.in: Regenerate.
573 2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
575 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
576 to allow the MIPS XPA ASE.
577 (parse_mips_dis_option): Process the -Mxpa option.
578 * mips-opc.c (XPA): New define.
579 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
580 locations of the ctc0 and cfc0 instructions.
582 2014-04-22 Christian Svensson <blue@cmd.nu>
584 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
585 * configure.in: Likewise.
586 * disassemble.c: Likewise.
587 * or1k-asm.c: New file.
588 * or1k-desc.c: New file.
589 * or1k-desc.h: New file.
590 * or1k-dis.c: New file.
591 * or1k-ibld.c: New file.
592 * or1k-opc.c: New file.
593 * or1k-opc.h: New file.
594 * or1k-opinst.c: New file.
595 * Makefile.in: Regenerate.
596 * configure: Regenerate.
597 * openrisc-asm.c: Delete.
598 * openrisc-desc.c: Delete.
599 * openrisc-desc.h: Delete.
600 * openrisc-dis.c: Delete.
601 * openrisc-ibld.c: Delete.
602 * openrisc-opc.c: Delete.
603 * openrisc-opc.h: Delete.
604 * or32-dis.c: Delete.
605 * or32-opc.c: Delete.
607 2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
609 * i386-dis.c (rm_table): Add encls, enclu.
610 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
611 (cpu_flags): Add CpuSE1.
612 * i386-opc.h (enum): Add CpuSE1.
613 (i386_cpu_flags): Add cpuse1.
614 * i386-opc.tbl: Add encls, enclu.
615 * i386-init.h: Regenerated.
616 * i386-tbl.h: Likewise.
618 2014-04-02 Anthony Green <green@moxielogic.com>
620 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
621 instructions, sex.b and sex.s.
623 2014-03-26 Jiong Wang <jiong.wang@arm.com>
625 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
628 2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
630 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
631 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
633 * i386-tbl.h: Regenerate.
635 2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
637 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
638 %hstick_enable added.
640 2014-03-19 Nick Clifton <nickc@redhat.com>
642 * rx-decode.opc (bwl): Allow for bogus instructions with a size
644 (sbwl, ubwl, SCALE): Likewise.
645 * rx-decode.c: Regenerate.
647 2014-03-12 Alan Modra <amodra@gmail.com>
649 * Makefile.in: Regenerate.
651 2014-03-05 Alan Modra <amodra@gmail.com>
653 Update copyright years.
655 2014-03-04 Heiher <r@hev.cc>
657 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
659 2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
661 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
662 so that they come after the Loongson extensions.
664 2014-03-03 Alan Modra <amodra@gmail.com>
666 * i386-gen.c (process_copyright): Emit copyright notice on one line.
668 2014-02-28 Alan Modra <amodra@gmail.com>
670 * msp430-decode.c: Regenerate.
672 2014-02-27 Jiong Wang <jiong.wang@arm.com>
674 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
675 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
677 2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
679 * aarch64-opc.c (print_register_offset_address): Call
680 get_int_reg_name to prepare the register name.
682 2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
684 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
685 * i386-tbl.h: Regenerate.
687 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
689 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
690 (cpu_flags): Add CpuPREFETCHWT1.
691 * i386-init.h: Regenerate.
692 * i386-opc.h (CpuPREFETCHWT1): New.
693 (i386_cpu_flags): Add cpuprefetchwt1.
694 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
695 * i386-tbl.h: Regenerate.
697 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
699 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
701 * i386-tbl.h: Regenerate.
703 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
705 * i386-gen.c (output_cpu_flags): Don't output trailing space.
706 (output_opcode_modifier): Likewise.
707 (output_operand_type): Likewise.
708 * i386-init.h: Regenerated.
709 * i386-tbl.h: Likewise.
711 2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
713 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
715 (PREFIX enum): Add PREFIX_0FAE_REG_7.
716 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
717 (prefix_table): Add clflusopt.
718 (mod_table): Add xrstors, xsavec, xsaves.
719 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
720 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
721 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
722 * i386-init.h: Regenerate.
723 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
724 xsaves64, xsavec, xsavec64.
725 * i386-tbl.h: Regenerate.
727 2014-02-10 Alan Modra <amodra@gmail.com>
729 * po/POTFILES.in: Regenerate.
730 * po/opcodes.pot: Regenerate.
732 2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
733 Jan Beulich <jbeulich@suse.com>
736 * i386-dis.c (OP_E_memory): Fix shift computation for
737 vex_vsib_q_w_dq_mode.
739 2014-01-09 Bradley Nelson <bradnelson@google.com>
740 Roland McGrath <mcgrathr@google.com>
742 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
743 last_rex_prefix is -1.
745 2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
747 * i386-gen.c (process_copyright): Update copyright year to 2014.
749 2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
751 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
753 For older changes see ChangeLog-2013
755 Copyright (C) 2014 Free Software Foundation, Inc.
757 Copying and distribution of this file, with or without modification,
758 are permitted in any medium without royalty provided the copyright
759 notice and this notice are preserved.
765 version-control: never