1 2020-01-30 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
4 (dis386): Use them to replace C2/C3 table entries.
5 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
6 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
7 ones. Use Size64 instead of DefaultSize on Intel64 ones.
8 * i386-tbl.h: Re-generate.
10 2020-01-30 Jan Beulich <jbeulich@suse.com>
12 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
14 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
16 * i386-tbl.h: Re-generate.
18 2020-01-30 Alan Modra <amodra@gmail.com>
20 * tic4x-dis.c (tic4x_dp): Make unsigned.
22 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
23 Jan Beulich <jbeulich@suse.com>
26 * i386-dis.c (MOVSXD_Fixup): New function.
27 (movsxd_mode): New enum.
28 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
29 (intel_operand_size): Handle movsxd_mode.
30 (OP_E_register): Likewise.
32 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
33 register on movsxd. Add movsxd with 16-bit destination register
34 for AMD64 and Intel64 ISAs.
35 * i386-tbl.h: Regenerated.
37 2020-01-27 Tamar Christina <tamar.christina@arm.com>
40 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
41 * aarch64-asm-2.c: Regenerate
42 * aarch64-dis-2.c: Likewise.
43 * aarch64-opc-2.c: Likewise.
45 2020-01-21 Jan Beulich <jbeulich@suse.com>
47 * i386-opc.tbl (sysret): Drop DefaultSize.
48 * i386-tbl.h: Re-generate.
50 2020-01-21 Jan Beulich <jbeulich@suse.com>
52 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
54 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
55 * i386-tbl.h: Re-generate.
57 2020-01-20 Nick Clifton <nickc@redhat.com>
59 * po/de.po: Updated German translation.
60 * po/pt_BR.po: Updated Brazilian Portuguese translation.
61 * po/uk.po: Updated Ukranian translation.
63 2020-01-20 Alan Modra <amodra@gmail.com>
65 * hppa-dis.c (fput_const): Remove useless cast.
67 2020-01-20 Alan Modra <amodra@gmail.com>
69 * arm-dis.c (print_insn_arm): Wrap 'T' value.
71 2020-01-18 Nick Clifton <nickc@redhat.com>
73 * configure: Regenerate.
74 * po/opcodes.pot: Regenerate.
76 2020-01-18 Nick Clifton <nickc@redhat.com>
78 Binutils 2.34 branch created.
80 2020-01-17 Christian Biesinger <cbiesinger@google.com>
82 * opintl.h: Fix spelling error (seperate).
84 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
86 * i386-opc.tbl: Add {vex} pseudo prefix.
87 * i386-tbl.h: Regenerated.
89 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
92 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
93 (neon_opcodes): Likewise.
94 (select_arm_features): Make sure we enable MVE bits when selecting
95 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
98 2020-01-16 Jan Beulich <jbeulich@suse.com>
100 * i386-opc.tbl: Drop stale comment from XOP section.
102 2020-01-16 Jan Beulich <jbeulich@suse.com>
104 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
105 (extractps): Add VexWIG to SSE2AVX forms.
106 * i386-tbl.h: Re-generate.
108 2020-01-16 Jan Beulich <jbeulich@suse.com>
110 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
111 Size64 from and use VexW1 on SSE2AVX forms.
112 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
113 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
114 * i386-tbl.h: Re-generate.
116 2020-01-15 Alan Modra <amodra@gmail.com>
118 * tic4x-dis.c (tic4x_version): Make unsigned long.
119 (optab, optab_special, registernames): New file scope vars.
120 (tic4x_print_register): Set up registernames rather than
121 malloc'd registertable.
122 (tic4x_disassemble): Delete optable and optable_special. Use
123 optab and optab_special instead. Throw away old optab,
124 optab_special and registernames when info->mach changes.
126 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
129 * z80-dis.c (suffix): Use .db instruction to generate double
132 2020-01-14 Alan Modra <amodra@gmail.com>
134 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
135 values to unsigned before shifting.
137 2020-01-13 Thomas Troeger <tstroege@gmx.de>
139 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
141 (print_insn_thumb16, print_insn_thumb32): Likewise.
142 (print_insn): Initialize the insn info.
143 * i386-dis.c (print_insn): Initialize the insn info fields, and
146 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
148 * arc-opc.c (C_NE): Make it required.
150 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
152 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
153 reserved register name.
155 2020-01-13 Alan Modra <amodra@gmail.com>
157 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
158 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
160 2020-01-13 Alan Modra <amodra@gmail.com>
162 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
163 result of wasm_read_leb128 in a uint64_t and check that bits
164 are not lost when copying to other locals. Use uint32_t for
165 most locals. Use PRId64 when printing int64_t.
167 2020-01-13 Alan Modra <amodra@gmail.com>
169 * score-dis.c: Formatting.
170 * score7-dis.c: Formatting.
172 2020-01-13 Alan Modra <amodra@gmail.com>
174 * score-dis.c (print_insn_score48): Use unsigned variables for
175 unsigned values. Don't left shift negative values.
176 (print_insn_score32): Likewise.
177 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
179 2020-01-13 Alan Modra <amodra@gmail.com>
181 * tic4x-dis.c (tic4x_print_register): Remove dead code.
183 2020-01-13 Alan Modra <amodra@gmail.com>
185 * fr30-ibld.c: Regenerate.
187 2020-01-13 Alan Modra <amodra@gmail.com>
189 * xgate-dis.c (print_insn): Don't left shift signed value.
190 (ripBits): Formatting, use 1u.
192 2020-01-10 Alan Modra <amodra@gmail.com>
194 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
195 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
197 2020-01-10 Alan Modra <amodra@gmail.com>
199 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
200 and XRREG value earlier to avoid a shift with negative exponent.
201 * m10200-dis.c (disassemble): Similarly.
203 2020-01-09 Nick Clifton <nickc@redhat.com>
206 * z80-dis.c (ld_ii_ii): Use correct cast.
208 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
211 * z80-dis.c (ld_ii_ii): Use character constant when checking
214 2020-01-09 Jan Beulich <jbeulich@suse.com>
216 * i386-dis.c (SEP_Fixup): New.
218 (dis386_twobyte): Use it for sysenter/sysexit.
219 (enum x86_64_isa): Change amd64 enumerator to value 1.
220 (OP_J): Compare isa64 against intel64 instead of amd64.
221 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
223 * i386-tbl.h: Re-generate.
225 2020-01-08 Alan Modra <amodra@gmail.com>
227 * z8k-dis.c: Include libiberty.h
228 (instr_data_s): Make max_fetched unsigned.
229 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
230 Don't exceed byte_info bounds.
231 (output_instr): Make num_bytes unsigned.
232 (unpack_instr): Likewise for nibl_count and loop.
233 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
235 * z8k-opc.h: Regenerate.
237 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
239 * arc-tbl.h (llock): Use 'LLOCK' as class.
241 (scond): Use 'SCOND' as class.
243 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
246 2020-01-06 Alan Modra <amodra@gmail.com>
248 * m32c-ibld.c: Regenerate.
250 2020-01-06 Alan Modra <amodra@gmail.com>
253 * z80-dis.c (suffix): Don't use a local struct buffer copy.
254 Peek at next byte to prevent recursion on repeated prefix bytes.
255 Ensure uninitialised "mybuf" is not accessed.
256 (print_insn_z80): Don't zero n_fetch and n_used here,..
257 (print_insn_z80_buf): ..do it here instead.
259 2020-01-04 Alan Modra <amodra@gmail.com>
261 * m32r-ibld.c: Regenerate.
263 2020-01-04 Alan Modra <amodra@gmail.com>
265 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
267 2020-01-04 Alan Modra <amodra@gmail.com>
269 * crx-dis.c (match_opcode): Avoid shift left of signed value.
271 2020-01-04 Alan Modra <amodra@gmail.com>
273 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
275 2020-01-03 Jan Beulich <jbeulich@suse.com>
277 * aarch64-tbl.h (aarch64_opcode_table): Use
278 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
280 2020-01-03 Jan Beulich <jbeulich@suse.com>
282 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
283 forms of SUDOT and USDOT.
285 2020-01-03 Jan Beulich <jbeulich@suse.com>
287 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
289 * opcodes/aarch64-dis-2.c: Re-generate.
291 2020-01-03 Jan Beulich <jbeulich@suse.com>
293 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
295 * opcodes/aarch64-dis-2.c: Re-generate.
297 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
299 * z80-dis.c: Add support for eZ80 and Z80 instructions.
301 2020-01-01 Alan Modra <amodra@gmail.com>
303 Update year range in copyright notice of all files.
305 For older changes see ChangeLog-2019
307 Copyright (C) 2020 Free Software Foundation, Inc.
309 Copying and distribution of this file, with or without modification,
310 are permitted in any medium without royalty provided the copyright
311 notice and this notice are preserved.
317 version-control: never