opcodes/ChangeLog

   1 2011-11-25  Nick Clifton  <nickc@redhat.com>
   2
   3         * po/it.po: Updated Italian translation.
   4
   5 2011-11-16  Maciej W. Rozycki  <macro@codesourcery.com>
   6
   7         * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
   8         for "alnv.ps".
   9
  10 2011-11-02  Nick Clifton  <nickc@redhat.com>
  11
  12         * po/it.po: New Italian translation.
  13         * configure.in (ALL_LINGUAS): Add it.
  14         * configure: Regenerate.
  15         * po/opcodes.pot: Regenerate.
  16
  17 2011-11-01  DJ Delorie  <dj@redhat.com>
  18
  19         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
  20         rl78-dis.c.
  21         (MAINTAINERCLEANFILES): Add rl78-decode.c.
  22         (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
  23         * Makefile.in: Regenerate.
  24         * configure.in: Add bfd_rl78_arch case.
  25         * configure: Regenerate.
  26         * disassemble.c: Define ARCH_rl78.
  27         (disassembler): Add ARCH_rl78 case.
  28         * rl78-decode.c: New file.
  29         * rl78-decode.opc: New file.
  30         * rl78-dis.c: New file.
  31
  32 2011-10-27  Peter Bergner  <bergner@vnet.ibm.com>
  33
  34         * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
  35         dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
  36         diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
  37         instructions.
  38
  39 2011-10-26  Nick Clifton  <nickc@redhat.com>
  40
  41         PR binutils/13348
  42         * i386-dis.c (print_insn): Fix testing of array subscript.
  43
  44 2011-10-26  Joern Rennecke  <joern.rennecke@embecosm.com>
  45
  46         * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
  47         * epiphany-asm.c, epiphany-opc.h: Regenerate.
  48
  49 2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
  50
  51         * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
  52         (TARGET_LIBOPCODES_CFILES): Add  epiphany-asm.c, epiphany-desc.c,
  53         epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
  54         (CLEANFILES): Add stamp-epiphany.
  55         (EPIPHANY_DEPS): Set.  Make CGEN-generated Epiphany files depend on it.
  56         (stamp-epiphany): New rule.
  57         * configure.in: Handle bfd_epiphany_arch.
  58         * disassemble.c (ARCH_epiphany): Define.
  59         (disassembler): Handle bfd_arch_epiphany.
  60         * epiphany-asm.c: New file.
  61         * epiphany-desc.c: New file.
  62         * epiphany-desc.h: New file.
  63         * epiphany-dis.c: New file.
  64         * epiphany-ibld.c: New file.
  65         * epiphany-opc.c: New file.
  66         * epiphany-opc.h: New file.
  67         * Makefile.in: Regenerate.
  68         * configure: Regenerate.
  69         * po/POTFILES.in: Regenerate.
  70         * po/opcodes.pot: Regenerate.
  71
  72 2011-10-24  Julian Brown  <julian@codesourcery.com>
  73
  74         * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
  75
  76 2011-10-21  Jan Glauber  <jang@linux.vnet.ibm.com>
  77
  78         * s390-opc.txt: Add CPUMF instructions.
  79
  80 2011-10-18  Jie Zhang  <jie@codesourcery.com>
  81             Julian Brown  <julian@codesourcery.com>
  82
  83         * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
  84
  85 2011-10-10  Nick Clifton  <nickc@redhat.com>
  86
  87         * po/es.po: Updated Spanish translation.
  88         * po/fi.po: Updated Finnish translation.
  89
  90 2011-09-28  Jan Beulich  <jbeulich@suse.com>
  91
  92         * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
  93         RBX): New.
  94         (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
  95         (powerpc_opcodes): Use RAX for second and RBXC for third operand of
  96         lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
  97         lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
  98         mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
  99         on DFP quad instructions.
 100
 101 2011-09-27  David S. Miller  <davem@davemloft.net>
 102
 103         * sparc-opc.c (sparc_opcodes): Fix random instruction to write
 104         to a float instead of an integer register.
 105
 106 2011-09-26  David S. Miller  <davem@davemloft.net>
 107
 108         * sparc-opc.c (sparc_opcodes): Add integer multiply-add
 109         instructions.
 110
 111 2011-09-21  David S. Miller  <davem@davemloft.net>
 112
 113         * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
 114         bits.  Fix "fchksm16" mnemonic.
 115
 116 2011-09-08  Mark Fortescue <mark@mtfhpc.demon.co.uk>
 117
 118         The changes below bring 'mov' and 'ticc' instructions into line
 119         with the V8 SPARC Architecture Manual.
 120         * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
 121         * sparc-opc.c (sparc_opcodes): Add alias entries for
 122         'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
 123         'mov regrs2,%wim' and 'mov regrs2,%tbr'.
 124         * sparc-opc.c (sparc_opcodes): Move/Change entries for
 125         'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
 126         and 'mov imm,%tbr'.
 127         * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
 128         mov aliases.
 129
 130         * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
 131         This has been reported as being accepted by the Sun assmebler.
 132
 133 2011-09-08  David S. Miller  <davem@davemloft.net>
 134
 135         * sparc-opc.c (pdistn): Destination is integer not float register.
 136
 137 2011-09-07  Andreas Schwab  <schwab@linux-m68k.org>
 138
 139         PR gas/13145
 140         * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
 141
 142 2011-08-26  Nick Clifton  <nickc@redhat.com>
 143
 144         * po/es.po: Updated Spanish translation.
 145
 146 2011-08-22  Nick Clifton  <nickc@redhat.com>
 147
 148         * Makefile.am (CPUDIR): Redfine to point to top level cpu
 149         directory.
 150         (stamp-frv): Use CPUDIR.
 151         (stamp-iq2000): Likewise.
 152         (stamp-lm32): Likewise.
 153         (stamp-m32c): Likewise.
 154         (stamp-mt): Likewise.
 155         (stamp-xc16x): Likewise.
 156         * Makefile.in: Regenerate.
 157
 158 2011-08-09  Chao-ying Fu  <fu@mips.com>
 159             Maciej W. Rozycki  <macro@codesourcery.com>
 160
 161         * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
 162         and "mips64r2".
 163         (print_insn_args, print_insn_micromips): Handle MCU.
 164         * micromips-opc.c (MC): New macro.
 165         (micromips_opcodes): Add "aclr", "aset" and "iret".
 166         * mips-opc.c (MC): New macro.
 167         (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
 168
 169 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 170
 171         * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
 172         (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
 173         (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
 174         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
 175         (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
 176         (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
 177         (WR_s): Update macro.
 178         (micromips_opcodes): Update register use flags of: "addiu",
 179         "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
 180         "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
 181         "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
 182         "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
 183         "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
 184         "swm" and "xor" instructions.
 185
 186 2011-08-05  David S. Miller  <davem@davemloft.net>
 187
 188         * sparc-dis.c (v9a_ast_reg_names): Add "cps".
 189         (X_RS3): New macro.
 190         (print_insn_sparc): Handle '4', '5', and '(' format codes.
 191         Accept %asr numbers below 28.
 192         * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
 193         instructions.
 194
 195 2011-08-02  Quentin Neill  <quentin.neill@amd.com>
 196
 197         * i386-dis.c (xop_table): Remove spurious bextr insn.
 198
 199 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 200
 201         PR ld/13048
 202         * i386-dis.c (print_insn): Optimize info->mach check.
 203
 204 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 205
 206         PR gas/13046
 207         * i386-opc.tbl: Add Disp32S to 64bit call.
 208         * i386-tbl.h: Regenerated.
 209
 210 2011-07-24  Chao-ying Fu  <fu@mips.com>
 211             Maciej W. Rozycki  <macro@codesourcery.com>
 212
 213         * micromips-opc.c: New file.
 214         * mips-dis.c (micromips_to_32_reg_b_map): New array.
 215         (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
 216         (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
 217         (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
 218         (micromips_to_32_reg_q_map): Likewise.
 219         (micromips_imm_b_map, micromips_imm_c_map): Likewise.
 220         (micromips_ase): New variable.
 221         (is_micromips): New function.
 222         (set_default_mips_dis_options): Handle microMIPS ASE.
 223         (print_insn_micromips): New function.
 224         (is_compressed_mode_p): Likewise.
 225         (_print_insn_mips): Handle microMIPS instructions.
 226         * Makefile.am (CFILES): Add micromips-opc.c.
 227         * configure.in (bfd_mips_arch): Add micromips-opc.lo.
 228         * Makefile.in: Regenerate.
 229         * configure: Regenerate.
 230
 231         * mips-dis.c (micromips_to_32_reg_h_map): New variable.
 232         (micromips_to_32_reg_i_map): Likewise.
 233         (micromips_to_32_reg_m_map): Likewise.
 234         (micromips_to_32_reg_n_map): New macro.
 235
 236 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 237
 238         * mips-opc.c (NODS): New macro.
 239         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 240         (DSP_VOLA): Likewise.
 241         (mips_builtin_opcodes): Add NODS annotation to "deret" and
 242         "eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
 243         place of TRAP for "wait", "waiti" and "yield".
 244         * mips16-opc.c (NODS): New macro.
 245         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 246         (mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
 247         "restore" and "save".
 248
 249 2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         * configure.in: Handle bfd_k1om_arch.
 252         * configure: Regenerated.
 253
 254         * disassemble.c (disassembler): Handle bfd_k1om_arch.
 255
 256         * i386-dis.c (print_insn): Handle bfd_mach_k1om and
 257         bfd_mach_k1om_intel_syntax.
 258
 259         * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
 260         ~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
 261         (cpu_flags): Add CpuK1OM.
 262
 263         * i386-opc.h (CpuK1OM): New.
 264         (i386_cpu_flags): Add cpuk1om.
 265
 266         * i386-init.h: Regenerated.
 267         * i386-tbl.h: Likewise.
 268
 269 2011-07-12  Nick Clifton  <nickc@redhat.com>
 270
 271         * arm-dis.c (print_insn_arm): Revert previous, undocumented,
 272         accidental change.
 273
 274 2011-07-01  Nick Clifton  <nickc@redhat.com>
 275
 276         PR binutils/12329
 277         * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
 278         insns using post-increment addressing.
 279
 280 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 281
 282         * i386-dis.c (vex_len_table): Update rorxS.
 283
 284 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 285
 286         AVX Programming Reference (June, 2011)
 287         * i386-dis.c (vex_len_table): Correct rorxS.
 288
 289         * i386-opc.tbl: Correct rorx.
 290         * i386-tbl.h: Regenerated.
 291
 292 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * tilegx-opc.c (find_opcode): Replace "index" with "i".
 295         * tilepro-opc.c (find_opcode): Likewise.
 296
 297 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
 298
 299         * mips16-opc.c (jalrc, jrc): Move earlier in file.
 300
 301 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 302
 303         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
 304         PREFIX_VEX_0F388E.
 305
 306 2011-06-17  Andreas Schwab  <schwab@redhat.com>
 307
 308         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
 309         (MOSTLYCLEANFILES): ... here.
 310         * Makefile.in: Regenerate.
 311
 312 2011-06-14  Alan Modra  <amodra@gmail.com>
 313
 314         * Makefile.in: Regenerate.
 315
 316 2011-06-13  Walter Lee  <walt@tilera.com>
 317
 318         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
 319         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
 320         * Makefile.in: Regenerate.
 321         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
 322         * configure: Regenerate.
 323         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
 324         * po/POTFILES.in: Regenerate.
 325         * tilegx-dis.c: New file.
 326         * tilegx-opc.c: New file.
 327         * tilepro-dis.c: New file.
 328         * tilepro-opc.c: New file.
 329
 330 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 331
 332         AVX Programming Reference (June, 2011)
 333         * i386-dis.c (XMGatherQ): New.
 334         * i386-dis.c (EXxmm_mb): New.
 335         (EXxmm_mb): Likewise.
 336         (EXxmm_mw): Likewise.
 337         (EXxmm_md): Likewise.
 338         (EXxmm_mq): Likewise.
 339         (EXxmmdw): Likewise.
 340         (EXxmmqd): Likewise.
 341         (VexGatherQ): Likewise.
 342         (MVexVSIBDWpX): Likewise.
 343         (MVexVSIBQWpX): Likewise.
 344         (xmm_mb_mode): Likewise.
 345         (xmm_mw_mode): Likewise.
 346         (xmm_md_mode): Likewise.
 347         (xmm_mq_mode): Likewise.
 348         (xmmdw_mode): Likewise.
 349         (xmmqd_mode): Likewise.
 350         (ymmxmm_mode): Likewise.
 351         (vex_vsib_d_w_dq_mode): Likewise.
 352         (vex_vsib_q_w_dq_mode): Likewise.
 353         (MOD_VEX_0F385A_PREFIX_2): Likewise.
 354         (MOD_VEX_0F388C_PREFIX_2): Likewise.
 355         (MOD_VEX_0F388E_PREFIX_2): Likewise.
 356         (PREFIX_0F3882): Likewise.
 357         (PREFIX_VEX_0F3816): Likewise.
 358         (PREFIX_VEX_0F3836): Likewise.
 359         (PREFIX_VEX_0F3845): Likewise.
 360         (PREFIX_VEX_0F3846): Likewise.
 361         (PREFIX_VEX_0F3847): Likewise.
 362         (PREFIX_VEX_0F3858): Likewise.
 363         (PREFIX_VEX_0F3859): Likewise.
 364         (PREFIX_VEX_0F385A): Likewise.
 365         (PREFIX_VEX_0F3878): Likewise.
 366         (PREFIX_VEX_0F3879): Likewise.
 367         (PREFIX_VEX_0F388C): Likewise.
 368         (PREFIX_VEX_0F388E): Likewise.
 369         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
 370         (PREFIX_VEX_0F38F5): Likewise.
 371         (PREFIX_VEX_0F38F6): Likewise.
 372         (PREFIX_VEX_0F3A00): Likewise.
 373         (PREFIX_VEX_0F3A01): Likewise.
 374         (PREFIX_VEX_0F3A02): Likewise.
 375         (PREFIX_VEX_0F3A38): Likewise.
 376         (PREFIX_VEX_0F3A39): Likewise.
 377         (PREFIX_VEX_0F3A46): Likewise.
 378         (PREFIX_VEX_0F3AF0): Likewise.
 379         (VEX_LEN_0F3816_P_2): Likewise.
 380         (VEX_LEN_0F3819_P_2): Likewise.
 381         (VEX_LEN_0F3836_P_2): Likewise.
 382         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 383         (VEX_LEN_0F38F5_P_0): Likewise.
 384         (VEX_LEN_0F38F5_P_1): Likewise.
 385         (VEX_LEN_0F38F5_P_3): Likewise.
 386         (VEX_LEN_0F38F6_P_3): Likewise.
 387         (VEX_LEN_0F38F7_P_1): Likewise.
 388         (VEX_LEN_0F38F7_P_2): Likewise.
 389         (VEX_LEN_0F38F7_P_3): Likewise.
 390         (VEX_LEN_0F3A00_P_2): Likewise.
 391         (VEX_LEN_0F3A01_P_2): Likewise.
 392         (VEX_LEN_0F3A38_P_2): Likewise.
 393         (VEX_LEN_0F3A39_P_2): Likewise.
 394         (VEX_LEN_0F3A46_P_2): Likewise.
 395         (VEX_LEN_0F3AF0_P_3): Likewise.
 396         (VEX_W_0F3816_P_2): Likewise.
 397         (VEX_W_0F3818_P_2): Likewise.
 398         (VEX_W_0F3819_P_2): Likewise.
 399         (VEX_W_0F3836_P_2): Likewise.
 400         (VEX_W_0F3846_P_2): Likewise.
 401         (VEX_W_0F3858_P_2): Likewise.
 402         (VEX_W_0F3859_P_2): Likewise.
 403         (VEX_W_0F385A_P_2_M_0): Likewise.
 404         (VEX_W_0F3878_P_2): Likewise.
 405         (VEX_W_0F3879_P_2): Likewise.
 406         (VEX_W_0F3A00_P_2): Likewise.
 407         (VEX_W_0F3A01_P_2): Likewise.
 408         (VEX_W_0F3A02_P_2): Likewise.
 409         (VEX_W_0F3A38_P_2): Likewise.
 410         (VEX_W_0F3A39_P_2): Likewise.
 411         (VEX_W_0F3A46_P_2): Likewise.
 412         (MOD_VEX_0F3818_PREFIX_2): Removed.
 413         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 414         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 415         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 416         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 417         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 418         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 419         (VEX_LEN_0F3A0E_P_2): Likewise.
 420         (VEX_LEN_0F3A0F_P_2): Likewise.
 421         (VEX_LEN_0F3A42_P_2): Likewise.
 422         (VEX_LEN_0F3A4C_P_2): Likewise.
 423         (VEX_W_0F3818_P_2_M_0): Likewise.
 424         (VEX_W_0F3819_P_2_M_0): Likewise.
 425         (prefix_table): Updated.
 426         (three_byte_table): Likewise.
 427         (vex_table): Likewise.
 428         (vex_len_table): Likewise.
 429         (vex_w_table): Likewise.
 430         (mod_table): Likewise.
 431         (putop): Handle "LW".
 432         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 433         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 434         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 435         (OP_EX): Likewise.
 436         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 437         vex_vsib_q_w_dq_mode.
 438         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 439         (OP_VEX): Likewise.
 440
 441         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 442         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 443         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 444         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 445         (opcode_modifiers): Add VecSIB.
 446
 447         * i386-opc.h (CpuAVX2): New.
 448         (CpuBMI2): Likewise.
 449         (CpuLZCNT): Likewise.
 450         (CpuINVPCID): Likewise.
 451         (VecSIB128): Likewise.
 452         (VecSIB256): Likewise.
 453         (VecSIB): Likewise.
 454         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 455         (i386_opcode_modifier): Add vecsib.
 456
 457         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 458         * i386-init.h: Regenerated.
 459         * i386-tbl.h: Likewise.
 460
 461 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 462
 463         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 464         * i386-init.h: Regenerated.
 465
 466 2011-06-03  Nick Clifton  <nickc@redhat.com>
 467
 468         PR binutils/12752
 469         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 470         computing address offsets.
 471         (print_arm_address): Likewise.
 472         (print_insn_arm): Likewise.
 473         (print_insn_thumb16): Likewise.
 474         (print_insn_thumb32): Likewise.
 475
 476 2011-06-02  Jie Zhang <jie@codesourcery.com>
 477             Nathan Sidwell <nathan@codesourcery.com>
 478             Maciej Rozycki <macro@codesourcery.com>
 479
 480         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 481         as address offset.
 482         (print_arm_address): Likewise. Elide positive #0 appropriately.
 483         (print_insn_arm): Likewise.
 484
 485 2011-06-02  Nick Clifton  <nickc@redhat.com>
 486
 487         PR gas/12752
 488         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 489         passed to print_address_func.
 490
 491 2011-06-02  Nick Clifton  <nickc@redhat.com>
 492
 493         * arm-dis.c: Fix spelling mistakes.
 494         * op/opcodes.pot: Regenerate.
 495
 496 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 497
 498         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 499         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 500         * s390-opc.txt: Fix cxr instruction type.
 501
 502 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 503
 504         * s390-opc.c: Add new instruction types marking register pair
 505         operands.
 506         * s390-opc.txt: Match instructions having register pair operands
 507         to the new instruction types.
 508
 509 2011-05-19  Nick Clifton  <nickc@redhat.com>
 510
 511         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 512         operands.
 513
 514 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 515
 516         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 517         * i386-init.h: Regenerated.
 518
 519 2011-04-27  Nick Clifton  <nickc@redhat.com>
 520
 521         * po/da.po: Updated Danish translation.
 522
 523 2011-04-26  Anton Blanchard  <anton@samba.org>
 524
 525         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 526
 527 2011-04-21  DJ Delorie  <dj@redhat.com>
 528
 529         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 530         * rx-decode.c: Regenerate.
 531
 532 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 533
 534         * i386-init.h: Regenerated.
 535
 536 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 537
 538         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 539         from bdver1 flags.
 540
 541 2011-04-13  Nick Clifton  <nickc@redhat.com>
 542
 543         * v850-dis.c (disassemble): Always print a closing square brace if
 544         an opening square brace was printed.
 545
 546 2011-04-12  Nick Clifton  <nickc@redhat.com>
 547
 548         PR binutils/12534
 549         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 550         patterns.
 551         (print_insn_thumb32): Handle %L.
 552
 553 2011-04-11  Julian Brown  <julian@codesourcery.com>
 554
 555         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 556         (print_insn_thumb32): Add APSR bitmask support.
 557
 558 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 559
 560         * arm-dis.c (print_insn): init vars moved into private_data structure.
 561
 562 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 563
 564         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 565
 566 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 567
 568         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 569         post-increment to support LPM Z+ instruction. Add support for 'E'
 570         constraint for DES instruction.
 571         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 572
 573 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 574
 575         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 576
 577 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 578
 579         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 580         Use branch types instead.
 581         (print_insn): Likewise.
 582
 583 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 584
 585         * mips-opc.c (mips_builtin_opcodes): Correct register use
 586         annotation of "alnv.ps".
 587
 588 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 589
 590         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 591
 592 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 593
 594         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 595
 596 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 597
 598         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 599
 600 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 601
 602         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 603         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 604         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 605         exception, end_of_registers, msize, memory, bfd_mach.
 606         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 607         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 608         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 609         (get_allreg): Change to new defines.  Fallback to abort().
 610
 611 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 612
 613         * bfin-dis.c: Add whitespace/parenthesis where needed.
 614
 615 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 616
 617         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 618         than 7.
 619
 620 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 621
 622         * configure: Regenerate.
 623
 624 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 625
 626         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 627
 628 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 629
 630         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 631         dregs only when P is set, and dregs_lo otherwise.
 632
 633 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 634
 635         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 636
 637 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 638
 639         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 640
 641 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 642
 643         * bfin-dis.c (machine_registers): Delete REG_GP.
 644         (reg_names): Delete "GP".
 645         (decode_allregs): Change REG_GP to REG_LASTREG.
 646
 647 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 648
 649         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 650         M_IH, M_IU): Delete.
 651
 652 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 653
 654         * bfin-dis.c (reg_names): Add const.
 655         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 656         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 657         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 658         decode_counters, decode_allregs): Likewise.
 659
 660 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 661
 662         * i386-dis.c (OP_J): Parenthesize expression to prevent
 663         truncated addresses.
 664         (print_insn): Fix indentation off-by-one.
 665
 666 2011-02-01  Nick Clifton  <nickc@redhat.com>
 667
 668         * po/da.po: Updated Danish translation.
 669
 670 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 671
 672         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 673
 674 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 675
 676         * i386-dis.c (sIbT): New.
 677         (b_T_mode): Likewise.
 678         (dis386): Replace sIb with sIbT on "pushT".
 679         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 680         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 681
 682 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 683
 684         * i386-init.h: Regenerated.
 685         * i386-tbl.h: Regenerated
 686
 687 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 688
 689         * i386-dis.c (REG_XOP_TBM_01): New.
 690         (REG_XOP_TBM_02): New.
 691         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 692         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 693         entries, and add bextr instruction.
 694
 695         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 696         (cpu_flags): Add CpuTBM.
 697
 698         * i386-opc.h (CpuTBM) New.
 699         (i386_cpu_flags): Add bit cputbm.
 700
 701         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 702         blcs, blsfill, blsic, t1mskc, and tzmsk.
 703
 704 2011-01-12  DJ Delorie  <dj@redhat.com>
 705
 706         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 707
 708 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 709
 710         * mips-dis.c (print_insn_args): Adjust the value to print the real
 711         offset for "+c" argument.
 712
 713 2011-01-10  Nick Clifton  <nickc@redhat.com>
 714
 715         * po/da.po: Updated Danish translation.
 716
 717 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 718
 719         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 720
 721 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 722
 723         * i386-dis.c (REG_VEX_38F3): New.
 724         (PREFIX_0FBC): Likewise.
 725         (PREFIX_VEX_38F2): Likewise.
 726         (PREFIX_VEX_38F3_REG_1): Likewise.
 727         (PREFIX_VEX_38F3_REG_2): Likewise.
 728         (PREFIX_VEX_38F3_REG_3): Likewise.
 729         (PREFIX_VEX_38F7): Likewise.
 730         (VEX_LEN_38F2_P_0): Likewise.
 731         (VEX_LEN_38F3_R_1_P_0): Likewise.
 732         (VEX_LEN_38F3_R_2_P_0): Likewise.
 733         (VEX_LEN_38F3_R_3_P_0): Likewise.
 734         (VEX_LEN_38F7_P_0): Likewise.
 735         (dis386_twobyte): Use PREFIX_0FBC.
 736         (reg_table): Add REG_VEX_38F3.
 737         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 738         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 739         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 740         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 741         PREFIX_VEX_38F7.
 742         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 743         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 744         VEX_LEN_38F7_P_0.
 745
 746         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 747         (cpu_flags): Add CpuBMI.
 748
 749         * i386-opc.h (CpuBMI): New.
 750         (i386_cpu_flags): Add cpubmi.
 751
 752         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 753         * i386-init.h: Regenerated.
 754         * i386-tbl.h: Likewise.
 755
 756 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 757
 758         * i386-dis.c (VexGdq): New.
 759         (OP_VEX): Handle dq_mode.
 760
 761 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 762
 763         * i386-gen.c (process_copyright): Update copyright to 2011.
 764
 765 For older changes see ChangeLog-2010
 766 \f
 767 Local Variables:
 768 mode: change-log
 769 left-margin: 8
 770 fill-column: 74
 771 version-control: never
 772 End: