opcodes/ChangeLog

   1 2005-01-27  Andrew Cagney  <cagney@gnu.org>
   2
   3         * configure: Regenerate to track ../gettext.m4 change.
   4
   5 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
   6
   7         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
   8         * frv-asm.c: Rebuilt.
   9         * frv-desc.c: Rebuilt.
  10         * frv-desc.h: Rebuilt.
  11         * frv-dis.c: Rebuilt.
  12         * frv-ibld.c: Rebuilt.
  13         * frv-opc.c: Rebuilt.
  14         * frv-opc.h: Rebuilt.
  15
  16 2005-01-24  Andrew Cagney  <cagney@gnu.org>
  17
  18         * configure: Regenerate, ../gettext.m4 was updated.
  19
  20 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  21
  22         * mips-opc.c:  Change INSN_ALIAS to INSN2_ALIAS.
  23         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  24         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  25         * mips-dis.c: Ditto.
  26
  27 2005-01-20  Alan Modra  <amodra@bigpond.net.au>
  28
  29         * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
  30
  31 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  32
  33         * mips-dis.c (no_aliases): New disassembly option flag.
  34         (set_default_mips_dis_options): Init no_aliases to zero.
  35         (parse_mips_dis_option): Handle no-aliases option.
  36         (print_insn_mips): Ignore table entries that are aliases
  37         if no_aliases is set.
  38         (print_insn_mips16): Ditto.
  39         * mips-opc.c (mips_builtin_opcodes): Add initializer column for
  40         new pinfo2 member and add INSN_ALIAS initializers as needed.  Also
  41         move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
  42         * mips16-opc.c (mips16_opcodes): Ditto.
  43
  44 2005-01-17  Andrew Stubbs  <andrew.stubbs@st.com>
  45
  46         * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
  47         (inheritance diagram): Add missing edge.
  48         (arch_sh1_up): Rename arch_sh_up to match external name to make life
  49         easier for the testsuite.
  50         (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
  51         (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
  52         (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
  53         arch_sh2a_or_sh4_up child.
  54         (sh_table): Do renaming as above.
  55         Correct comment for ldc.l for gas testsuite to read.
  56         Remove rogue mul.l from sh1 (duplicate of the one for sh2).
  57         Correct comments for movy.w and movy.l for gas testsuite to read.
  58         Correct comments for fmov.d and fmov.s for gas testsuite to read.
  59
  60 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
  61
  62         * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
  63
  64 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
  65
  66         * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
  67
  68 2005-01-10  Andreas Schwab  <schwab@suse.de>
  69
  70         * disassemble.c (disassemble_init_for_target) <case
  71         bfd_arch_ia64>: Set skip_zeroes to 16.
  72         <case bfd_arch_tic4x>: Set skip_zeroes to 32.
  73
  74 2004-12-23  Tomer Levi  <Tomer.Levi@nsc.com>
  75
  76         * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
  77
  78 2004-12-14  Svein E. Seldal  <Svein.Seldal@solidas.com>
  79
  80         * avr-dis.c: Prettyprint. Added printing of symbol names in all
  81         memory references. Convert avr_operand() to C90 formatting.
  82
  83 2004-12-05  Tomer Levi  <Tomer.Levi@nsc.com>
  84
  85         * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
  86
  87 2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  88
  89         * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
  90         (no_op_insn): Initialize array with instructions that have no
  91         operands.
  92         * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
  93
  94 2004-11-29  Richard Earnshaw  <rearnsha@arm.com>
  95
  96         * arm-dis.c: Correct top-level comment.
  97
  98 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
  99
 100         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
 101         architecuture defining the insn.
 102         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
 103         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
 104         field.
 105         Also include opcode/arm.h.
 106         * Makefile.am (arm-dis.lo): Update dependency list.
 107         * Makefile.in: Regenerate.
 108
 109 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
 110
 111         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
 112         reflect the change to the short immediate syntax.
 113
 114 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 115
 116         * or32-opc.c (debug): Warning fix.
 117         * po/POTFILES.in: Regenerate.
 118
 119         * maxq-dis.c: Formatting.
 120         (print_insn): Warning fix.
 121
 122 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
 123
 124         * arm-dis.c (WORD_ADDRESS): Define.
 125         (print_insn): Use it.  Correct big-endian end-of-section handling.
 126
 127 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 128             Vineet Sharma      <vineets@noida.hcltech.com>
 129
 130         * maxq-dis.c: New file.
 131         * disassemble.c (ARCH_maxq): Define.
 132         (disassembler): Add 'print_insn_maxq_little' for handling maxq
 133         instructions..
 134         * configure.in: Add case for bfd_maxq_arch.
 135         * configure: Regenerate.
 136         * Makefile.am: Add support for maxq-dis.c
 137         * Makefile.in: Regenerate.
 138         * aclocal.m4: Regenerate.
 139
 140 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 141
 142         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
 143         mode.
 144         * crx-dis.c: Likewise.
 145
 146 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 147
 148         Generally, handle CRISv32.
 149         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
 150         (struct cris_disasm_data): New type.
 151         (format_reg, format_hex, cris_constraint, print_flags)
 152         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
 153         callers changed.
 154         (format_sup_reg, print_insn_crisv32_with_register_prefix)
 155         (print_insn_crisv32_without_register_prefix)
 156         (print_insn_crisv10_v32_with_register_prefix)
 157         (print_insn_crisv10_v32_without_register_prefix)
 158         (cris_parse_disassembler_options): New functions.
 159         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
 160         parameter.  All callers changed.
 161         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
 162         failure.
 163         (cris_constraint) <case 'Y', 'U'>: New cases.
 164         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
 165         for constraint 'n'.
 166         (print_with_operands) <case 'Y'>: New case.
 167         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
 168         <case 'N', 'Y', 'Q'>: New cases.
 169         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
 170         (print_insn_cris_with_register_prefix)
 171         (print_insn_cris_without_register_prefix): Call
 172         cris_parse_disassembler_options.
 173         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
 174         for CRISv32 and the size of immediate operands.  New v32-only
 175         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
 176         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
 177         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
 178         Change brp to be v3..v10.
 179         (cris_support_regs): New vector.
 180         (cris_opcodes): Update head comment.  New format characters '[',
 181         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
 182         Add new opcodes for v32 and adjust existing opcodes to accommodate
 183         differences to earlier variants.
 184         (cris_cond15s): New vector.
 185
 186 2004-11-04 Jan Beulich <jbeulich@novell.com>
 187
 188         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
 189         (indirEb): Remove.
 190         (Mp): Use f_mode rather than none at all.
 191         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
 192         replaces what previously was x_mode; x_mode now means 128-bit SSE
 193         operands.
 194         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
 195         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
 196         pinsrw's second operand is Edqw.
 197         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 198         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 199         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 200         mode when an operand size override is present or always suffixing.
 201         More instructions will need to be added to this group.
 202         (putop): Handle new macro chars 'C' (short/long suffix selector),
 203         'I' (Intel mode override for following macro char), and 'J' (for
 204         adding the 'l' prefix to far branches in AT&T mode). When an
 205         alternative was specified in the template, honor macro character when
 206         specified for Intel mode.
 207         (OP_E): Handle new *_mode values. Correct pointer specifications for
 208         memory operands. Consolidate output of index register.
 209         (OP_G): Handle new *_mode values.
 210         (OP_I): Handle const_1_mode.
 211         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 212         respective opcode prefix bits have been consumed.
 213         (OP_EM, OP_EX): Provide some default handling for generating pointer
 214         specifications.
 215
 216 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 217
 218         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 219         COP_INST macro.
 220
 221 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 222
 223         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 224         (getregliststring): Support HI/LO and user registers.
 225         * crx-opc.c (crx_instruction): Update data structure according to the
 226         rearrangement done in CRX opcode header file.
 227         (crx_regtab):  Likewise.
 228         (crx_optab):  Likewise.
 229         (crx_instruction): Reorder load/stor instructions, remove unsupported
 230         formats.
 231         support new Co-Processor instruction 'cpi'.
 232
 233 2004-10-27  Nick Clifton  <nickc@redhat.com>
 234
 235         * opcodes/iq2000-asm.c: Regenerate.
 236         * opcodes/iq2000-desc.c: Regenerate.
 237         * opcodes/iq2000-desc.h: Regenerate.
 238         * opcodes/iq2000-dis.c: Regenerate.
 239         * opcodes/iq2000-ibld.c: Regenerate.
 240         * opcodes/iq2000-opc.c: Regenerate.
 241         * opcodes/iq2000-opc.h: Regenerate.
 242
 243 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 244
 245         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 246         us4, us5 (respectively).
 247         Remove unsupported 'popa' instruction.
 248         Reverse operands order in store co-processor instructions.
 249
 250 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 251
 252         * Makefile.am: Run "make dep-am"
 253         * Makefile.in: Regenerate.
 254
 255 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 256
 257         * xtensa-dis.c: Use ISO C90 formatting.
 258
 259 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 260
 261         * ppc-opc.c: Revert 2004-09-09 change.
 262
 263 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 264
 265         * xtensa-dis.c (state_names): Delete.
 266         (fetch_data): Use xtensa_isa_maxlength.
 267         (print_xtensa_operand): Replace operand parameter with opcode/operand
 268         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 269         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 270         instruction bundles.  Use xmalloc instead of malloc.
 271
 272 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 273
 274         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 275         initializers.
 276
 277 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 278
 279         * crx-opc.c (crx_instruction): Support Co-processor insns.
 280         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 281         (getregliststring): Change function to use the above enum.
 282         (print_arg): Handle CO-Processor insns.
 283         (crx_cinvs): Add 'b' option to invalidate the branch-target
 284         cache.
 285
 286 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 287
 288         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 289         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 290         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 291         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 292         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 293
 294 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 295
 296         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 297         rather than add it.
 298
 299 2004-09-30  Paul Brook  <paul@codesourcery.com>
 300
 301         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 302         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 303
 304 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 305
 306         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 307         (CONFIG_STATUS_DEPENDENCIES): New.
 308         (Makefile): Removed.
 309         (config.status): Likewise.
 310         * Makefile.in: Regenerated.
 311
 312 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 313
 314         * Makefile.am: Run "make dep-am".
 315         * Makefile.in: Regenerate.
 316         * aclocal.m4: Regenerate.
 317         * configure: Regenerate.
 318         * po/POTFILES.in: Regenerate.
 319         * po/opcodes.pot: Regenerate.
 320
 321 2004-09-11  Andreas Schwab  <schwab@suse.de>
 322
 323         * configure: Rebuild.
 324
 325 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 326
 327         * ppc-opc.c (L): Make this field not optional.
 328
 329 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 330
 331         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 332         Fix parameter to 'm[t|f]csr' insns.
 333
 334 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 335
 336         * configure.in: Autoupdate to autoconf 2.59.
 337         * aclocal.m4: Rebuild with aclocal 1.4p6.
 338         * configure: Rebuild with autoconf 2.59.
 339         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 340         bfd changes for autoconf 2.59 on the way).
 341         * config.in: Rebuild with autoheader 2.59.
 342
 343 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 344
 345         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 346
 347 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 348
 349         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 350         (GRPPADLCK2): New define.
 351         (twobyte_has_modrm): True for 0xA6.
 352         (grps): GRPPADLCK2 for opcode 0xA6.
 353
 354 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 355
 356         Introduce SH2a support.
 357         * sh-opc.h (arch_sh2a_base): Renumber.
 358         (arch_sh2a_nofpu_base): Remove.
 359         (arch_sh_base_mask): Adjust.
 360         (arch_opann_mask): New.
 361         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 362         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 363         (sh_table): Adjust whitespace.
 364         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 365         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 366         instruction list throughout.
 367         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 368         of arch_sh2a in instruction list throughout.
 369         (arch_sh2e_up): Accomodate above changes.
 370         (arch_sh2_up): Ditto.
 371         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 372         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 373         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 374         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 375         * sh-opc.h (arch_sh2a_nofpu): New.
 376         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 377         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 378         instruction.
 379         2004-01-20  DJ Delorie  <dj@redhat.com>
 380         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 381         2003-12-29  DJ Delorie  <dj@redhat.com>
 382         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 383         sh_opcode_info, sh_table): Add sh2a support.
 384         (arch_op32): New, to tag 32-bit opcodes.
 385         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 386         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 387         * sh-opc.h (arch_sh2a): Add.
 388         * sh-dis.c (arch_sh2a): Handle.
 389         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 390
 391 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 392
 393         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 394
 395 2004-07-22  Nick Clifton  <nickc@redhat.com>
 396
 397         PR/280
 398         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 399         insns - this is done by objdump itself.
 400         * h8500-dis.c (print_insn_h8500): Likewise.
 401
 402 2004-07-21  Jan Beulich <jbeulich@novell.com>
 403
 404         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 405         regardless of address size prefix in effect.
 406         (ptr_reg): Size or address registers does not depend on rex64, but
 407         on the presence of an address size override.
 408         (OP_MMX): Use rex.x only for xmm registers.
 409         (OP_EM): Use rex.z only for xmm registers.
 410
 411 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 412
 413         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 414         move/branch operations to the bottom so that VR5400 multimedia
 415         instructions take precedence in disassembly.
 416
 417 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 418
 419         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 420         ISA-specific "break" encoding.
 421
 422 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 423
 424         * arm-opc.h: Fix typo in comment.
 425
 426 2004-07-11  Andreas Schwab  <schwab@suse.de>
 427
 428         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 429
 430 2004-07-09  Andreas Schwab  <schwab@suse.de>
 431
 432         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 433
 434 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 435
 436         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 437         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 438         (crx-dis.lo): New target.
 439         (crx-opc.lo): Likewise.
 440         * Makefile.in: Regenerate.
 441         * configure.in: Handle bfd_crx_arch.
 442         * configure: Regenerate.
 443         * crx-dis.c: New file.
 444         * crx-opc.c: New file.
 445         * disassemble.c (ARCH_crx): Define.
 446         (disassembler): Handle ARCH_crx.
 447
 448 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 449
 450         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 451         * ia64-asmtab.c: Regnerate.
 452
 453 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 454
 455         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 456         (extract_fxm): Don't test dialect.
 457         (XFXFXM_MASK): Include the power4 bit.
 458         (XFXM): Add p4 param.
 459         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 460
 461 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 462
 463         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 464         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 465
 466 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 467
 468         * ppc-opc.c (BH, XLBH_MASK): Define.
 469         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 470
 471 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 472
 473         * i386-dis.c (x_mode): Comment.
 474         (two_source_ops): File scope.
 475         (float_mem): Correct fisttpll and fistpll.
 476         (float_mem_mode): New table.
 477         (dofloat): Use it.
 478         (OP_E): Correct intel mode PTR output.
 479         (ptr_reg): Use open_char and close_char.
 480         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 481         operands.  Set two_source_ops.
 482
 483 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 484
 485         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 486         instead of _raw_size.
 487
 488 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 489
 490         * ia64-gen.c (in_iclass): Handle more postinc st
 491         and ld variants.
 492         * ia64-asmtab.c: Rebuilt.
 493
 494 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 495
 496         * s390-opc.txt: Correct architecture mask for some opcodes.
 497         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 498         in the esa mode as well.
 499
 500 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 501
 502         * sh-dis.c (target_arch): Make unsigned.
 503         (print_insn_sh): Replace (most of) switch with a call to
 504         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 505         * sh-opc.h: Redefine architecture flags values.
 506         Add sh3-nommu architecture.
 507         Reorganise <arch>_up macros so they make more visual sense.
 508         (SH_MERGE_ARCH_SET): Define new macro.
 509         (SH_VALID_BASE_ARCH_SET): Likewise.
 510         (SH_VALID_MMU_ARCH_SET): Likewise.
 511         (SH_VALID_CO_ARCH_SET): Likewise.
 512         (SH_VALID_ARCH_SET): Likewise.
 513         (SH_MERGE_ARCH_SET_VALID): Likewise.
 514         (SH_ARCH_SET_HAS_FPU): Likewise.
 515         (SH_ARCH_SET_HAS_DSP): Likewise.
 516         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 517         (sh_get_arch_from_bfd_mach): Add prototype.
 518         (sh_get_arch_up_from_bfd_mach): Likewise.
 519         (sh_get_bfd_mach_from_arch_set): Likewise.
 520         (sh_merge_bfd_arc): Likewise.
 521
 522 2004-05-24  Peter Barada  <peter@the-baradas.com>
 523
 524         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 525         into new match_insn_m68k function.  Loop over canidate
 526         matches and select first that completely matches.
 527         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 528         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 529         to verify addressing for MAC/EMAC.
 530         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 531         reigster halves since 'fpu' and 'spl' look misleading.
 532         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 533         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 534         first, tighten up match masks.
 535         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 536         'size' from special case code in print_insn_m68k to
 537         determine decode size of insns.
 538
 539 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 540
 541         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 542         well as when -mpower4.
 543
 544 2004-05-13  Nick Clifton  <nickc@redhat.com>
 545
 546         * po/fr.po: Updated French translation.
 547
 548 2004-05-05  Peter Barada  <peter@the-baradas.com>
 549
 550         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 551         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 552         * m68k-op.c: Switch from ColdFire chips to core variants.
 553
 554 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 555
 556         PR 147.
 557         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 558
 559 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 560
 561         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 562         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 563
 564 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 565
 566         * sh-dis.c (print_insn_sh): Print the value in constant pool
 567         as a symbol if it looks like a symbol.
 568
 569 2004-04-22  Peter Barada <peter@the-baradas.com>
 570
 571         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 572         appropriate ColdFire architectures.
 573         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 574         mask addressing.
 575         Add EMAC instructions, fix MAC instructions. Remove
 576         macmw/macml/msacmw/msacml instructions since mask addressing now
 577         supported.
 578
 579 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 580
 581         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 582         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 583         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 584         macro.  Adjust all users.
 585
 586 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 587
 588         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 589         separately.
 590
 591 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 592
 593         * m32r-asm.c: Regenerate.
 594
 595 2004-03-29  Stan Shebs  <shebs@apple.com>
 596
 597         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 598         used.
 599
 600 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 601
 602         * aclocal.m4: Regenerate.
 603         * config.in: Regenerate.
 604         * configure: Regenerate.
 605         * po/POTFILES.in: Regenerate.
 606         * po/opcodes.pot: Regenerate.
 607
 608 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 609
 610         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 611         PPC_OPERANDS_GPR_0.
 612         * ppc-opc.c (RA0): Define.
 613         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 614         (RAOPT): Rename from RAO.  Update all uses.
 615         (powerpc_opcodes): Use RA0 as appropriate.
 616
 617 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 618
 619         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 620
 621 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 622
 623         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 624
 625 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 626
 627         * i386-dis.c (GRPPLOCK): Delete.
 628         (grps): Delete GRPPLOCK entry.
 629
 630 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 631
 632         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 633         (M, Mp): Use OP_M.
 634         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 635         (GRPPADLCK): Define.
 636         (dis386): Use NOP_Fixup on "nop".
 637         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 638         (twobyte_has_modrm): Set for 0xa7.
 639         (padlock_table): Delete.  Move to..
 640         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 641         and clflush.
 642         (print_insn): Revert PADLOCK_SPECIAL code.
 643         (OP_E): Delete sfence, lfence, mfence checks.
 644
 645 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 646
 647         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 648         (INVLPG_Fixup): New function.
 649         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 650
 651 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 652
 653         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 654         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 655         (padlock_table): New struct with PadLock instructions.
 656         (print_insn): Handle PADLOCK_SPECIAL.
 657
 658 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 659
 660         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 661         (OP_E): Twiddle clflush to sfence here.
 662
 663 2004-03-08  Nick Clifton  <nickc@redhat.com>
 664
 665         * po/de.po: Updated German translation.
 666
 667 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 668
 669         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 670         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 671         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 672         accordingly.
 673
 674 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 675
 676         * frv-asm.c: Regenerate.
 677         * frv-desc.c: Regenerate.
 678         * frv-desc.h: Regenerate.
 679         * frv-dis.c: Regenerate.
 680         * frv-ibld.c: Regenerate.
 681         * frv-opc.c: Regenerate.
 682         * frv-opc.h: Regenerate.
 683
 684 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 685
 686         * frv-desc.c, frv-opc.c: Regenerate.
 687
 688 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 689
 690         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 691
 692 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 693
 694         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 695         Also correct mistake in the comment.
 696
 697 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 698
 699         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 700         ensure that double registers have even numbers.
 701         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 702         that reserved instruction 0xfffd does not decode the same
 703         as 0xfdfd (ftrv).
 704         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 705         REG_N refers to a double register.
 706         Add REG_N_B01 nibble type and use it instead of REG_NM
 707         in ftrv.
 708         Adjust the bit patterns in a few comments.
 709
 710 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 711
 712         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 713
 714 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 715
 716         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 717
 718 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 719
 720         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 721
 722 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 723
 724         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 725         mtivor32, mtivor33, mtivor34.
 726
 727 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 728
 729         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 730
 731 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 732
 733         * arm-opc.h Maverick accumulator register opcode fixes.
 734
 735 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 736
 737         * m32r-dis.c: Regenerate.
 738
 739 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 740
 741         * sh-opc.h (sh_table): "fsrra", not "fssra".
 742
 743 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 744
 745         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 746         contraints.
 747
 748 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 749
 750         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 751
 752 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 753
 754         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 755         1.  Don't print scale factor on AT&T mode when index missing.
 756
 757 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 758
 759         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 760         when loaded into XR registers.
 761
 762 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 763
 764         * frv-desc.h: Regenerate.
 765         * frv-desc.c: Regenerate.
 766         * frv-opc.c: Regenerate.
 767
 768 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 769
 770         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 771
 772 2004-01-09  Paul Brook  <paul@codesourcery.com>
 773
 774         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 775         specific opcodes.
 776
 777 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 778
 779         * Makefile.am (libopcodes_la_DEPENDENCIES)
 780         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 781         comment about the problem.
 782         * Makefile.in: Regenerate.
 783
 784 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 785
 786         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 787         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 788         cut&paste errors in shifting/truncating numerical operands.
 789         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 790         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 791         (parse_uslo16): Likewise.
 792         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 793         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 794         (parse_s12): Likewise.
 795         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 796         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 797         (parse_uslo16): Likewise.
 798         (parse_uhi16): Parse gothi and gotfuncdeschi.
 799         (parse_d12): Parse got12 and gotfuncdesc12.
 800         (parse_s12): Likewise.
 801
 802 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 803
 804         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 805         instruction which looks similar to an 'rla' instruction.
 806
 807 For older changes see ChangeLog-0203
 808 \f
 809 Local Variables:
 810 mode: change-log
 811 left-margin: 8
 812 fill-column: 74
 813 version-control: never
 814 End: