opcodes/ChangeLog

   1 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
   2
   3         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
   4
   5 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
   6             Faraz Shahbazker  <fshahbazker@wavecomp.com>
   7
   8         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
   9
  10 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
  11
  12         * s12z-opc.h: Add extern "C" bracketing to help
  13         users who wish to use this interface in c++ code.
  14
  15 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
  16
  17         * s12z-opc.c (bm_decode): Handle bit map operations with the
  18         "reserved0" mode.
  19
  20 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  21
  22         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
  23         specifier.  Add entries for VLDR and VSTR of system registers.
  24         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
  25         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
  26         of %J and %K format specifier.
  27
  28 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  29
  30         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
  31         Add new entries for VSCCLRM instruction.
  32         (print_insn_coprocessor): Handle new %C format control code.
  33
  34 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  35
  36         * arm-dis.c (enum isa): New enum.
  37         (struct sopcode32): New structure.
  38         (coprocessor_opcodes): change type of entries to struct sopcode32 and
  39         set isa field of all current entries to ANY.
  40         (print_insn_coprocessor): Change type of insn to struct sopcode32.
  41         Only match an entry if its isa field allows the current mode.
  42
  43 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  44
  45         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
  46         CLRM.
  47         (print_insn_thumb32): Add logic to print %n CLRM register list.
  48
  49 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  50
  51         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
  52         and %Q patterns.
  53
  54 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  55
  56         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
  57         (print_insn_thumb32): Edit the switch case for %Z.
  58
  59 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  60
  61         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
  62
  63 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  64
  65         * arm-dis.c (thumb32_opcodes): New instruction bfl.
  66
  67 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  68
  69         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
  70
  71 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  72
  73         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
  74         Arm register with r13 and r15 unpredictable.
  75         (thumb32_opcodes): New instructions for bfx and bflx.
  76
  77 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  78
  79         * arm-dis.c (thumb32_opcodes): New instructions for bf.
  80
  81 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  82
  83         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
  84
  85 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  86
  87         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
  88
  89 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  90
  91         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
  92
  93 2019-04-12  John Darrington <john@darrington.wattle.id.au>
  94
  95         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
  96         "optr". ("operator" is a reserved word in c++).
  97
  98 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
  99
 100         * aarch64-opc.c (aarch64_print_operand): Add case for
 101         AARCH64_OPND_Rt_SP.
 102         (verify_constraints): Likewise.
 103         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 104         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 105         to accept Rt|SP as first operand.
 106         (AARCH64_OPERANDS): Add new Rt_SP.
 107         * aarch64-asm-2.c: Regenerated.
 108         * aarch64-dis-2.c: Regenerated.
 109         * aarch64-opc-2.c: Regenerated.
 110
 111 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 112
 113         * aarch64-asm-2.c: Regenerated.
 114         * aarch64-dis-2.c: Likewise.
 115         * aarch64-opc-2.c: Likewise.
 116         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 117
 118 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 119
 120         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 121
 122 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 123
 124         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 125         * i386-init.h: Regenerated.
 126
 127 2019-04-07  Alan Modra  <amodra@gmail.com>
 128
 129         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 130         op_separator to control printing of spaces, comma and parens
 131         rather than need_comma, need_paren and spaces vars.
 132
 133 2019-04-07  Alan Modra  <amodra@gmail.com>
 134
 135         PR 24421
 136         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 137         (print_insn_neon, print_insn_arm): Likewise.
 138
 139 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 140
 141         * i386-dis-evex.h (evex_table): Updated to support BF16
 142         instructions.
 143         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 144         and EVEX_W_0F3872_P_3.
 145         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 146         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 147         * i386-opc.h (enum): Add CpuAVX512_BF16.
 148         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 149         * i386-opc.tbl: Add AVX512 BF16 instructions.
 150         * i386-init.h: Regenerated.
 151         * i386-tbl.h: Likewise.
 152
 153 2019-04-05  Alan Modra  <amodra@gmail.com>
 154
 155         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 156         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 157         to favour printing of "-" branch hint when using the "y" bit.
 158         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 159
 160 2019-04-05  Alan Modra  <amodra@gmail.com>
 161
 162         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 163         opcode until first operand is output.
 164
 165 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 166
 167         PR gas/24349
 168         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 169         (valid_bo_post_v2): Add support for 'at' branch hints.
 170         (insert_bo): Only error on branch on ctr.
 171         (get_bo_hint_mask): New function.
 172         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 173         for inserting 'at' branch hints.
 174         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 175         for extracting 'at' branch hints.
 176         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 177         (BOE): Delete operand.
 178         (BOM, BOP): New operands.
 179         (RM): Update value.
 180         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 181         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 182         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 183         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 184         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 185         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 186         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 187         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 188         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 189         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 190         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 191         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 192         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 193         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 194         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 195         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 196         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 197         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 198         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 199         bttarl+>: New extended mnemonics.
 200
 201 2019-03-28  Alan Modra  <amodra@gmail.com>
 202
 203         PR 24390
 204         * ppc-opc.c (BTF): Define.
 205         (powerpc_opcodes): Use for mtfsb*.
 206         * ppc-dis.c (print_insn_powerpc): Print fields with both
 207         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 208
 209 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 210
 211         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 212         (mapping_symbol_for_insn): Implement new algorithm.
 213         (print_insn): Remove duplicate code.
 214
 215 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 216
 217         * aarch64-dis.c (print_insn_aarch64):
 218         Implement override.
 219
 220 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 221
 222         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 223         order.
 224
 225 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 226
 227         * aarch64-dis.c (last_stop_offset): New.
 228         (print_insn_aarch64): Use stop_offset.
 229
 230 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         PR gas/24359
 233         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 234         CPU_ANY_AVX2_FLAGS.
 235         * i386-init.h: Regenerated.
 236
 237 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 238
 239         PR gas/24348
 240         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 241         vmovdqu16, vmovdqu32 and vmovdqu64.
 242         * i386-tbl.h: Regenerated.
 243
 244 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 245
 246         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 247         from vstrszb, vstrszh, and vstrszf.
 248
 249 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 250
 251         * s390-opc.txt: Add instruction descriptions.
 252
 253 2019-02-08  Jim Wilson  <jimw@sifive.com>
 254
 255         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 256         <bne>: Likewise.
 257
 258 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 259
 260         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 261
 262 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 263
 264         PR binutils/23212
 265         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 266         * aarch64-opc.c (verify_elem_sd): New.
 267         (fields): Add FLD_sz entr.
 268         * aarch64-tbl.h (_SIMD_INSN): New.
 269         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 270         fmulx scalar and vector by element isns.
 271
 272 2019-02-07  Nick Clifton  <nickc@redhat.com>
 273
 274         * po/sv.po: Updated Swedish translation.
 275
 276 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 277
 278         * s390-mkopc.c (main): Accept arch13 as cpu string.
 279         * s390-opc.c: Add new instruction formats and instruction opcode
 280         masks.
 281         * s390-opc.txt: Add new arch13 instructions.
 282
 283 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 284
 285         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 286         (aarch64_opcode): Change encoding for stg, stzg
 287         st2g and st2zg.
 288         * aarch64-asm-2.c: Regenerated.
 289         * aarch64-dis-2.c: Regenerated.
 290         * aarch64-opc-2.c: Regenerated.
 291
 292 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 293
 294         * aarch64-asm-2.c: Regenerated.
 295         * aarch64-dis-2.c: Likewise.
 296         * aarch64-opc-2.c: Likewise.
 297         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 298
 299 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 300             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 301
 302         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 303         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 304         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 305         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 306         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 307         case for ldstgv_indexed.
 308         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 309         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 310         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 311         * aarch64-asm-2.c: Regenerated.
 312         * aarch64-dis-2.c: Regenerated.
 313         * aarch64-opc-2.c: Regenerated.
 314
 315 2019-01-23  Nick Clifton  <nickc@redhat.com>
 316
 317         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 318
 319 2019-01-21  Nick Clifton  <nickc@redhat.com>
 320
 321         * po/de.po: Updated German translation.
 322         * po/uk.po: Updated Ukranian translation.
 323
 324 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 325         * mips-dis.c (mips_arch_choices): Fix typo in
 326         gs464, gs464e and gs264e descriptors.
 327
 328 2019-01-19  Nick Clifton  <nickc@redhat.com>
 329
 330         * configure: Regenerate.
 331         * po/opcodes.pot: Regenerate.
 332
 333 2018-06-24  Nick Clifton  <nickc@redhat.com>
 334
 335         2.32 branch created.
 336
 337 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 338
 339         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 340         if it is null.
 341         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 342         zero.
 343
 344 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 345
 346         * configure: Regenerate.
 347
 348 2019-01-07  Alan Modra  <amodra@gmail.com>
 349
 350         * configure: Regenerate.
 351         * po/POTFILES.in: Regenerate.
 352
 353 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 354
 355         * s12z-opc.c: New file.
 356         * s12z-opc.h: New file.
 357         * s12z-dis.c: Removed all code not directly related to display
 358         of instructions.  Used the interface provided by the new files
 359         instead.
 360         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 361         * Makefile.in: Regenerate.
 362         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 363         * configure: Regenerate.
 364
 365 2019-01-01  Alan Modra  <amodra@gmail.com>
 366
 367         Update year range in copyright notice of all files.
 368
 369 For older changes see ChangeLog-2018
 370 \f
 371 Copyright (C) 2019 Free Software Foundation, Inc.
 372
 373 Copying and distribution of this file, with or without modification,
 374 are permitted in any medium without royalty provided the copyright
 375 notice and this notice are preserved.
 376
 377 Local Variables:
 378 mode: change-log
 379 left-margin: 8
 380 fill-column: 74
 381 version-control: never
 382 End: