opcodes/ChangeLog

   1 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
   2
   3         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
   4         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
   5
   6 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
   7
   8         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
   9         and AARCH64_FEATURE_F16.
  10
  11 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  12
  13         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
  14         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
  15         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
  16         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
  17         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
  18         (ldapur, ldapursw, stlur): New.
  19         * aarch64-dis-2.c: Regenerate.
  20
  21 2017-11-16  Jan Beulich  <jbeulich@suse.com>
  22
  23         (get_valid_dis386): Never flag bad opcode when
  24         vex.register_specifier is beyond 7. Always store all four
  25         bits of it. Move 16-/32-bit override in EVEX handling after
  26         all to be overridden bits have been set.
  27         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
  28         Use rex to determine GPR register set.
  29         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
  30         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
  31
  32 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
  35         determine GPR register set.
  36
  37 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  38
  39         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
  40         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
  41         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
  42         pass.
  43         (OP_REG_VexI4): Drop low 4 bits check.
  44
  45 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-reg.tbl (axl): Remove Acc and Byte.
  48         * i386-tbl.h: Re-generate.
  49
  50 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
  53         (vex_len_table): Use VPCOM.
  54
  55 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
  58         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
  59         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
  60         vpcmpw): Move up.
  61         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
  62         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
  63         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
  64         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
  65         vpcmpnltuw): New.
  66         * i386-tbl.h: Re-generate.
  67
  68 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
  71         smov, ssca, stos, ssto, xlat): Drop Disp*.
  72         * i386-tbl.h: Re-generate.
  73
  74 2017-11-13  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
  77         xsaveopt64): Add No_qSuf.
  78         * i386-tbl.h: Re-generate.
  79
  80 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  81
  82         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
  83         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
  84         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
  85         sder32_el2, vncr_el2.
  86         (aarch64_sys_reg_supported_p): Likewise.
  87         (aarch64_pstatefields): Add dit register.
  88         (aarch64_pstatefield_supported_p): Likewise.
  89         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
  90         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
  91         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
  92         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
  93         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
  94         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
  95         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
  96
  97 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  98
  99         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 100         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 101         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 102         (QL_STLW, QL_STLX): New.
 103
 104 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 105
 106         * aarch64-asm.h (ins_addr_offset): New.
 107         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 108         (aarch64_ins_addr_offset): New.
 109         * aarch64-asm-2.c: Regenerate.
 110         * aarch64-dis.h (ext_addr_offset): New.
 111         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 112         (aarch64_ext_addr_offset): New.
 113         * aarch64-dis-2.c: Regenerate.
 114         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 115         FLD_imm4_2 and FLD_SM3_imm2.
 116         * aarch64-opc.c (fields): Add FLD_imm6_2,
 117         FLD_imm4_2 and FLD_SM3_imm2.
 118         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 119         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 120         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 121         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 122         * aarch64-tbl.h
 123         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 124
 125 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 126
 127         * aarch64-tbl.h
 128         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 129         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 130         (aarch64_feature_fp_16_v8_2): New.
 131         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 132         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 133         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 134
 135 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 136
 137         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 138         (aarch64_feature_sha2, aarch64_feature_aes): New.
 139         (SHA2, AES): New.
 140         (AES_INSN, SHA2_INSN): New.
 141         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 142         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 143          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 144         Change to SHA2_INS.
 145
 146 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 147             Tamar Christina <tamar.christina@arm.com>
 148
 149         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 150         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 151
 152 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 153
 154         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 155
 156 2017-11-07  Alan Modra  <amodra@gmail.com>
 157
 158         * opintl.h: Formatting, comment fixes.
 159         (gettext, ngettext): Redefine when ENABLE_NLS.
 160         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 161         (_): Define using gettext.
 162         (textdomain, bindtextdomain): Use safer "do nothing".
 163
 164 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 165
 166         * arc-dis.c (print_hex): New variable.
 167         (parse_option): Check for hex option.
 168         (print_insn_arc): Use hexadecimal representation for short
 169         immediate values when requested.
 170         (print_arc_disassembler_options): Add hex option to the list.
 171
 172 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 173
 174         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 175         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 176         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 177         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 178         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 179         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 180         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 181         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 182         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 183         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 184         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 185         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 186         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 187         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 188         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 189         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 190         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 191         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 192         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 193         Changed opcodes.
 194         (prealloc, prefetch*): Place them before ld instruction.
 195         * arc-opc.c (skip_this_opcode): Add ARITH class.
 196
 197 2017-10-25  Alan Modra  <amodra@gmail.com>
 198
 199         PR 22348
 200         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 201         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 202         (imm4flag, size_changed): Likewise.
 203         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 204         (words, allWords, processing_argument_number): Likewise.
 205         (cst4flag, size_changed): Likewise.
 206         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 207         (crx_cst4_maps): Rename from cst4_maps.
 208         (crx_no_op_insn): Rename from no_op_insn.
 209
 210 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 211
 212         * riscv-opc.c (match_c_addi16sp) : New function.
 213         (match_c_addi4spn): New function.
 214         (match_c_lui): Don't allow 0-immediate encodings.
 215         (riscv_opcodes) <addi>: Use the above functions.
 216         <add>: Likewise.
 217         <c.addi4spn>: Likewise.
 218         <c.addi16sp>: Likewise.
 219
 220 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 221
 222         * i386-init.h: Regenerate
 223         * i386-tbl.h: Likewise
 224
 225 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 226
 227         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 228         (enum): Add EVEX_W_0F3854_P_2.
 229         * i386-dis-evex.h (evex_table): Updated.
 230         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 231         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 232         (cpu_flags): Add CpuAVX512_BITALG.
 233         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 234         (i386_cpu_flags): Add cpuavx512_bitalg..
 235         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 236         * i386-init.h: Regenerate.
 237         * i386-tbl.h: Likewise.
 238
 239 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 240
 241         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 242         * i386-dis-evex.h (evex_table): Updated.
 243         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 244         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 245         (cpu_flags): Add CpuAVX512_VNNI.
 246         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 247         (i386_cpu_flags): Add cpuavx512_vnni.
 248         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 249         * i386-init.h: Regenerate.
 250         * i386-tbl.h: Likewise.
 251
 252 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 253
 254         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 255         (enum): Remove VEX_LEN_0F3A44_P_2.
 256         (vex_len_table): Ditto.
 257         (enum): Remove VEX_W_0F3A44_P_2.
 258         (vew_w_table): Ditto.
 259         (prefix_table): Adjust instructions (see prefixes above).
 260         * i386-dis-evex.h (evex_table):
 261         Add new instructions (see prefixes above).
 262         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 263         (bitfield_cpu_flags): Ditto.
 264         * i386-opc.h (enum): Ditto.
 265         (i386_cpu_flags): Ditto.
 266         (CpuUnused): Comment out to avoid zero-width field problem.
 267         * i386-opc.tbl (vpclmulqdq): New instruction.
 268         * i386-init.h: Regenerate.
 269         * i386-tbl.h: Ditto.
 270
 271 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 272
 273         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 274         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 275         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 276         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 277         (vex_len_table): Ditto.
 278         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 279         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 280         (vew_w_table): Ditto.
 281         (prefix_table): Adjust instructions (see prefixes above).
 282         * i386-dis-evex.h (evex_table):
 283         Add new instructions (see prefixes above).
 284         * i386-gen.c (cpu_flag_init): Add VAES.
 285         (bitfield_cpu_flags): Ditto.
 286         * i386-opc.h (enum): Ditto.
 287         (i386_cpu_flags): Ditto.
 288         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 289         * i386-init.h: Regenerate.
 290         * i386-tbl.h: Ditto.
 291
 292 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 293
 294         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 295         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 296         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 297         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 298         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 299         (prefix_table): Updated (see prefixes above).
 300         (three_byte_table): Likewise.
 301         (vex_w_table): Likewise.
 302         * i386-dis-evex.h: Likewise.
 303         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 304         (cpu_flags): Add CpuGFNI.
 305         * i386-opc.h (enum): Add CpuGFNI.
 306         (i386_cpu_flags): Add cpugfni.
 307         * i386-opc.tbl: Add Intel GFNI instructions.
 308         * i386-init.h: Regenerate.
 309         * i386-tbl.h: Likewise.
 310
 311 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 312
 313         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 314         Define EXbScalar and EXwScalar for OP_EX.
 315         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 316         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 317         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 318         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 319         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 320         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 321         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 322         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 323         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 324         (OP_E_memory): Likewise.
 325         * i386-dis-evex.h: Updated.
 326         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 327         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 328         (cpu_flags): Add CpuAVX512_VBMI2.
 329         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 330         (i386_cpu_flags): Add cpuavx512_vbmi2.
 331         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 332         * i386-init.h: Regenerate.
 333         * i386-tbl.h: Likewise.
 334
 335 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 336
 337         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 338
 339 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 340
 341         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 342         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 343         K15. Add jmpix pattern.
 344
 345 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 346
 347         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 348
 349 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 350
 351         * s390-opc.c (INSTR_SI_RD): New macro.
 352         (INSTR_S_RD): Adjust example instruction.
 353         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 354         SI_RD.
 355
 356 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 357
 358         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 359         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 360         VLE multimple load/store instructions. Old e_ldm* variants are
 361         kept as aliases.
 362         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 363
 364 2017-09-27  Nick Clifton  <nickc@redhat.com>
 365
 366         PR 22179
 367         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 368         names for the fmv.x.s and fmv.s.x instructions respectively.
 369
 370 2017-09-26  do  <do@nerilex.org>
 371
 372         PR 22123
 373         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 374         be used on CPUs that have emacs support.
 375
 376 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 377
 378         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 379
 380 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 381
 382         * nds32-asm.c: Rename __BIT() to N32_BIT().
 383         * nds32-asm.h: Likewise.
 384         * nds32-dis.c: Likewise.
 385
 386 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 387
 388         * i386-dis.c (last_active_prefix): Removed.
 389         (ckprefix): Don't set last_active_prefix.
 390         (NOTRACK_Fixup): Don't check last_active_prefix.
 391
 392 2017-08-31  Nick Clifton  <nickc@redhat.com>
 393
 394         * po/fr.po: Updated French translation.
 395
 396 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 397
 398         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 399         fields.
 400
 401 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 402             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 403
 404         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 405         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 406         New entries efs2 and spe2.
 407         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 408         (SPE2_OPCD_SEGS): New macro.
 409         (spe2_opcd_indices): New.
 410         (disassemble_init_powerpc): Handle SPE2 opcodes.
 411         (lookup_spe2): New function.
 412         (print_insn_powerpc): call lookup_spe2.
 413         * ppc-opc.c (insert_evuimm1_ex0): New function.
 414         (extract_evuimm1_ex0): Likewise.
 415         (insert_evuimm_lt8): Likewise.
 416         (extract_evuimm_lt8): Likewise.
 417         (insert_off_spe2): Likewise.
 418         (extract_off_spe2): Likewise.
 419         (insert_Ddd): Likewise.
 420         (extract_Ddd): Likewise.
 421         (DD): New operand.
 422         (EVUIMM_LT8): Likewise.
 423         (EVUIMM_LT16): Adjust.
 424         (MMMM): New operand.
 425         (EVUIMM_1): Likewise.
 426         (EVUIMM_1_EX0): Likewise.
 427         (EVUIMM_2): Adjust.
 428         (NNN): New operand.
 429         (VX_OFF_SPE2): Likewise.
 430         (BBB): Likewise.
 431         (DDD): Likewise.
 432         (VX_MASK_DDD): New mask.
 433         (HH): New operand.
 434         (VX_RA_CONST): New macro.
 435         (VX_RA_CONST_MASK): Likewise.
 436         (VX_RB_CONST): Likewise.
 437         (VX_RB_CONST_MASK): Likewise.
 438         (VX_OFF_SPE2_MASK): Likewise.
 439         (VX_SPE_CRFD): Likewise.
 440         (VX_SPE_CRFD_MASK VX): Likewise.
 441         (VX_SPE2_CLR): Likewise.
 442         (VX_SPE2_CLR_MASK): Likewise.
 443         (VX_SPE2_SPLATB): Likewise.
 444         (VX_SPE2_SPLATB_MASK): Likewise.
 445         (VX_SPE2_OCTET): Likewise.
 446         (VX_SPE2_OCTET_MASK): Likewise.
 447         (VX_SPE2_DDHH): Likewise.
 448         (VX_SPE2_DDHH_MASK): Likewise.
 449         (VX_SPE2_HH): Likewise.
 450         (VX_SPE2_HH_MASK): Likewise.
 451         (VX_SPE2_EVMAR): Likewise.
 452         (VX_SPE2_EVMAR_MASK): Likewise.
 453         (PPCSPE2): Likewise.
 454         (PPCEFS2): Likewise.
 455         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 456         (powerpc_macros): Map old SPE instructions have new names
 457         with the same opcodes. Add SPE2 instructions which just are
 458         mapped to SPE2.
 459         (spe2_opcodes): Add SPE2 opcodes.
 460
 461 2017-08-23  Alan Modra  <amodra@gmail.com>
 462
 463         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 464         extract functions earlier, deleting forward declarations.
 465         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 466         RA_MASK.
 467
 468 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 469
 470         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 471
 472 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 473             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 474
 475         * ppc-opc.c (insert_evuimm2_ex0): New function.
 476         (extract_evuimm2_ex0): Likewise.
 477         (insert_evuimm4_ex0): Likewise.
 478         (extract_evuimm4_ex0): Likewise.
 479         (insert_evuimm8_ex0): Likewise.
 480         (extract_evuimm8_ex0): Likewise.
 481         (insert_evuimm_lt16): Likewise.
 482         (extract_evuimm_lt16): Likewise.
 483         (insert_rD_rS_even): Likewise.
 484         (extract_rD_rS_even): Likewise.
 485         (insert_off_lsp): Likewise.
 486         (extract_off_lsp): Likewise.
 487         (RD_EVEN): New operand.
 488         (RS_EVEN): Likewise.
 489         (RSQ): Adjust.
 490         (EVUIMM_LT16): New operand.
 491         (HTM_SI): Adjust.
 492         (EVUIMM_2_EX0): New operand.
 493         (EVUIMM_4): Adjust.
 494         (EVUIMM_4_EX0): New operand.
 495         (EVUIMM_8): Adjust.
 496         (EVUIMM_8_EX0): New operand.
 497         (WS): Adjust.
 498         (VX_OFF): New operand.
 499         (VX_LSP): New macro.
 500         (VX_LSP_MASK): Likewise.
 501         (VX_LSP_OFF_MASK): Likewise.
 502         (PPC_OPCODE_LSP): Likewise.
 503         (vle_opcodes): Add LSP opcodes.
 504         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 505
 506 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 507
 508         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 509         register operands in CRC instructions.
 510         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 511         comments.
 512
 513 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 514
 515         * disassemble.c (disassembler): Mark big and mach with
 516         ATTRIBUTE_UNUSED.
 517
 518 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 519
 520         * disassemble.c (disassembler): Remove arch/mach/endian
 521         assertions.
 522
 523 2017-07-25  Nick Clifton  <nickc@redhat.com>
 524
 525         PR 21739
 526         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 527         message.
 528         (insert_r0): Likewise.
 529         (insert_r1): Likewise.
 530         (insert_r2): Likewise.
 531         (insert_r3): Likewise.
 532         (insert_sp): Likewise.
 533         (insert_gp): Likewise.
 534         (insert_pcl): Likewise.
 535         (insert_blink): Likewise.
 536         (insert_ilink1): Likewise.
 537         (insert_ilink2): Likewise.
 538         (insert_ras): Likewise.
 539         (insert_rbs): Likewise.
 540         (insert_rcs): Likewise.
 541         (insert_simm3s): Likewise.
 542         (insert_rrange): Likewise.
 543         (insert_r13el): Likewise.
 544         (insert_fpel): Likewise.
 545         (insert_blinkel): Likewise.
 546         (insert_pclel): Likewise.
 547         (insert_nps_bitop_size_2b): Likewise.
 548         (insert_nps_imm_offset): Likewise.
 549         (insert_nps_imm_entry): Likewise.
 550         (insert_nps_size_16bit): Likewise.
 551         (insert_nps_##NAME##_pos): Likewise.
 552         (insert_nps_##NAME): Likewise.
 553         (insert_nps_bitop_ins_ext): Likewise.
 554         (insert_nps_##NAME): Likewise.
 555         (insert_nps_min_hofs): Likewise.
 556         (insert_nps_##NAME): Likewise.
 557         (insert_nps_rbdouble_64): Likewise.
 558         (insert_nps_misc_imm_offset): Likewise.
 559         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 560         option description.
 561
 562 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 563             Jiong Wang  <jiong.wang@arm.com>
 564
 565         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 566         correct the print.
 567         * aarch64-dis-2.c: Regenerated.
 568
 569 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 570
 571         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 572         table.
 573
 574 2017-07-20  Nick Clifton  <nickc@redhat.com>
 575
 576         * po/de.po: Updated German translation.
 577
 578 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 579
 580         * arc-regs.h (sec_stat): New aux register.
 581         (aux_kernel_sp): Likewise.
 582         (aux_sec_u_sp): Likewise.
 583         (aux_sec_k_sp): Likewise.
 584         (sec_vecbase_build): Likewise.
 585         (nsc_table_top): Likewise.
 586         (nsc_table_base): Likewise.
 587         (ersec_stat): Likewise.
 588         (aux_sec_except): Likewise.
 589
 590 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 591
 592         * arc-opc.c (extract_uimm12_20): New function.
 593         (UIMM12_20): New operand.
 594         (SIMM3_5_S): Adjust.
 595         * arc-tbl.h (sjli): Add new instruction.
 596
 597 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 598             John Eric Martin  <John.Martin@emmicro-us.com>
 599
 600         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 601         (UIMM3_23): Adjust accordingly.
 602         * arc-regs.h: Add/correct jli_base register.
 603         * arc-tbl.h (jli_s): Likewise.
 604
 605 2017-07-18  Nick Clifton  <nickc@redhat.com>
 606
 607         PR 21775
 608         * aarch64-opc.c: Fix spelling typos.
 609         * i386-dis.c: Likewise.
 610
 611 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 612
 613         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 614         max_addr_offset and octets variables to size_t.
 615
 616 2017-07-12  Alan Modra  <amodra@gmail.com>
 617
 618         * po/da.po: Update from translationproject.org/latest/opcodes/.
 619         * po/de.po: Likewise.
 620         * po/es.po: Likewise.
 621         * po/fi.po: Likewise.
 622         * po/fr.po: Likewise.
 623         * po/id.po: Likewise.
 624         * po/it.po: Likewise.
 625         * po/nl.po: Likewise.
 626         * po/pt_BR.po: Likewise.
 627         * po/ro.po: Likewise.
 628         * po/sv.po: Likewise.
 629         * po/tr.po: Likewise.
 630         * po/uk.po: Likewise.
 631         * po/vi.po: Likewise.
 632         * po/zh_CN.po: Likewise.
 633
 634 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 635             Alan Modra  <amodra@gmail.com>
 636
 637         * cgen.sh: Mark generated files read-only.
 638         * epiphany-asm.c: Regenerate.
 639         * epiphany-desc.c: Regenerate.
 640         * epiphany-desc.h: Regenerate.
 641         * epiphany-dis.c: Regenerate.
 642         * epiphany-ibld.c: Regenerate.
 643         * epiphany-opc.c: Regenerate.
 644         * epiphany-opc.h: Regenerate.
 645         * fr30-asm.c: Regenerate.
 646         * fr30-desc.c: Regenerate.
 647         * fr30-desc.h: Regenerate.
 648         * fr30-dis.c: Regenerate.
 649         * fr30-ibld.c: Regenerate.
 650         * fr30-opc.c: Regenerate.
 651         * fr30-opc.h: Regenerate.
 652         * frv-asm.c: Regenerate.
 653         * frv-desc.c: Regenerate.
 654         * frv-desc.h: Regenerate.
 655         * frv-dis.c: Regenerate.
 656         * frv-ibld.c: Regenerate.
 657         * frv-opc.c: Regenerate.
 658         * frv-opc.h: Regenerate.
 659         * ip2k-asm.c: Regenerate.
 660         * ip2k-desc.c: Regenerate.
 661         * ip2k-desc.h: Regenerate.
 662         * ip2k-dis.c: Regenerate.
 663         * ip2k-ibld.c: Regenerate.
 664         * ip2k-opc.c: Regenerate.
 665         * ip2k-opc.h: Regenerate.
 666         * iq2000-asm.c: Regenerate.
 667         * iq2000-desc.c: Regenerate.
 668         * iq2000-desc.h: Regenerate.
 669         * iq2000-dis.c: Regenerate.
 670         * iq2000-ibld.c: Regenerate.
 671         * iq2000-opc.c: Regenerate.
 672         * iq2000-opc.h: Regenerate.
 673         * lm32-asm.c: Regenerate.
 674         * lm32-desc.c: Regenerate.
 675         * lm32-desc.h: Regenerate.
 676         * lm32-dis.c: Regenerate.
 677         * lm32-ibld.c: Regenerate.
 678         * lm32-opc.c: Regenerate.
 679         * lm32-opc.h: Regenerate.
 680         * lm32-opinst.c: Regenerate.
 681         * m32c-asm.c: Regenerate.
 682         * m32c-desc.c: Regenerate.
 683         * m32c-desc.h: Regenerate.
 684         * m32c-dis.c: Regenerate.
 685         * m32c-ibld.c: Regenerate.
 686         * m32c-opc.c: Regenerate.
 687         * m32c-opc.h: Regenerate.
 688         * m32r-asm.c: Regenerate.
 689         * m32r-desc.c: Regenerate.
 690         * m32r-desc.h: Regenerate.
 691         * m32r-dis.c: Regenerate.
 692         * m32r-ibld.c: Regenerate.
 693         * m32r-opc.c: Regenerate.
 694         * m32r-opc.h: Regenerate.
 695         * m32r-opinst.c: Regenerate.
 696         * mep-asm.c: Regenerate.
 697         * mep-desc.c: Regenerate.
 698         * mep-desc.h: Regenerate.
 699         * mep-dis.c: Regenerate.
 700         * mep-ibld.c: Regenerate.
 701         * mep-opc.c: Regenerate.
 702         * mep-opc.h: Regenerate.
 703         * mt-asm.c: Regenerate.
 704         * mt-desc.c: Regenerate.
 705         * mt-desc.h: Regenerate.
 706         * mt-dis.c: Regenerate.
 707         * mt-ibld.c: Regenerate.
 708         * mt-opc.c: Regenerate.
 709         * mt-opc.h: Regenerate.
 710         * or1k-asm.c: Regenerate.
 711         * or1k-desc.c: Regenerate.
 712         * or1k-desc.h: Regenerate.
 713         * or1k-dis.c: Regenerate.
 714         * or1k-ibld.c: Regenerate.
 715         * or1k-opc.c: Regenerate.
 716         * or1k-opc.h: Regenerate.
 717         * or1k-opinst.c: Regenerate.
 718         * xc16x-asm.c: Regenerate.
 719         * xc16x-desc.c: Regenerate.
 720         * xc16x-desc.h: Regenerate.
 721         * xc16x-dis.c: Regenerate.
 722         * xc16x-ibld.c: Regenerate.
 723         * xc16x-opc.c: Regenerate.
 724         * xc16x-opc.h: Regenerate.
 725         * xstormy16-asm.c: Regenerate.
 726         * xstormy16-desc.c: Regenerate.
 727         * xstormy16-desc.h: Regenerate.
 728         * xstormy16-dis.c: Regenerate.
 729         * xstormy16-ibld.c: Regenerate.
 730         * xstormy16-opc.c: Regenerate.
 731         * xstormy16-opc.h: Regenerate.
 732
 733 2017-07-07  Alan Modra  <amodra@gmail.com>
 734
 735         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 736         * m32c-dis.c: Regenerate.
 737         * mep-dis.c: Regenerate.
 738
 739 2017-07-05  Borislav Petkov  <bp@suse.de>
 740
 741         * i386-dis.c: Enable ModRM.reg /6 aliases.
 742
 743 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 744
 745         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 746         with vmrs and vmsr.
 747
 748 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 749
 750         * configure: Regenerate.
 751
 752 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 753
 754         * po/opcodes.pot: Regenerate.
 755
 756 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 757
 758         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 759         entries to the MSA ASE instruction block.
 760
 761 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 762             Maciej W. Rozycki  <macro@imgtec.com>
 763
 764         * micromips-opc.c (XPA, XPAVZ): New macros.
 765         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 766         "mthgc0".
 767
 768 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 769             Maciej W. Rozycki  <macro@imgtec.com>
 770
 771         * micromips-opc.c (I36): New macro.
 772         (micromips_opcodes): Add "eretnc".
 773
 774 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 775             Andrew Bennett  <andrew.bennett@imgtec.com>
 776
 777         * mips-dis.c (mips_calculate_combination_ases): Handle the
 778         ASE_XPA_VIRT flag.
 779         (parse_mips_ase_option): New function.
 780         (parse_mips_dis_option): Factor out ASE option handling to the
 781         new function.  Call `mips_calculate_combination_ases'.
 782         * mips-opc.c (XPAVZ): New macro.
 783         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 784         "mfhgc0", "mthc0" and "mthgc0".
 785
 786 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 787
 788         * mips-dis.c (mips_calculate_combination_ases): New function.
 789         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 790         calculation to the new function.
 791         (set_default_mips_dis_options): Call the new function.
 792
 793 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 794
 795         * arc-dis.c (parse_disassembler_options): Use
 796         FOR_EACH_DISASSEMBLER_OPTION.
 797
 798 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 799
 800         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 801         disassembler option strings.
 802         (parse_cpu_option): Likewise.
 803
 804 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 805
 806         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 807         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 808         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 809         (aarch64_feature_dotprod, DOT_INSN): New.
 810         (udot, sdot): New.
 811         * aarch64-dis-2.c: Regenerated.
 812
 813 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 814
 815         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 816
 817 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 818             Matthew Fortune  <matthew.fortune@imgtec.com>
 819             Andrew Bennett  <andrew.bennett@imgtec.com>
 820
 821         * mips-formats.h (INT_BIAS): New macro.
 822         (INT_ADJ): Redefine in INT_BIAS terms.
 823         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 824         (mips_print_save_restore): New function.
 825         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 826         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 827         call.
 828         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 829         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 830         OP_SAVE_RESTORE_LIST handling, factored out from here.
 831         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 832         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 833         (mips_builtin_opcodes): Add "restore" and "save" entries.
 834         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 835         (IAMR2): New macro.
 836         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 837
 838 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 839
 840         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 841         alias; do not mark SLTI instruction as an alias.
 842
 843 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 844
 845         * i386-dis.c (RM_0FAE_REG_5): Removed.
 846         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 847         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 848         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 849         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 850         PREFIX_MOD_3_0F01_REG_5_RM_0.
 851         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 852         PREFIX_MOD_3_0FAE_REG_5.
 853         (mod_table): Update MOD_0FAE_REG_5.
 854         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 855         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 856         * i386-tbl.h: Regenerated.
 857
 858 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 859
 860         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 861         * i386-opc.tbl: Likewise.
 862         * i386-tbl.h: Regenerated.
 863
 864 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 865
 866         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 867         and "jmp{&|}".
 868         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 869         prefix.
 870
 871 2017-06-19  Nick Clifton  <nickc@redhat.com>
 872
 873         PR binutils/21614
 874         * score-dis.c (score_opcodes): Add sentinel.
 875
 876 2017-06-16  Alan Modra  <amodra@gmail.com>
 877
 878         * rx-decode.c: Regenerate.
 879
 880 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 881
 882         PR binutils/21594
 883         * i386-dis.c (OP_E_register): Check valid bnd register.
 884         (OP_G): Likewise.
 885
 886 2017-06-15  Nick Clifton  <nickc@redhat.com>
 887
 888         PR binutils/21595
 889         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 890         range value.
 891
 892 2017-06-15  Nick Clifton  <nickc@redhat.com>
 893
 894         PR binutils/21588
 895         * rl78-decode.opc (OP_BUF_LEN): Define.
 896         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 897         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 898         array.
 899         * rl78-decode.c: Regenerate.
 900
 901 2017-06-15  Nick Clifton  <nickc@redhat.com>
 902
 903         PR binutils/21586
 904         * bfin-dis.c (gregs): Clip index to prevent overflow.
 905         (regs): Likewise.
 906         (regs_lo): Likewise.
 907         (regs_hi): Likewise.
 908
 909 2017-06-14  Nick Clifton  <nickc@redhat.com>
 910
 911         PR binutils/21576
 912         * score7-dis.c (score_opcodes): Add sentinel.
 913
 914 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 915
 916         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 917         * arm-dis.c: Likewise.
 918         * ia64-dis.c: Likewise.
 919         * mips-dis.c: Likewise.
 920         * spu-dis.c: Likewise.
 921         * disassemble.h (print_insn_aarch64): New declaration, moved from
 922         include/dis-asm.h.
 923         (print_insn_big_arm, print_insn_big_mips): Likewise.
 924         (print_insn_i386, print_insn_ia64): Likewise.
 925         (print_insn_little_arm, print_insn_little_mips): Likewise.
 926
 927 2017-06-14  Nick Clifton  <nickc@redhat.com>
 928
 929         PR binutils/21587
 930         * rx-decode.opc: Include libiberty.h
 931         (GET_SCALE): New macro - validates access to SCALE array.
 932         (GET_PSCALE): New macro - validates access to PSCALE array.
 933         (DIs, SIs, S2Is, rx_disp): Use new macros.
 934         * rx-decode.c: Regenerate.
 935
 936 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 937
 938         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 939
 940 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 941
 942         * arc-dis.c (enforced_isa_mask): Declare.
 943         (cpu_types): Likewise.
 944         (parse_cpu_option): New function.
 945         (parse_disassembler_options): Use it.
 946         (print_insn_arc): Use enforced_isa_mask.
 947         (print_arc_disassembler_options): Document new options.
 948
 949 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 950
 951         * alpha-dis.c: Include disassemble.h, don't include
 952         dis-asm.h.
 953         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 954         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 955         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 956         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 957         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 958         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 959         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 960         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 961         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 962         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 963         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 964         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 965         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 966         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 967         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 968         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 969         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 970         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 971         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 972         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 973         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 974         * z80-dis.c, z8k-dis.c: Likewise.
 975         * disassemble.h: New file.
 976
 977 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 978
 979         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 980         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 981
 982 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 983
 984         * disassemble.c (disassembler): Add arguments a, big and mach.
 985         Use them.
 986
 987 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 988
 989         * i386-dis.c (NOTRACK_Fixup): New.
 990         (NOTRACK): Likewise.
 991         (NOTRACK_PREFIX): Likewise.
 992         (last_active_prefix): Likewise.
 993         (reg_table): Use NOTRACK on indirect call and jmp.
 994         (ckprefix): Set last_active_prefix.
 995         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 996         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 997         * i386-opc.h (NoTrackPrefixOk): New.
 998         (i386_opcode_modifier): Add notrackprefixok.
 999         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1000         Add notrack.
1001         * i386-tbl.h: Regenerated.
1002
1003 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1004
1005         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1006         (X_IMM2): Define.
1007         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1008         bfd_mach_sparc_v9m8.
1009         (print_insn_sparc): Handle new operand types.
1010         * sparc-opc.c (MASK_M8): Define.
1011         (v6): Add MASK_M8.
1012         (v6notlet): Likewise.
1013         (v7): Likewise.
1014         (v8): Likewise.
1015         (v9): Likewise.
1016         (v9a): Likewise.
1017         (v9b): Likewise.
1018         (v9c): Likewise.
1019         (v9d): Likewise.
1020         (v9e): Likewise.
1021         (v9v): Likewise.
1022         (v9m): Likewise.
1023         (v9andleon): Likewise.
1024         (m8): Define.
1025         (HWS_VM8): Define.
1026         (HWS2_VM8): Likewise.
1027         (sparc_opcode_archs): Add entry for "m8".
1028         (sparc_opcodes): Add OSA2017 and M8 instructions
1029         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1030         fpx{ll,ra,rl}64x,
1031         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1032         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1033         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1034         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1035         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1036         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1037         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1038         ASI_CORE_SELECT_COMMIT_NHT.
1039
1040 2017-05-18  Alan Modra  <amodra@gmail.com>
1041
1042         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1043         * aarch64-dis.c: Likewise.
1044         * aarch64-gen.c: Likewise.
1045         * aarch64-opc.c: Likewise.
1046
1047 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1048             Matthew Fortune  <matthew.fortune@imgtec.com>
1049
1050         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1051         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1052         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1053         (print_insn_arg) <OP_REG28>: Add handler.
1054         (validate_insn_args) <OP_REG28>: Handle.
1055         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1056         32-bit encoding and 9-bit immediates.
1057         (print_insn_mips16): Handle MIPS16 instructions that require
1058         32-bit encoding and MFC0/MTC0 operand decoding.
1059         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1060         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1061         (RD_C0, WR_C0, E2, E2MT): New macros.
1062         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1063         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1064         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1065         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1066         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1067         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1068         instructions, "swl", "swr", "sync" and its "sync_acquire",
1069         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1070         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1071         regular/extended entries for original MIPS16 ISA revision
1072         instructions whose extended forms are subdecoded in the MIPS16e2
1073         ISA revision: "li", "sll" and "srl".
1074
1075 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1076
1077         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1078         reference in CP0 move operand decoding.
1079
1080 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1081
1082         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1083         type to hexadecimal.
1084         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1085
1086 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1087
1088         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1089         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1090         "sync_rmb" and "sync_wmb" as aliases.
1091         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1092         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1093
1094 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1095
1096         * arc-dis.c (parse_option): Update quarkse_em option..
1097         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1098         QUARKSE1.
1099         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1100
1101 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1102
1103         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1104
1105 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1106
1107         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1108         register.
1109
1110 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1111
1112         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1113         and branches and not synthetic data instructions.
1114
1115 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1116
1117         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1118
1119 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1120
1121         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1122         * arc-opc.c (insert_r13el): New function.
1123         (R13_EL): Define.
1124         * arc-tbl.h: Add new enter/leave variants.
1125
1126 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1127
1128         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1129
1130 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1131
1132         * mips-dis.c (print_mips_disassembler_options): Add
1133         `no-aliases'.
1134
1135 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1136
1137         * mips16-opc.c (AL): New macro.
1138         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1139         of "ld" and "lw" as aliases.
1140
1141 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1142
1143         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1144         arguments.
1145
1146 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1147             Alan Modra  <amodra@gmail.com>
1148
1149         * ppc-opc.c (ELEV): Define.
1150         (vle_opcodes): Add se_rfgi and e_sc.
1151         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1152         for E200Z4.
1153
1154 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1155
1156         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1157
1158 2017-04-21  Nick Clifton  <nickc@redhat.com>
1159
1160         PR binutils/21380
1161         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1162         LD3R and LD4R.
1163
1164 2017-04-13  Alan Modra  <amodra@gmail.com>
1165
1166         * epiphany-desc.c: Regenerate.
1167         * fr30-desc.c: Regenerate.
1168         * frv-desc.c: Regenerate.
1169         * ip2k-desc.c: Regenerate.
1170         * iq2000-desc.c: Regenerate.
1171         * lm32-desc.c: Regenerate.
1172         * m32c-desc.c: Regenerate.
1173         * m32r-desc.c: Regenerate.
1174         * mep-desc.c: Regenerate.
1175         * mt-desc.c: Regenerate.
1176         * or1k-desc.c: Regenerate.
1177         * xc16x-desc.c: Regenerate.
1178         * xstormy16-desc.c: Regenerate.
1179
1180 2017-04-11  Alan Modra  <amodra@gmail.com>
1181
1182         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1183         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1184         PPC_OPCODE_TMR for e6500.
1185         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1186         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1187         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1188         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1189         (PPCHTM): Define as PPC_OPCODE_POWER8.
1190         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1191
1192 2017-04-10  Alan Modra  <amodra@gmail.com>
1193
1194         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1195         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1196         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1197         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1198
1199 2017-04-09  Pip Cet  <pipcet@gmail.com>
1200
1201         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1202         appropriate floating-point precision directly.
1203
1204 2017-04-07  Alan Modra  <amodra@gmail.com>
1205
1206         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1207         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1208         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1209         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1210         vector instructions with E6500 not PPCVEC2.
1211
1212 2017-04-06  Pip Cet  <pipcet@gmail.com>
1213
1214         * Makefile.am: Add wasm32-dis.c.
1215         * configure.ac: Add wasm32-dis.c to wasm32 target.
1216         * disassemble.c: Add wasm32 disassembler code.
1217         * wasm32-dis.c: New file.
1218         * Makefile.in: Regenerate.
1219         * configure: Regenerate.
1220         * po/POTFILES.in: Regenerate.
1221         * po/opcodes.pot: Regenerate.
1222
1223 2017-04-05  Pedro Alves  <palves@redhat.com>
1224
1225         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1226         * arm-dis.c (parse_arm_disassembler_options): Constify.
1227         * ppc-dis.c (powerpc_init_dialect): Constify local.
1228         * vax-dis.c (parse_disassembler_options): Constify.
1229
1230 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1231
1232         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1233         RISCV_GP_SYMBOL.
1234
1235 2017-03-30  Pip Cet  <pipcet@gmail.com>
1236
1237         * configure.ac: Add (empty) bfd_wasm32_arch target.
1238         * configure: Regenerate
1239         * po/opcodes.pot: Regenerate.
1240
1241 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1242
1243         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1244         OSA2015.
1245         * opcodes/sparc-opc.c (asi_table): New ASIs.
1246
1247 2017-03-29  Alan Modra  <amodra@gmail.com>
1248
1249         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1250         "raw" option.
1251         (lookup_powerpc): Don't special case -1 dialect.  Handle
1252         PPC_OPCODE_RAW.
1253         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1254         lookup_powerpc call, pass it on second.
1255
1256 2017-03-27  Alan Modra  <amodra@gmail.com>
1257
1258         PR 21303
1259         * ppc-dis.c (struct ppc_mopt): Comment.
1260         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1261
1262 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1263
1264         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1265         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1266         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1267         (insert_nps_misc_imm_offset): New function.
1268         (extract_nps_misc imm_offset): New function.
1269         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1270         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1271
1272 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1273
1274         * s390-mkopc.c (main): Remove vx2 check.
1275         * s390-opc.txt: Remove vx2 instruction flags.
1276
1277 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1278
1279         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1280         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1281         (insert_nps_imm_offset): New function.
1282         (extract_nps_imm_offset): New function.
1283         (insert_nps_imm_entry): New function.
1284         (extract_nps_imm_entry): New function.
1285
1286 2017-03-17  Alan Modra  <amodra@gmail.com>
1287
1288         PR 21248
1289         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1290         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1291         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1292
1293 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1294
1295         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1296         <c.andi>: Likewise.
1297         <c.addiw> Likewise.
1298
1299 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1300
1301         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1302
1303 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1304
1305         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1306         <srl> Likewise.
1307         <srai> Likewise.
1308         <sra> Likewise.
1309
1310 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1311
1312         * i386-gen.c (opcode_modifiers): Replace S with Load.
1313         * i386-opc.h (S): Removed.
1314         (Load): New.
1315         (i386_opcode_modifier): Replace s with load.
1316         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1317         and {evex}.  Replace S with Load.
1318         * i386-tbl.h: Regenerated.
1319
1320 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1321
1322         * i386-opc.tbl: Use CpuCET on rdsspq.
1323         * i386-tbl.h: Regenerated.
1324
1325 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1326
1327         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1328         <vsx>: Do not use PPC_OPCODE_VSX3;
1329
1330 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1331
1332         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1333
1334 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1335
1336         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1337         (MOD_0F1E_PREFIX_1): Likewise.
1338         (MOD_0F38F5_PREFIX_2): Likewise.
1339         (MOD_0F38F6_PREFIX_0): Likewise.
1340         (RM_0F1E_MOD_3_REG_7): Likewise.
1341         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1342         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1343         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1344         (PREFIX_0F1E): Likewise.
1345         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1346         (PREFIX_0F38F5): Likewise.
1347         (dis386_twobyte): Use PREFIX_0F1E.
1348         (reg_table): Add REG_0F1E_MOD_3.
1349         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1350         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1351         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1352         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1353         (three_byte_table): Use PREFIX_0F38F5.
1354         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1355         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1356         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1357         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1358         PREFIX_MOD_3_0F01_REG_5_RM_2.
1359         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1360         (cpu_flags): Add CpuCET.
1361         * i386-opc.h (CpuCET): New enum.
1362         (CpuUnused): Commented out.
1363         (i386_cpu_flags): Add cpucet.
1364         * i386-opc.tbl: Add Intel CET instructions.
1365         * i386-init.h: Regenerated.
1366         * i386-tbl.h: Likewise.
1367
1368 2017-03-06  Alan Modra  <amodra@gmail.com>
1369
1370         PR 21124
1371         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1372         (extract_raq, extract_ras, extract_rbx): New functions.
1373         (powerpc_operands): Use opposite corresponding insert function.
1374         (Q_MASK): Define.
1375         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1376         register restriction.
1377
1378 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1379
1380         * disassemble.c Include "safe-ctype.h".
1381         (disassemble_init_for_target): Handle s390 init.
1382         (remove_whitespace_and_extra_commas): New function.
1383         (disassembler_options_cmp): Likewise.
1384         * arm-dis.c: Include "libiberty.h".
1385         (NUM_ELEM): Delete.
1386         (regnames): Use long disassembler style names.
1387         Add force-thumb and no-force-thumb options.
1388         (NUM_ARM_REGNAMES): Rename from this...
1389         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1390         (get_arm_regname_num_options): Delete.
1391         (set_arm_regname_option): Likewise.
1392         (get_arm_regnames): Likewise.
1393         (parse_disassembler_options): Likewise.
1394         (parse_arm_disassembler_option): Rename from this...
1395         (parse_arm_disassembler_options): ...to this.  Make static.
1396         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1397         (print_insn): Use parse_arm_disassembler_options.
1398         (disassembler_options_arm): New function.
1399         (print_arm_disassembler_options): Handle updated regnames.
1400         * ppc-dis.c: Include "libiberty.h".
1401         (ppc_opts): Add "32" and "64" entries.
1402         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1403         (powerpc_init_dialect): Add break to switch statement.
1404         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1405         (disassembler_options_powerpc): New function.
1406         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1407         Remove printing of "32" and "64".
1408         * s390-dis.c: Include "libiberty.h".
1409         (init_flag): Remove unneeded variable.
1410         (struct s390_options_t): New structure type.
1411         (options): New structure.
1412         (init_disasm): Rename from this...
1413         (disassemble_init_s390): ...to this.  Add initializations for
1414         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1415         (print_insn_s390): Delete call to init_disasm.
1416         (disassembler_options_s390): New function.
1417         (print_s390_disassembler_options): Print using information from
1418         struct 'options'.
1419         * po/opcodes.pot: Regenerate.
1420
1421 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1422
1423         * i386-dis.c (PCMPESTR_Fixup): New.
1424         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1425         (prefix_table): Use PCMPESTR_Fixup.
1426         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1427         PCMPESTR_Fixup.
1428         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1429         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1430         Split 64-bit and non-64-bit variants.
1431         * opcodes/i386-tbl.h: Re-generate.
1432
1433 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1434
1435         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1436         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1437         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1438         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1439         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1440         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1441         (OP_SVE_V_HSD): New macros.
1442         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1443         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1444         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1445         (aarch64_opcode_table): Add new SVE instructions.
1446         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1447         for rotation operands.  Add new SVE operands.
1448         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1449         (ins_sve_quad_index): Likewise.
1450         (ins_imm_rotate): Split into...
1451         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1452         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1453         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1454         functions.
1455         (aarch64_ins_sve_addr_ri_s4): New function.
1456         (aarch64_ins_sve_quad_index): Likewise.
1457         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1458         * aarch64-asm-2.c: Regenerate.
1459         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1460         (ext_sve_quad_index): Likewise.
1461         (ext_imm_rotate): Split into...
1462         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1463         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1464         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1465         functions.
1466         (aarch64_ext_sve_addr_ri_s4): New function.
1467         (aarch64_ext_sve_quad_index): Likewise.
1468         (aarch64_ext_sve_index): Allow quad indices.
1469         (do_misc_decoding): Likewise.
1470         * aarch64-dis-2.c: Regenerate.
1471         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1472         aarch64_field_kinds.
1473         (OPD_F_OD_MASK): Widen by one bit.
1474         (OPD_F_NO_ZR): Bump accordingly.
1475         (get_operand_field_width): New function.
1476         * aarch64-opc.c (fields): Add new SVE fields.
1477         (operand_general_constraint_met_p): Handle new SVE operands.
1478         (aarch64_print_operand): Likewise.
1479         * aarch64-opc-2.c: Regenerate.
1480
1481 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1482
1483         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1484         (aarch64_feature_compnum): ...this.
1485         (SIMD_V8_3): Replace with...
1486         (COMPNUM): ...this.
1487         (CNUM_INSN): New macro.
1488         (aarch64_opcode_table): Use it for the complex number instructions.
1489
1490 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1491
1492         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1493
1494 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1495
1496         Add support for associating SPARC ASIs with an architecture level.
1497         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1498         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1499         decoding of SPARC ASIs.
1500
1501 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1502
1503         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1504         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1505
1506 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1507
1508         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1509         1 (instead of to itself). Correct typo.
1510
1511 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1512
1513         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1514         pseudoinstructions.
1515
1516 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1517
1518         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1519         (aarch64_sys_reg_supported_p): Handle them.
1520
1521 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1522
1523         * arc-opc.c (UIMM6_20R): Define.
1524         (SIMM12_20): Use above.
1525         (SIMM12_20R): Define.
1526         (SIMM3_5_S): Use above.
1527         (UIMM7_A32_11R_S): Define.
1528         (UIMM7_9_S): Use above.
1529         (UIMM3_13R_S): Define.
1530         (SIMM11_A32_7_S): Use above.
1531         (SIMM9_8R): Define.
1532         (UIMM10_A32_8_S): Use above.
1533         (UIMM8_8R_S): Define.
1534         (W6): Use above.
1535         (arc_relax_opcodes): Use all above defines.
1536
1537 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1538
1539         * arc-regs.h: Distinguish some of the registers different on
1540         ARC700 and HS38 cpus.
1541
1542 2017-02-14  Alan Modra  <amodra@gmail.com>
1543
1544         PR 21118
1545         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1546         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1547
1548 2017-02-11  Stafford Horne  <shorne@gmail.com>
1549             Alan Modra  <amodra@gmail.com>
1550
1551         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1552         Use insn_bytes_value and insn_int_value directly instead.  Don't
1553         free allocated memory until function exit.
1554
1555 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1556
1557         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1558
1559 2017-02-03  Nick Clifton  <nickc@redhat.com>
1560
1561         PR 21096
1562         * aarch64-opc.c (print_register_list): Ensure that the register
1563         list index will fir into the tb buffer.
1564         (print_register_offset_address): Likewise.
1565         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1566
1567 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1568
1569         PR 21056
1570         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1571         instructions when the previous fetch packet ends with a 32-bit
1572         instruction.
1573
1574 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1575
1576         * pru-opc.c: Remove vague reference to a future GDB port.
1577
1578 2017-01-20  Nick Clifton  <nickc@redhat.com>
1579
1580         * po/ga.po: Updated Irish translation.
1581
1582 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1583
1584         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1585
1586 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1587
1588         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1589         if FETCH_DATA returns 0.
1590         (m68k_scan_mask): Likewise.
1591         (print_insn_m68k): Update code to handle -1 return value.
1592
1593 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1594
1595         * m68k-dis.c (enum print_insn_arg_error): New.
1596         (NEXTBYTE): Replace -3 with
1597         PRINT_INSN_ARG_MEMORY_ERROR.
1598         (NEXTULONG): Likewise.
1599         (NEXTSINGLE): Likewise.
1600         (NEXTDOUBLE): Likewise.
1601         (NEXTDOUBLE): Likewise.
1602         (NEXTPACKED): Likewise.
1603         (FETCH_ARG): Likewise.
1604         (FETCH_DATA): Update comments.
1605         (print_insn_arg): Update comments. Replace magic numbers with
1606         enum.
1607         (match_insn_m68k): Likewise.
1608
1609 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1610
1611         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1612         * i386-dis-evex.h (evex_table): Updated.
1613         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1614         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1615         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1616         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1617         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1618         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1619         * i386-init.h: Regenerate.
1620         * i386-tbl.h: Ditto.
1621
1622 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1623
1624         * msp430-dis.c (msp430_singleoperand): Return -1 if
1625         msp430dis_opcode_signed returns false.
1626         (msp430_doubleoperand): Likewise.
1627         (msp430_branchinstr): Return -1 if
1628         msp430dis_opcode_unsigned returns false.
1629         (msp430x_calla_instr): Likewise.
1630         (print_insn_msp430): Likewise.
1631
1632 2017-01-05  Nick Clifton  <nickc@redhat.com>
1633
1634         PR 20946
1635         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1636         could not be matched.
1637         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1638         NULL.
1639
1640 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1641
1642         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1643         (aarch64_opcode_table): Use RCPC_INSN.
1644
1645 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1646
1647         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1648         extension.
1649         * riscv-opcodes/all-opcodes: Likewise.
1650
1651 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1652
1653         * riscv-dis.c (print_insn_args): Add fall through comment.
1654
1655 2017-01-03  Nick Clifton  <nickc@redhat.com>
1656
1657         * po/sr.po: New Serbian translation.
1658         * configure.ac (ALL_LINGUAS): Add sr.
1659         * configure: Regenerate.
1660
1661 2017-01-02  Alan Modra  <amodra@gmail.com>
1662
1663         * epiphany-desc.h: Regenerate.
1664         * epiphany-opc.h: Regenerate.
1665         * fr30-desc.h: Regenerate.
1666         * fr30-opc.h: Regenerate.
1667         * frv-desc.h: Regenerate.
1668         * frv-opc.h: Regenerate.
1669         * ip2k-desc.h: Regenerate.
1670         * ip2k-opc.h: Regenerate.
1671         * iq2000-desc.h: Regenerate.
1672         * iq2000-opc.h: Regenerate.
1673         * lm32-desc.h: Regenerate.
1674         * lm32-opc.h: Regenerate.
1675         * m32c-desc.h: Regenerate.
1676         * m32c-opc.h: Regenerate.
1677         * m32r-desc.h: Regenerate.
1678         * m32r-opc.h: Regenerate.
1679         * mep-desc.h: Regenerate.
1680         * mep-opc.h: Regenerate.
1681         * mt-desc.h: Regenerate.
1682         * mt-opc.h: Regenerate.
1683         * or1k-desc.h: Regenerate.
1684         * or1k-opc.h: Regenerate.
1685         * xc16x-desc.h: Regenerate.
1686         * xc16x-opc.h: Regenerate.
1687         * xstormy16-desc.h: Regenerate.
1688         * xstormy16-opc.h: Regenerate.
1689
1690 2017-01-02  Alan Modra  <amodra@gmail.com>
1691
1692         Update year range in copyright notice of all files.
1693
1694 For older changes see ChangeLog-2016
1695 \f
1696 Copyright (C) 2017 Free Software Foundation, Inc.
1697
1698 Copying and distribution of this file, with or without modification,
1699 are permitted in any medium without royalty provided the copyright
1700 notice and this notice are preserved.
1701
1702 Local Variables:
1703 mode: change-log
1704 left-margin: 8
1705 fill-column: 74
1706 version-control: never
1707 End: