1 2020-11-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
3 * aarch64-tbl.h (FLAGM): Handle for FLAGM feature.
4 (struct aarch64_opcode): Move FLAGM instructions from V8_4_INSN to
6 (AARCH64_FEATURE_FLAGMANIP): Update comment for FEAT_FlagM2.
8 2020-11-14 Borislav Petkov <bp@suse.de>
10 * i386-dis.c (ckprefix): Do not assign active_seg_prefix in
11 64-bit addressing mode.
12 (NOTRACK_Fixup): Test prefixes for PREFIX_DS, instead of
15 2020-11-11 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
17 * aarch64-tbl.h: Enable -march=armv8.6-a+ls64.
19 2020-11-09 Spencer E. Olson <olsonse@umich.edu>
21 * pru-opc.c: Add opcode description for LMBD (left-most bit
24 2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
26 * aarch64-opc.c: Add ACCDATA_EL1 system register
28 2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
30 * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64
32 * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with
34 * aarch64-asm-2.c: Regenerated.
35 * aarch64-dis-2.c: Regenerated.
36 * aarch64-opc-2.c: Regenerated.
38 2020-11-06 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
40 * aarch64-tbl.h (PAC): Handle for PAC feature.
41 (PAC_INSN): New PAC instruction.
42 (struct aarch64_opcode): Move PAC instructions from V8_3_INSN to
45 2020-11-04 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
47 * aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1,
48 ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1.
50 2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
52 * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores.
53 (LS64): Handler with +ls64 feature flags.
54 (_LS64_INSN): New instruction group macro.
55 (struct aarch64_opcode): Add LS64 instructions.
56 * aarch64-asm-2.c: Regenerated.
57 * aarch64-dis-2.c: Regenerated.
58 * aarch64-opc-2.c: Regenerated.
60 2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
62 * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
63 * aarch64-asm-2.c: Regenerated.
64 * aarch64-dis-2.c: Regenerated.
65 * aarch64-opc-2.c: Regenerated.
67 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
69 * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
70 * aarch64-tbl.h (CSRE): New CSRE feature handler.
71 (_CSRE_INSN): New CSRE instruction type.
72 (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
73 * aarch64-asm-2.c: Regenerated.
74 * aarch64-dis-2.c: Regenerated.
75 * aarch64-opc-2.c: Regenerated.
77 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
79 * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
80 and operand description.
81 * aarch64-asm-2.c: Regenerated.
82 * aarch64-dis-2.c: Regenerated.
83 * aarch64-opc-2.c: Regenerated.
85 2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
87 * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
89 2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
91 * csky-dis.c (csky_output_operand): Add handler for
92 OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
93 * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
94 (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
95 some instructions for VDSPV1.
97 2020-10-26 Lili Cui <lili.cui@intel.com>
99 * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
101 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
103 * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
104 * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
106 * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
107 * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
109 * aarch64-opc.c (aarch64_print_operand): New options table
110 aarch64_barrier_dsb_nxs_options.
111 * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
112 * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
113 Armv8.7-a instruction.
114 * aarch64-asm-2.c: Regenerated.
115 * aarch64-dis-2.c: Regenerated.
116 * aarch64-opc-2.c: Regenerated.
118 2020-10-22 H.J. Lu <hongjiu.lu@intel.com>
120 * po/es.po: Remove the duplicated entry.
122 2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com>
124 * po/es.po: Fix printf format.
126 2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
128 * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
129 * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
130 CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
131 Add CPU_ZNVER3_FLAGS.
132 (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
133 * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
134 * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
135 rmpupdate, rmpadjust.
136 * i386-init.h: Re-generated.
137 * i386-tbl.h: Re-generated.
139 2020-10-16 Lili Cui <lili.cui@intel.com>
141 * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
142 and move it from cpu_flags to opcode_modifiers.
143 Use VexW0 and VexVVVV in the AVX-VNNI instructions.
144 * i386-gen.c: Likewise.
145 * i386-opc.h: Likewise.
146 * i386-opc.h: Likewise.
147 * i386-init.h: Regenerated.
148 * i386-tbl.h: Likewise.
150 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
152 * aarch64-tbl.h (ARMV8_7): New macro.
154 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
155 Lili Cui <lili.cui@intel.com>
157 * i386-dis.c (PREFIX_VEX_0F3850): New.
158 (PREFIX_VEX_0F3851): Likewise.
159 (PREFIX_VEX_0F3852): Likewise.
160 (PREFIX_VEX_0F3853): Likewise.
161 (VEX_W_0F3850_P_2): Likewise.
162 (VEX_W_0F3851_P_2): Likewise.
163 (VEX_W_0F3852_P_2): Likewise.
164 (VEX_W_0F3853_P_2): Likewise.
165 (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
166 PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
167 (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
168 VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
169 (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
170 * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
171 CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
172 CPU_ANY_AVX_VNNI_FLAGS.
173 (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
174 * i386-opc.h (CpuAVX_VNNI): New.
175 (CpuVEX_PREFIX): Likewise.
176 (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
177 * i386-opc.tbl: Add Intel AVX VNNI instructions.
178 * i386-init.h: Regenerated.
179 * i386-tbl.h: Likewise.
181 2020-10-14 Lili Cui <lili.cui@intel.com>
182 H.J. Lu <hongjiu.lu@intel.com>
184 * i386-dis.c (PREFIX_0F3A0F): New.
185 (MOD_0F3A0F_PREFIX_1): Likewise.
186 (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
187 (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
188 (prefix_table): Add PREFIX_0F3A0F.
189 (mod_table): Add MOD_0F3A0F_PREFIX_1.
190 (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
191 (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
192 * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
193 CPU_ANY_HRESET_FLAGS.
194 (cpu_flags): Add CpuHRESET.
195 (output_i386_opcode): Allow 4 byte base_opcode.
196 * i386-opc.h (enum): Add CpuHRESET.
197 (i386_cpu_flags): Add cpuhreset.
198 * i386-opc.tbl: Add Intel HRESET instruction.
199 * i386-init.h: Regenerate.
200 * i386-tbl.h: Likewise.
202 2020-10-14 Lili Cui <lili.cui@intel.com>
204 * i386-dis.c (enum): Add
205 PREFIX_MOD_3_0F01_REG_5_RM_4,
206 PREFIX_MOD_3_0F01_REG_5_RM_5,
207 PREFIX_MOD_3_0F01_REG_5_RM_6,
208 PREFIX_MOD_3_0F01_REG_5_RM_7,
209 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
210 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
211 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
212 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
213 X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
214 (prefix_table): New instructions (see prefixes above).
216 * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
218 (cpu_flags): Add CpuUINTR.
219 * i386-opc.h (enum): Add CpuUINTR.
220 (i386_cpu_flags): Add cpuuintr.
221 * i386-opc.tbl: Add UINTR insns.
222 * i386-init.h: Regenerate.
223 * i386-tbl.h: Likewise.
225 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
227 * i386-gen.c (process_i386_opcode_modifier): Return 1 for
228 non-VEX/EVEX/prefix encoding.
229 (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
231 * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
232 base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
233 * i386-tbl.h: Regenerated.
235 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
237 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
239 * i386-opc.h (VexOpcode): Renamed to ...
240 (OpcodePrefix): This.
242 (PREFIX_0X66): Likewise.
243 (PREFIX_0XF2): Likewise.
244 (PREFIX_0XF3): Likewise.
245 * i386-opc.tbl (Prefix_0X66): New.
246 (Prefix_0XF2): Likewise.
247 (Prefix_0XF3): Likewise.
248 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
249 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
250 * i386-tbl.h: Regenerated.
252 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
254 * aarch64-opc.c: Add BRBE system registers.
256 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
258 * aarch64-opc.c: New CSRE system registers defined.
260 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
262 * cgen-asm.c: Fix spelling mistakes.
263 * cgen-dis.c: Fix spelling mistakes.
264 * tic30-dis.c: Fix spelling mistakes.
266 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
269 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
271 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
274 * i386-dis.c (print_insn): Clear modrm if not needed.
275 (putop): Check need_modrm for modrm.mod != 3. Don't check
276 need_modrm for modrm.mod == 3.
278 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
280 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
281 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
282 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
283 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
284 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
285 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
286 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
287 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
288 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
289 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
290 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
291 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
292 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
293 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
295 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
297 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
299 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
301 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
302 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
304 2020-09-26 Alan Modra <amodra@gmail.com>
306 * csky-opc.h: Formatting.
307 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
308 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
310 (get_register_number): Likewise.
311 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
313 2020-09-24 Lili Cui <lili.cui@intel.com>
316 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
318 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
320 * csky-dis.c (csky_output_operand): Enclose body of if in curly
323 2020-09-24 Lili Cui <lili.cui@intel.com>
325 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
326 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
327 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
328 X86_64_0F01_REG_1_RM_7_P_2.
329 (prefix_table): Likewise.
330 (x86_64_table): Likewise.
331 (rm_table): Likewise.
332 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
333 and CPU_ANY_TDX_FLAGS.
334 (cpu_flags): Add CpuTDX.
335 * i386-opc.h (enum): Add CpuTDX.
336 (i386_cpu_flags): Add cputdx.
337 * i386-opc.tbl: Add TDX insns.
338 * i386-init.h: Regenerate.
339 * i386-tbl.h: Likewise.
341 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
343 * csky-dis.c (using_abi): New.
344 (parse_csky_dis_options): New function.
345 (get_gr_name): New function.
346 (get_cr_name): New function.
347 (csky_output_operand): Use get_gr_name and get_cr_name to
348 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
349 (print_insn_csky): Parse disassembler options.
350 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
351 (GENARAL_REG_BANK): Define.
352 (REG_SUPPORT_ALL): Define.
353 (REG_SUPPORT_ALL): New.
355 (REG_SUPPORT_A): Define.
356 (REG_SUPPORT_B): Define.
357 (REG_SUPPORT_C): Define.
358 (REG_SUPPORT_D): Define.
359 (REG_SUPPORT_E): Define.
360 (csky_abiv1_general_regs): New.
361 (csky_abiv1_control_regs): New.
362 (csky_abiv2_general_regs): New.
363 (csky_abiv2_control_regs): New.
364 (get_register_name): New function.
365 (get_register_number): New function.
366 (csky_get_general_reg_name): New function.
367 (csky_get_general_regno): New function.
368 (csky_get_control_reg_name): New function.
369 (csky_get_control_regno): New function.
370 (csky_v2_opcodes): Prefer two oprerans format for bclri and
371 bseti, strengthen the operands legality check of addc, zext
374 2020-09-23 Lili Cui <lili.cui@intel.com>
376 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
377 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
378 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
379 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
380 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
381 (reg_table): New instructions (see prefixes above).
382 (prefix_table): Likewise.
383 (three_byte_table): Likewise.
384 (mod_table): Likewise
385 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
386 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
387 (cpu_flags): Likewise.
388 (operand_type_init): Likewise.
389 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
390 (i386_cpu_flags): Add cpukl and cpuwide_kl.
391 * i386-opc.tbl: Add KL and WIDE_KL insns.
392 * i386-init.h: Regenerate.
393 * i386-tbl.h: Likewise.
395 2020-09-21 Alan Modra <amodra@gmail.com>
397 * rx-dis.c (flag_names): Add missing comma.
398 (register_names, flag_names, double_register_names),
399 (double_register_high_names, double_register_low_names),
400 (double_control_register_names, double_condition_names): Remove
403 2020-09-18 David Faust <david.faust@oracle.com>
405 * bpf-desc.c: Regenerate.
406 * bpf-desc.h: Likewise.
407 * bpf-opc.c: Likewise.
408 * bpf-opc.h: Likewise.
410 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
412 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
415 2020-09-16 Alan Modra <amodra@gmail.com>
417 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
419 2020-09-10 Nick Clifton <nickc@redhat.com>
421 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
422 for hidden, local, no-type symbols.
423 (disassemble_init_powerpc): Point the symbol_is_valid field in the
424 info structure at the new function.
426 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
428 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
429 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
432 2020-09-10 Nick Clifton <nickc@redhat.com>
434 * csky-dis.c (csky_output_operand): Coerce the immediate values to
435 long before printing.
437 2020-09-10 Alan Modra <amodra@gmail.com>
439 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
441 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
443 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
446 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
448 * csky-dis.c (csky_output_operand): Add handlers for
449 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
450 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
451 to support FPUV3 instructions.
452 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
453 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
454 OPRND_TYPE_DFLOAT_FMOVI.
455 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
456 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
457 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
458 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
459 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
460 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
461 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
462 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
463 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
464 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
465 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
466 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
467 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
468 (csky_v2_opcodes): Add FPUV3 instructions.
470 2020-09-08 Alex Coplan <alex.coplan@arm.com>
472 * aarch64-dis.c (print_operands): Pass CPU features to
473 aarch64_print_operand().
474 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
475 preferred disassembly of system registers.
476 (SR_RNG): Refactor to use new SR_FEAT2 macro.
482 (SR_EXPAND_ELx): New.
483 (SR_EXPAND_EL12): New.
484 (aarch64_sys_regs): Specify which registers are only on
485 A-profile, add R-profile system registers.
489 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
492 2020-09-08 Alex Coplan <alex.coplan@arm.com>
494 * aarch64-tbl.h (aarch64_feature_v8_r): New.
497 (aarch64_opcode_table): Add dfb.
498 * aarch64-opc-2.c: Regenerate.
499 * aarch64-asm-2.c: Regenerate.
500 * aarch64-dis-2.c: Regenerate.
502 2020-09-08 Alex Coplan <alex.coplan@arm.com>
504 * aarch64-dis.c (arch_variant): New.
505 (determine_disassembling_preference): Disassemble according to
507 (select_aarch64_variant): New.
508 (print_insn_aarch64): Set feature set.
510 2020-09-02 Alan Modra <amodra@gmail.com>
512 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
513 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
514 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
515 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
516 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
517 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
518 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
519 for value parameter and update code to suit.
520 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
521 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
523 2020-09-02 Alan Modra <amodra@gmail.com>
525 * i386-dis.c (OP_E_memory): Don't cast to signed type when
527 (get32, get32s): Use unsigned types in shift expressions.
529 2020-09-02 Alan Modra <amodra@gmail.com>
531 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
533 2020-09-02 Alan Modra <amodra@gmail.com>
535 * crx-dis.c: Whitespace.
536 (print_arg): Use unsigned type for longdisp and mask variables,
537 and for left shift constant.
539 2020-09-02 Alan Modra <amodra@gmail.com>
541 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
542 * bpf-ibld.c: Regenerate.
543 * epiphany-ibld.c: Regenerate.
544 * fr30-ibld.c: Regenerate.
545 * frv-ibld.c: Regenerate.
546 * ip2k-ibld.c: Regenerate.
547 * iq2000-ibld.c: Regenerate.
548 * lm32-ibld.c: Regenerate.
549 * m32c-ibld.c: Regenerate.
550 * m32r-ibld.c: Regenerate.
551 * mep-ibld.c: Regenerate.
552 * mt-ibld.c: Regenerate.
553 * or1k-ibld.c: Regenerate.
554 * xc16x-ibld.c: Regenerate.
555 * xstormy16-ibld.c: Regenerate.
557 2020-09-02 Alan Modra <amodra@gmail.com>
559 * bfin-dis.c (MASKBITS): Use SIGNBIT.
561 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
563 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
564 to CSKYV2_ISA_3E3R3 instruction set.
566 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
568 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
570 2020-09-01 Alan Modra <amodra@gmail.com>
572 * mep-ibld.c: Regenerate.
574 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
576 * csky-dis.c (csky_output_operand): Assign dis_info.value for
579 2020-08-30 Alan Modra <amodra@gmail.com>
581 * cr16-dis.c: Formatting.
582 (parameter): Delete struct typedef. Use dwordU instead
584 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
586 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
588 2020-08-29 Alan Modra <amodra@gmail.com>
591 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
592 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
594 2020-08-28 Alan Modra <amodra@gmail.com>
598 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
599 (extract_normal): Likewise.
600 (insert_normal): Likewise, and move past zero length test.
601 (put_insn_int_value): Handle mask for zero length, use 1UL.
602 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
603 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
604 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
605 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
607 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
609 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
610 (csky_dis_info): Add member isa.
611 (csky_find_inst_info): Skip instructions that do not belong to
613 (csky_get_disassembler): Get infomation from attribute section.
614 (print_insn_csky): Set defualt ISA flag.
615 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
616 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
617 isa_flag32'type to unsigned 64 bits.
619 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
621 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
623 2020-08-26 David Faust <david.faust@oracle.com>
625 * bpf-desc.c: Regenerate.
626 * bpf-desc.h: Likewise.
627 * bpf-opc.c: Likewise.
628 * bpf-opc.h: Likewise.
629 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
630 ISA when appropriate.
632 2020-08-25 Alan Modra <amodra@gmail.com>
635 * vax-dis.c (parse_disassembler_options): Always add at least one
636 to entry_addr_total_slots.
638 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
640 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
641 in other CPUs to speed up disassembling.
642 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
643 Change plsli.u16 to plsli.16, change sync's operand format.
645 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
647 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
649 2020-08-21 Nick Clifton <nickc@redhat.com>
651 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
654 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
656 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
658 2020-08-19 Alan Modra <amodra@gmail.com>
660 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
663 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
665 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
666 <xvcvbf16spn>: ...to this.
668 2020-08-12 Alex Coplan <alex.coplan@arm.com>
670 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
672 2020-08-12 Nick Clifton <nickc@redhat.com>
674 * po/sr.po: Updated Serbian translation.
676 2020-08-11 Alan Modra <amodra@gmail.com>
678 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
680 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
682 * aarch64-opc.c (aarch64_print_operand):
683 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
684 (aarch64_sys_reg_supported_p): Function removed.
685 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
686 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
689 2020-08-10 Alan Modra <amodra@gmail.com>
691 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
694 2020-08-10 Alan Modra <amodra@gmail.com>
696 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
697 Enable icbt for power5, miso for power8.
699 2020-08-10 Alan Modra <amodra@gmail.com>
701 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
702 mtvsrd, and similarly for mfvsrd.
704 2020-08-04 Christian Groessler <chris@groessler.org>
705 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
707 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
708 opcodes (special "out" to absolute address).
709 * z8k-opc.h: Regenerate.
711 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
714 * i386-opc.h (Prefix_Disp8): New.
715 (Prefix_Disp16): Likewise.
716 (Prefix_Disp32): Likewise.
717 (Prefix_Load): Likewise.
718 (Prefix_Store): Likewise.
719 (Prefix_VEX): Likewise.
720 (Prefix_VEX3): Likewise.
721 (Prefix_EVEX): Likewise.
722 (Prefix_REX): Likewise.
723 (Prefix_NoOptimize): Likewise.
724 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
725 * i386-tbl.h: Regenerated.
727 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
729 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
730 default case with abort() instead of printing an error message and
731 continuing, to avoid a maybe-uninitialized warning.
733 2020-07-24 Nick Clifton <nickc@redhat.com>
735 * po/de.po: Updated German translation.
737 2020-07-21 Jan Beulich <jbeulich@suse.com>
739 * i386-dis.c (OP_E_memory): Revert previous change.
741 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
744 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
745 without base nor index registers.
747 2020-07-15 Jan Beulich <jbeulich@suse.com>
749 * i386-dis.c (putop): Move 'V' and 'W' handling.
751 2020-07-15 Jan Beulich <jbeulich@suse.com>
753 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
754 construct for push/pop of register.
755 (putop): Honor cond when handling 'P'. Drop handling of plain
758 2020-07-15 Jan Beulich <jbeulich@suse.com>
760 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
761 description. Drop '&' description. Use P for push of immediate,
762 pushf/popf, enter, and leave. Use %LP for lret/retf.
763 (dis386_twobyte): Use P for push/pop of fs/gs.
764 (reg_table): Use P for push/pop. Use @ for near call/jmp.
765 (x86_64_table): Use P for far call/jmp.
766 (putop): Drop handling of 'U' and '&'. Move and adjust handling
767 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
769 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
770 and dqw_mode (unconditional).
772 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
775 * i386-dis.c (OP_E_memory): Without base nor index registers,
776 32-bit displacement to 64 bits.
778 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
780 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
781 faulty double register pair is detected.
783 2020-07-14 Jan Beulich <jbeulich@suse.com>
785 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
787 2020-07-14 Jan Beulich <jbeulich@suse.com>
789 * i386-dis.c (OP_R, Rm): Delete.
790 (MOD_0F24, MOD_0F26): Rename to ...
791 (X86_64_0F24, X86_64_0F26): ... respectively.
792 (dis386): Update 'L' and 'Z' comments.
793 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
795 (mod_table): Move opcode 0F24 and 0F26 entries ...
796 (x86_64_table): ... here.
797 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
800 2020-07-14 Jan Beulich <jbeulich@suse.com>
802 * i386-dis.c (Rd, Rdq, MaskR): Delete.
803 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
804 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
805 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
806 MOD_EVEX_0F387C): New enumerators.
807 (reg_table): Use Edq for rdssp.
808 (prefix_table): Use Edq for incssp.
809 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
810 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
811 ktest*, and kshift*. Use Edq / MaskE for kmov*.
812 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
813 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
814 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
815 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
816 0F3828_P_1 and 0F3838_P_1.
817 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
818 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
820 2020-07-14 Jan Beulich <jbeulich@suse.com>
822 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
823 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
824 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
825 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
826 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
827 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
828 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
829 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
830 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
831 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
832 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
833 (reg_table, prefix_table, three_byte_table, vex_table,
834 vex_len_table, mod_table, rm_table): Replace / remove respective
836 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
837 of PREFIX_DATA in used_prefixes.
839 2020-07-14 Jan Beulich <jbeulich@suse.com>
841 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
842 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
843 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
844 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
845 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
846 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
847 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
848 VEX_W_0F3A33_L_0): Delete.
849 (dis386): Adjust "BW" description.
850 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
851 0F3A31, 0F3A32, and 0F3A33.
852 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
854 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
857 2020-07-14 Jan Beulich <jbeulich@suse.com>
859 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
860 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
861 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
862 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
863 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
864 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
865 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
866 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
867 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
868 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
869 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
870 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
871 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
872 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
873 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
874 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
875 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
876 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
877 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
878 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
879 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
880 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
881 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
882 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
883 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
884 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
885 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
886 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
887 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
888 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
889 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
890 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
891 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
892 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
893 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
894 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
895 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
896 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
897 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
898 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
899 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
900 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
901 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
902 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
903 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
904 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
905 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
906 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
907 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
908 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
909 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
910 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
911 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
912 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
913 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
914 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
915 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
916 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
917 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
918 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
919 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
920 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
921 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
922 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
923 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
924 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
925 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
926 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
927 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
928 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
929 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
930 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
931 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
932 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
933 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
934 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
935 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
936 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
937 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
938 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
939 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
940 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
941 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
942 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
943 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
944 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
945 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
946 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
947 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
948 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
949 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
950 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
951 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
952 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
953 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
954 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
955 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
956 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
957 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
958 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
959 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
960 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
961 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
962 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
963 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
964 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
965 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
966 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
967 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
968 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
969 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
970 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
971 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
972 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
973 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
974 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
975 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
976 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
977 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
978 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
979 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
980 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
981 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
982 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
983 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
984 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
985 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
986 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
987 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
988 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
989 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
990 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
991 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
992 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
993 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
994 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
995 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
996 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
997 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
998 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
999 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
1000 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
1001 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
1002 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
1003 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
1004 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
1005 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
1006 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
1007 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
1008 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
1009 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
1010 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
1011 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
1012 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
1013 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
1014 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
1015 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
1016 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
1017 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
1018 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
1019 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
1020 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
1021 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
1022 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
1023 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
1024 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
1025 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
1026 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
1027 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1028 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1029 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
1030 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
1031 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
1032 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
1033 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
1034 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
1035 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
1036 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
1037 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
1038 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
1039 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
1040 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
1041 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
1042 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
1043 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
1044 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
1045 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
1046 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
1047 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
1048 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
1049 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1050 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
1051 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1052 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1053 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
1054 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
1055 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
1056 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
1057 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
1058 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1059 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
1060 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1061 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1062 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1063 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
1064 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
1065 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
1066 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
1067 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
1068 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
1069 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
1070 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
1071 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
1072 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
1073 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
1074 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
1075 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
1076 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
1077 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
1078 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
1079 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
1080 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
1081 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
1082 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
1083 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
1084 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
1085 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
1086 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
1087 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
1088 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
1089 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
1090 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
1091 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
1092 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
1093 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
1094 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
1095 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
1096 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
1097 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
1098 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
1099 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
1100 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
1101 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
1102 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
1103 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
1104 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
1105 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
1106 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
1107 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
1108 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
1109 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
1110 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1111 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
1112 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1113 EVEX_W_0F3A72_P_2): Rename to ...
1114 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1115 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1116 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1117 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1118 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1119 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1120 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1121 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1122 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1123 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1124 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1125 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1126 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1127 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1128 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1129 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1130 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1131 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1132 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1133 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1134 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1135 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1136 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1137 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1138 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1139 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1140 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1141 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1142 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1143 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1144 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1145 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1146 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1147 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1148 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1149 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1150 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1151 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1152 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1153 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1154 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1155 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1156 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1157 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1158 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1159 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1160 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1161 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1162 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1163 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1164 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1165 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1166 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1167 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1168 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1169 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1170 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1171 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1172 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1173 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1174 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1175 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1176 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1177 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1178 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1179 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1180 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1181 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1182 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1183 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1184 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1185 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1187 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1188 vex_w_table, mod_table): Replace / remove respective entries.
1189 (print_insn): Move up dp->prefix_requirement handling. Handle
1191 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1192 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1193 Replace / remove respective entries.
1195 2020-07-14 Jan Beulich <jbeulich@suse.com>
1197 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1198 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1199 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1200 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1201 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1203 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1204 0F2C, 0F2D, 0F2E, and 0F2F.
1205 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1208 2020-07-14 Jan Beulich <jbeulich@suse.com>
1210 * i386-dis.c (OP_VexR, VexScalarR): New.
1211 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1212 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1213 need_vex_reg): Delete.
1214 (prefix_table): Replace VexScalar by VexScalarR and
1215 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1216 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1217 (vex_len_table): Replace EXqVexScalarS by EXqS.
1218 (get_valid_dis386): Don't set need_vex_reg.
1219 (print_insn): Don't initialize need_vex_reg.
1220 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1221 q_scalar_swap_mode cases.
1222 (OP_EX): Don't check for d_scalar_swap_mode and
1224 (OP_VEX): Done check need_vex_reg.
1225 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1226 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1227 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1229 2020-07-14 Jan Beulich <jbeulich@suse.com>
1231 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1232 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1233 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1234 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1235 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1236 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1237 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1238 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1239 (vex_table): Replace Vex128 by Vex.
1240 (vex_len_table): Likewise. Adjust referenced enum names.
1241 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1242 referenced enum names.
1243 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1244 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1246 2020-07-14 Jan Beulich <jbeulich@suse.com>
1248 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1249 (putop): Handle "DQ". Don't handle "LW" anymore.
1250 (prefix_table, mod_table): Replace %LW by %DQ.
1251 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1253 2020-07-14 Jan Beulich <jbeulich@suse.com>
1255 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1256 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1257 d_scalar_swap_mode case handling. Move shift adjsutment into
1258 the case its applicable to.
1260 2020-07-14 Jan Beulich <jbeulich@suse.com>
1262 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1263 (EXbScalar, EXwScalar): Fold to ...
1264 (EXbwUnit): ... this.
1265 (b_scalar_mode, w_scalar_mode): Fold to ...
1266 (bw_unit_mode): ... this.
1267 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1268 w_scalar_mode handling by bw_unit_mode one.
1269 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1271 * i386-dis-evex-prefix.h: ... here.
1273 2020-07-14 Jan Beulich <jbeulich@suse.com>
1275 * i386-dis.c (PCMPESTR_Fixup): Delete.
1276 (dis386): Adjust "LQ" description.
1277 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1278 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1279 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1280 vpcmpestrm, and vpcmpestri.
1281 (putop): Honor "cond" when handling LQ.
1282 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1283 vcvtsi2ss and vcvtusi2ss.
1284 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1285 vcvtsi2sd and vcvtusi2sd.
1287 2020-07-14 Jan Beulich <jbeulich@suse.com>
1289 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1290 (simd_cmp_op): Add const.
1291 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1292 (CMP_Fixup): Handle VEX case.
1293 (prefix_table): Replace VCMP by CMP.
1294 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1296 2020-07-14 Jan Beulich <jbeulich@suse.com>
1298 * i386-dis.c (MOVBE_Fixup): Delete.
1300 (prefix_table): Use Mv for movbe entries.
1302 2020-07-14 Jan Beulich <jbeulich@suse.com>
1304 * i386-dis.c (CRC32_Fixup): Delete.
1305 (prefix_table): Use Eb/Ev for crc32 entries.
1307 2020-07-14 Jan Beulich <jbeulich@suse.com>
1309 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1310 Conditionalize invocations of "USED_REX (0)".
1312 2020-07-14 Jan Beulich <jbeulich@suse.com>
1314 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1315 CH, DH, BH, AX, DX): Delete.
1316 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1317 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1318 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1320 2020-07-10 Lili Cui <lili.cui@intel.com>
1322 * i386-dis.c (TMM): New.
1325 (MVexSIBMEM): Likewise.
1326 (tmm_mode): Likewise.
1327 (vex_sibmem_mode): Likewise.
1328 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1329 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1330 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1331 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1332 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1333 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1334 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1335 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1336 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1337 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1338 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1339 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1340 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1341 (PREFIX_VEX_0F3849_X86_64): Likewise.
1342 (PREFIX_VEX_0F384B_X86_64): Likewise.
1343 (PREFIX_VEX_0F385C_X86_64): Likewise.
1344 (PREFIX_VEX_0F385E_X86_64): Likewise.
1345 (X86_64_VEX_0F3849): Likewise.
1346 (X86_64_VEX_0F384B): Likewise.
1347 (X86_64_VEX_0F385C): Likewise.
1348 (X86_64_VEX_0F385E): Likewise.
1349 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1350 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1351 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1352 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1353 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1354 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1355 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1356 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1357 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1358 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1359 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1360 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1361 (VEX_W_0F3849_X86_64_P_0): Likewise.
1362 (VEX_W_0F3849_X86_64_P_2): Likewise.
1363 (VEX_W_0F3849_X86_64_P_3): Likewise.
1364 (VEX_W_0F384B_X86_64_P_1): Likewise.
1365 (VEX_W_0F384B_X86_64_P_2): Likewise.
1366 (VEX_W_0F384B_X86_64_P_3): Likewise.
1367 (VEX_W_0F385C_X86_64_P_1): Likewise.
1368 (VEX_W_0F385E_X86_64_P_0): Likewise.
1369 (VEX_W_0F385E_X86_64_P_1): Likewise.
1370 (VEX_W_0F385E_X86_64_P_2): Likewise.
1371 (VEX_W_0F385E_X86_64_P_3): Likewise.
1372 (names_tmm): Likewise.
1373 (att_names_tmm): Likewise.
1374 (intel_operand_size): Handle void_mode.
1375 (OP_XMM): Handle tmm_mode.
1378 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1379 CpuAMX_BF16 and CpuAMX_TILE.
1380 (operand_type_shorthands): Add RegTMM.
1381 (operand_type_init): Likewise.
1382 (operand_types): Add Tmmword.
1383 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1384 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1385 * i386-opc.h (CpuAMX_INT8): New.
1386 (CpuAMX_BF16): Likewise.
1387 (CpuAMX_TILE): Likewise.
1389 (Tmmword): Likewise.
1390 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1391 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1392 (i386_operand_type): Add tmmword.
1393 * i386-opc.tbl: Add AMX instructions.
1394 * i386-reg.tbl: Add AMX registers.
1395 * i386-init.h: Regenerated.
1396 * i386-tbl.h: Likewise.
1398 2020-07-08 Jan Beulich <jbeulich@suse.com>
1400 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1401 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1403 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1404 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1406 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1407 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1408 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1409 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1410 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1411 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1412 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1413 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1414 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1415 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1416 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1417 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1418 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1419 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1420 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1421 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1422 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1423 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1424 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1425 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1426 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1427 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1428 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1429 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1430 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1431 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1432 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1433 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1434 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1435 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1436 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1437 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1438 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1439 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1440 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1441 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1442 (reg_table): Re-order XOP entries. Adjust their operands.
1443 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1444 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1445 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1446 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1447 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1448 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1449 entries by references ...
1450 (vex_len_table): ... to resepctive new entries here. For several
1451 new and existing entries reference ...
1452 (vex_w_table): ... new entries here.
1453 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1455 2020-07-08 Jan Beulich <jbeulich@suse.com>
1457 * i386-dis.c (XMVexScalarI4): Define.
1458 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1459 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1460 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1461 (vex_len_table): Move scalar FMA4 entries ...
1462 (prefix_table): ... here.
1463 (OP_REG_VexI4): Handle scalar_mode.
1464 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1465 * i386-tbl.h: Re-generate.
1467 2020-07-08 Jan Beulich <jbeulich@suse.com>
1469 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1470 Vex_2src_2): Delete.
1471 (OP_VexW, VexW): New.
1472 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1473 for shifts and rotates by register.
1475 2020-07-08 Jan Beulich <jbeulich@suse.com>
1477 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1478 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1479 OP_EX_VexReg): Delete.
1480 (OP_VexI4, VexI4): New.
1481 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1482 (prefix_table): ... here.
1483 (print_insn): Drop setting of vex_w_done.
1485 2020-07-08 Jan Beulich <jbeulich@suse.com>
1487 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1488 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1489 (xop_table): Replace operands of 4-operand insns.
1490 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1492 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1494 * arc-opc.c (insert_rbd): New function.
1497 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1500 2020-07-07 Jan Beulich <jbeulich@suse.com>
1502 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1503 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1504 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1505 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1507 (putop): Handle "BW".
1508 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1509 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1511 * i386-dis-evex-prefix.h: ... here.
1513 2020-07-06 Jan Beulich <jbeulich@suse.com>
1515 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1516 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1517 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1518 VEX_W_0FXOP_09_83): New enumerators.
1519 (xop_table): Reference the above.
1520 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1521 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1522 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1523 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1525 2020-07-06 Jan Beulich <jbeulich@suse.com>
1527 * i386-dis.c (EVEX_W_0F3838_P_1,
1528 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1529 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1530 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1531 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1532 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1533 (putop): Centralize management of last[]. Delete SAVE_LAST.
1534 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1535 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1536 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1537 * i386-dis-evex-prefix.h: here.
1539 2020-07-06 Jan Beulich <jbeulich@suse.com>
1541 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1542 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1543 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1544 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1546 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1547 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1548 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1549 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1550 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1551 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1552 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1553 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1554 these, respectively.
1555 * i386-dis-evex-len.h: Adjust comments.
1556 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1557 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1558 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1559 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1560 MOD_EVEX_0F385B_P_2_W_1 table entries.
1561 * i386-dis-evex-w.h: Reference mod_table[] for
1562 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1565 2020-07-06 Jan Beulich <jbeulich@suse.com>
1567 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1568 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1570 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1571 Likewise. Mark 256-bit entries invalid.
1573 2020-07-06 Jan Beulich <jbeulich@suse.com>
1575 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1576 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1577 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1578 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1579 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1580 PREFIX_EVEX_0F382B): Delete.
1581 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1582 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1583 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1584 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1585 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1587 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1588 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1589 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1590 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1592 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1593 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1594 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1595 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1596 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1597 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1598 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1599 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1600 PREFIX_EVEX_0F382B): Remove table entries.
1601 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1602 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1603 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1605 2020-07-06 Jan Beulich <jbeulich@suse.com>
1607 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1608 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1610 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1611 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1612 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1613 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1616 2020-07-06 Jan Beulich <jbeulich@suse.com>
1618 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1619 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1620 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1621 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1622 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1623 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1624 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1625 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1626 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1629 2020-07-06 Jan Beulich <jbeulich@suse.com>
1631 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1632 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1633 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1635 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1637 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1639 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1641 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1643 2020-07-06 Jan Beulich <jbeulich@suse.com>
1645 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1646 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1647 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1648 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1649 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1650 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1651 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1652 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1653 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1654 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1655 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1656 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1657 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1658 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1659 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1660 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1661 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1662 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1663 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1664 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1665 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1666 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1667 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1668 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1669 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1670 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1671 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1672 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1673 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1674 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1675 (prefix_table): Add EXxEVexR to FMA table entries.
1676 (OP_Rounding): Move abort() invocation.
1677 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1678 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1679 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1680 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1681 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1682 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1683 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1684 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1685 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1686 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1688 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1689 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1690 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1691 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1692 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1693 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1694 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1695 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1696 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1697 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1698 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1699 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1700 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1701 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1702 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1703 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1704 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1705 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1706 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1707 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1708 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1709 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1710 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1711 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1712 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1713 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1714 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1715 Delete table entries.
1716 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1717 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1718 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1721 2020-07-06 Jan Beulich <jbeulich@suse.com>
1723 * i386-dis.c (EXqScalarS): Delete.
1724 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1725 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1727 2020-07-06 Jan Beulich <jbeulich@suse.com>
1729 * i386-dis.c (safe-ctype.h): Include.
1730 (EXdScalar, EXqScalar): Delete.
1731 (d_scalar_mode, q_scalar_mode): Delete.
1732 (prefix_table, vex_len_table): Use EXxmm_md in place of
1733 EXdScalar and EXxmm_mq in place of EXqScalar.
1734 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1735 d_scalar_mode and q_scalar_mode.
1736 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1737 (vmovsd): Use EXxmm_mq.
1739 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1742 * arc-dis.c: Fix spelling mistake.
1743 * po/opcodes.pot: Regenerate.
1745 2020-07-06 Nick Clifton <nickc@redhat.com>
1747 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1748 * po/uk.po: Updated Ukranian translation.
1750 2020-07-04 Nick Clifton <nickc@redhat.com>
1752 * configure: Regenerate.
1753 * po/opcodes.pot: Regenerate.
1755 2020-07-04 Nick Clifton <nickc@redhat.com>
1757 Binutils 2.35 branch created.
1759 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1761 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1762 * i386-opc.h (VexSwapSources): New.
1763 (i386_opcode_modifier): Add vexswapsources.
1764 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1765 with two source operands swapped.
1766 * i386-tbl.h: Regenerated.
1768 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1770 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1771 unprivileged CSR can also be initialized.
1773 2020-06-29 Alan Modra <amodra@gmail.com>
1775 * arm-dis.c: Use C style comments.
1776 * cr16-opc.c: Likewise.
1777 * ft32-dis.c: Likewise.
1778 * moxie-opc.c: Likewise.
1779 * tic54x-dis.c: Likewise.
1780 * s12z-opc.c: Remove useless comment.
1781 * xgate-dis.c: Likewise.
1783 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1785 * i386-opc.tbl: Add a blank line.
1787 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1789 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1790 (VecSIB128): Renamed to ...
1792 (VecSIB256): Renamed to ...
1794 (VecSIB512): Renamed to ...
1796 (VecSIB): Renamed to ...
1798 (i386_opcode_modifier): Replace vecsib with sib.
1799 * i386-opc.tbl (VecSIB128): New.
1800 (VecSIB256): Likewise.
1801 (VecSIB512): Likewise.
1802 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1803 and VecSIB512, respectively.
1805 2020-06-26 Jan Beulich <jbeulich@suse.com>
1807 * i386-dis.c: Adjust description of I macro.
1808 (x86_64_table): Drop use of I.
1809 (float_mem): Replace use of I.
1810 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1812 2020-06-26 Jan Beulich <jbeulich@suse.com>
1814 * i386-dis.c: (print_insn): Avoid straight assignment to
1815 priv.orig_sizeflag when processing -M sub-options.
1817 2020-06-25 Jan Beulich <jbeulich@suse.com>
1819 * i386-dis.c: Adjust description of J macro.
1820 (dis386, x86_64_table, mod_table): Replace J.
1821 (putop): Remove handling of J.
1823 2020-06-25 Jan Beulich <jbeulich@suse.com>
1825 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1827 2020-06-25 Jan Beulich <jbeulich@suse.com>
1829 * i386-dis.c: Adjust description of "LQ" macro.
1830 (dis386_twobyte): Use LQ for sysret.
1831 (putop): Adjust handling of LQ.
1833 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1835 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1836 * riscv-dis.c: Include elfxx-riscv.h.
1838 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1840 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1842 2020-06-17 Lili Cui <lili.cui@intel.com>
1844 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1846 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1849 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1850 * i386-opc.tbl: Likewise.
1851 * i386-tbl.h: Regenerated.
1853 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1855 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1857 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1859 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1860 (SR_CORE): Likewise.
1861 (SR_FEAT): Likewise.
1863 (SR_V8_1): Likewise.
1864 (SR_V8_2): Likewise.
1865 (SR_V8_3): Likewise.
1866 (SR_V8_4): Likewise.
1869 (SR_SSBS): Likewise.
1871 (SR_ID_PFR2): Likewise.
1872 (SR_PROFILE): Likewise.
1873 (SR_MEMTAG): Likewise.
1874 (SR_SCXTNUM): Likewise.
1875 (aarch64_sys_regs): Refactor to store feature information in the table.
1876 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1877 that now describe their own features.
1878 (aarch64_pstatefield_supported_p): Likewise.
1880 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1882 * i386-dis.c (prefix_table): Fix a typo in comments.
1884 2020-06-09 Jan Beulich <jbeulich@suse.com>
1886 * i386-dis.c (rex_ignored): Delete.
1887 (ckprefix): Drop rex_ignored initialization.
1888 (get_valid_dis386): Drop setting of rex_ignored.
1889 (print_insn): Drop checking of rex_ignored. Don't record data
1890 size prefix as used with VEX-and-alike encodings.
1892 2020-06-09 Jan Beulich <jbeulich@suse.com>
1894 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1895 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1896 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1897 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1898 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1899 VEX_0F12, and VEX_0F16.
1900 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1901 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1902 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1903 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1904 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1905 MOD_VEX_0F16_PREFIX_2 entries.
1907 2020-06-09 Jan Beulich <jbeulich@suse.com>
1909 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1910 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1911 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1912 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1913 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1914 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1915 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1916 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1917 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1918 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1919 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1920 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1921 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1922 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1923 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1924 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1925 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1926 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1927 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1928 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1929 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1930 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1931 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1932 EVEX_W_0FC6_P_2): Delete.
1933 (print_insn): Add EVEX.W vs embedded prefix consistency check
1934 to prefix validation.
1935 * i386-dis-evex.h (evex_table): Don't further descend for
1936 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1937 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1939 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1940 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1941 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1942 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1943 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1944 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1945 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1946 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1947 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1948 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1949 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1950 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1951 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1952 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1953 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1954 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1955 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1956 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1957 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1958 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1959 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1960 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1961 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1962 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1963 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1964 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1965 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1967 2020-06-09 Jan Beulich <jbeulich@suse.com>
1969 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1970 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1971 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1973 (print_insn): Drop pointless check against bad_opcode. Split
1974 prefix validation into legacy and VEX-and-alike parts.
1975 (putop): Re-work 'X' macro handling.
1977 2020-06-09 Jan Beulich <jbeulich@suse.com>
1979 * i386-dis.c (MOD_0F51): Rename to ...
1980 (MOD_0F50): ... this.
1982 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1984 * arm-dis.c (arm_opcodes): Add dfb.
1985 (thumb32_opcodes): Add dfb.
1987 2020-06-08 Jan Beulich <jbeulich@suse.com>
1989 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1991 2020-06-06 Alan Modra <amodra@gmail.com>
1993 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1995 2020-06-05 Alan Modra <amodra@gmail.com>
1997 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1998 size is large enough.
2000 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
2002 * disassemble.c (disassemble_init_for_target): Set endian_code for
2004 * bpf-desc.c: Regenerate.
2005 * bpf-opc.c: Likewise.
2006 * bpf-dis.c: Likewise.
2008 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
2010 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
2011 (cgen_put_insn_value): Likewise.
2012 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
2013 * cgen-dis.in (print_insn): Likewise.
2014 * cgen-ibld.in (insert_1): Likewise.
2015 (insert_1): Likewise.
2016 (insert_insn_normal): Likewise.
2017 (extract_1): Likewise.
2018 * bpf-dis.c: Regenerate.
2019 * bpf-ibld.c: Likewise.
2020 * bpf-ibld.c: Likewise.
2021 * cgen-dis.in: Likewise.
2022 * cgen-ibld.in: Likewise.
2023 * cgen-opc.c: Likewise.
2024 * epiphany-dis.c: Likewise.
2025 * epiphany-ibld.c: Likewise.
2026 * fr30-dis.c: Likewise.
2027 * fr30-ibld.c: Likewise.
2028 * frv-dis.c: Likewise.
2029 * frv-ibld.c: Likewise.
2030 * ip2k-dis.c: Likewise.
2031 * ip2k-ibld.c: Likewise.
2032 * iq2000-dis.c: Likewise.
2033 * iq2000-ibld.c: Likewise.
2034 * lm32-dis.c: Likewise.
2035 * lm32-ibld.c: Likewise.
2036 * m32c-dis.c: Likewise.
2037 * m32c-ibld.c: Likewise.
2038 * m32r-dis.c: Likewise.
2039 * m32r-ibld.c: Likewise.
2040 * mep-dis.c: Likewise.
2041 * mep-ibld.c: Likewise.
2042 * mt-dis.c: Likewise.
2043 * mt-ibld.c: Likewise.
2044 * or1k-dis.c: Likewise.
2045 * or1k-ibld.c: Likewise.
2046 * xc16x-dis.c: Likewise.
2047 * xc16x-ibld.c: Likewise.
2048 * xstormy16-dis.c: Likewise.
2049 * xstormy16-ibld.c: Likewise.
2051 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
2053 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
2054 (print_insn_): Handle instruction endian.
2055 * bpf-dis.c: Regenerate.
2056 * bpf-desc.c: Regenerate.
2057 * epiphany-dis.c: Likewise.
2058 * epiphany-desc.c: Likewise.
2059 * fr30-dis.c: Likewise.
2060 * fr30-desc.c: Likewise.
2061 * frv-dis.c: Likewise.
2062 * frv-desc.c: Likewise.
2063 * ip2k-dis.c: Likewise.
2064 * ip2k-desc.c: Likewise.
2065 * iq2000-dis.c: Likewise.
2066 * iq2000-desc.c: Likewise.
2067 * lm32-dis.c: Likewise.
2068 * lm32-desc.c: Likewise.
2069 * m32c-dis.c: Likewise.
2070 * m32c-desc.c: Likewise.
2071 * m32r-dis.c: Likewise.
2072 * m32r-desc.c: Likewise.
2073 * mep-dis.c: Likewise.
2074 * mep-desc.c: Likewise.
2075 * mt-dis.c: Likewise.
2076 * mt-desc.c: Likewise.
2077 * or1k-dis.c: Likewise.
2078 * or1k-desc.c: Likewise.
2079 * xc16x-dis.c: Likewise.
2080 * xc16x-desc.c: Likewise.
2081 * xstormy16-dis.c: Likewise.
2082 * xstormy16-desc.c: Likewise.
2084 2020-06-03 Nick Clifton <nickc@redhat.com>
2086 * po/sr.po: Updated Serbian translation.
2088 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
2090 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
2091 (riscv_get_priv_spec_class): Likewise.
2093 2020-06-01 Alan Modra <amodra@gmail.com>
2095 * bpf-desc.c: Regenerate.
2097 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
2098 David Faust <david.faust@oracle.com>
2100 * bpf-desc.c: Regenerate.
2101 * bpf-opc.h: Likewise.
2102 * bpf-opc.c: Likewise.
2103 * bpf-dis.c: Likewise.
2105 2020-05-28 Alan Modra <amodra@gmail.com>
2107 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
2110 2020-05-28 Alan Modra <amodra@gmail.com>
2112 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2114 (print_insn_ns32k): Revert last change.
2116 2020-05-28 Nick Clifton <nickc@redhat.com>
2118 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2121 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
2123 Fix extraction of signed constants in nios2 disassembler (again).
2125 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2126 extractions of signed fields.
2128 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2130 * s390-opc.txt: Relocate vector load/store instructions with
2131 additional alignment parameter and change architecture level
2132 constraint from z14 to z13.
2134 2020-05-21 Alan Modra <amodra@gmail.com>
2136 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2137 * sparc-dis.c: Likewise.
2138 * tic4x-dis.c: Likewise.
2139 * xtensa-dis.c: Likewise.
2140 * bpf-desc.c: Regenerate.
2141 * epiphany-desc.c: Regenerate.
2142 * fr30-desc.c: Regenerate.
2143 * frv-desc.c: Regenerate.
2144 * ip2k-desc.c: Regenerate.
2145 * iq2000-desc.c: Regenerate.
2146 * lm32-desc.c: Regenerate.
2147 * m32c-desc.c: Regenerate.
2148 * m32r-desc.c: Regenerate.
2149 * mep-asm.c: Regenerate.
2150 * mep-desc.c: Regenerate.
2151 * mt-desc.c: Regenerate.
2152 * or1k-desc.c: Regenerate.
2153 * xc16x-desc.c: Regenerate.
2154 * xstormy16-desc.c: Regenerate.
2156 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
2158 * riscv-opc.c (riscv_ext_version_table): The table used to store
2159 all information about the supported spec and the corresponding ISA
2160 versions. Currently, only Zicsr is supported to verify the
2161 correctness of Z sub extension settings. Others will be supported
2162 in the future patches.
2163 (struct isa_spec_t, isa_specs): List for all supported ISA spec
2164 classes and the corresponding strings.
2165 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
2166 spec class by giving a ISA spec string.
2167 * riscv-opc.c (struct priv_spec_t): New structure.
2168 (struct priv_spec_t priv_specs): List for all supported privilege spec
2169 classes and the corresponding strings.
2170 (riscv_get_priv_spec_class): New function. Get the corresponding
2171 privilege spec class by giving a spec string.
2172 (riscv_get_priv_spec_name): New function. Get the corresponding
2173 privilege spec string by giving a CSR version class.
2174 * riscv-dis.c: Updated since DECLARE_CSR is changed.
2175 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2176 according to the chosen version. Build a hash table riscv_csr_hash to
2177 store the valid CSR for the chosen pirv verison. Dump the direct
2178 CSR address rather than it's name if it is invalid.
2179 (parse_riscv_dis_option_without_args): New function. Parse the options
2181 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2182 parse the options without arguments first, and then handle the options
2183 with arguments. Add the new option -Mpriv-spec, which has argument.
2184 * riscv-dis.c (print_riscv_disassembler_options): Add description
2185 about the new OBJDUMP option.
2187 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
2189 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2190 WC values on POWER10 sync, dcbf and wait instructions.
2191 (insert_pl, extract_pl): New functions.
2192 (L2OPT, LS, WC): Use insert_ls and extract_ls.
2193 (LS3): New , 3-bit L for sync.
2194 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2195 (SC2, PL): New, 2-bit SC and PL for sync and wait.
2196 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2197 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2198 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2199 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2200 <wait>: Enable PL operand on POWER10.
2201 <dcbf>: Enable L3OPT operand on POWER10.
2202 <sync>: Enable SC2 operand on POWER10.
2204 2020-05-19 Stafford Horne <shorne@gmail.com>
2207 * or1k-asm.c: Regenerate.
2208 * or1k-desc.c: Regenerate.
2209 * or1k-desc.h: Regenerate.
2210 * or1k-dis.c: Regenerate.
2211 * or1k-ibld.c: Regenerate.
2212 * or1k-opc.c: Regenerate.
2213 * or1k-opc.h: Regenerate.
2214 * or1k-opinst.c: Regenerate.
2216 2020-05-11 Alan Modra <amodra@gmail.com>
2218 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2221 2020-05-11 Alan Modra <amodra@gmail.com>
2223 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2224 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2226 2020-05-11 Alan Modra <amodra@gmail.com>
2228 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2230 2020-05-11 Alan Modra <amodra@gmail.com>
2232 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2233 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2235 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2237 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2240 2020-05-11 Alan Modra <amodra@gmail.com>
2242 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2243 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2244 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2245 (prefix_opcodes): Add xxeval.
2247 2020-05-11 Alan Modra <amodra@gmail.com>
2249 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2250 xxgenpcvwm, xxgenpcvdm.
2252 2020-05-11 Alan Modra <amodra@gmail.com>
2254 * ppc-opc.c (MP, VXVAM_MASK): Define.
2255 (VXVAPS_MASK): Use VXVA_MASK.
2256 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2257 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2258 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2259 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2261 2020-05-11 Alan Modra <amodra@gmail.com>
2262 Peter Bergner <bergner@linux.ibm.com>
2264 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2266 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2267 YMSK2, XA6a, XA6ap, XB6a entries.
2268 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2269 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2271 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2272 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2273 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2274 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2275 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2276 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2277 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2278 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2279 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2280 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2281 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2282 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2283 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2284 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2286 2020-05-11 Alan Modra <amodra@gmail.com>
2288 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2289 (insert_xts, extract_xts): New functions.
2290 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2291 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2292 (VXRC_MASK, VXSH_MASK): Define.
2293 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2294 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2295 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2296 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2297 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2298 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2299 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2301 2020-05-11 Alan Modra <amodra@gmail.com>
2303 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2304 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2305 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2306 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2307 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2309 2020-05-11 Alan Modra <amodra@gmail.com>
2311 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2312 (XTP, DQXP, DQXP_MASK): Define.
2313 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2314 (prefix_opcodes): Add plxvp and pstxvp.
2316 2020-05-11 Alan Modra <amodra@gmail.com>
2318 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2319 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2320 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2322 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2324 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2326 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2328 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2330 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2332 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2334 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2336 2020-05-11 Alan Modra <amodra@gmail.com>
2338 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2340 2020-05-11 Alan Modra <amodra@gmail.com>
2342 * ppc-dis.c (ppc_opts): Add "power10" entry.
2343 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2344 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2346 2020-05-11 Nick Clifton <nickc@redhat.com>
2348 * po/fr.po: Updated French translation.
2350 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2352 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2353 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2354 (operand_general_constraint_met_p): validate
2355 AARCH64_OPND_UNDEFINED.
2356 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2358 * aarch64-asm-2.c: Regenerated.
2359 * aarch64-dis-2.c: Regenerated.
2360 * aarch64-opc-2.c: Regenerated.
2362 2020-04-29 Nick Clifton <nickc@redhat.com>
2365 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2368 2020-04-29 Nick Clifton <nickc@redhat.com>
2370 * po/sv.po: Updated Swedish translation.
2372 2020-04-29 Nick Clifton <nickc@redhat.com>
2375 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2376 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2377 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2380 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2383 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2384 cmpi only on m68020up and cpu32.
2386 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2388 * aarch64-asm.c (aarch64_ins_none): New.
2389 * aarch64-asm.h (ins_none): New declaration.
2390 * aarch64-dis.c (aarch64_ext_none): New.
2391 * aarch64-dis.h (ext_none): New declaration.
2392 * aarch64-opc.c (aarch64_print_operand): Update case for
2393 AARCH64_OPND_BARRIER_PSB.
2394 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2395 (AARCH64_OPERANDS): Update inserter/extracter for
2396 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2397 * aarch64-asm-2.c: Regenerated.
2398 * aarch64-dis-2.c: Regenerated.
2399 * aarch64-opc-2.c: Regenerated.
2401 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2403 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2404 (aarch64_feature_ras, RAS): Likewise.
2405 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2406 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2407 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2408 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2409 * aarch64-asm-2.c: Regenerated.
2410 * aarch64-dis-2.c: Regenerated.
2411 * aarch64-opc-2.c: Regenerated.
2413 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2415 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2416 (print_insn_neon): Support disassembly of conditional
2419 2020-02-16 David Faust <david.faust@oracle.com>
2421 * bpf-desc.c: Regenerate.
2422 * bpf-desc.h: Likewise.
2423 * bpf-opc.c: Regenerate.
2424 * bpf-opc.h: Likewise.
2426 2020-04-07 Lili Cui <lili.cui@intel.com>
2428 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2429 (prefix_table): New instructions (see prefixes above).
2430 (rm_table): Likewise
2431 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2432 CPU_ANY_TSXLDTRK_FLAGS.
2433 (cpu_flags): Add CpuTSXLDTRK.
2434 * i386-opc.h (enum): Add CpuTSXLDTRK.
2435 (i386_cpu_flags): Add cputsxldtrk.
2436 * i386-opc.tbl: Add XSUSPLDTRK insns.
2437 * i386-init.h: Regenerate.
2438 * i386-tbl.h: Likewise.
2440 2020-04-02 Lili Cui <lili.cui@intel.com>
2442 * i386-dis.c (prefix_table): New instructions serialize.
2443 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2444 CPU_ANY_SERIALIZE_FLAGS.
2445 (cpu_flags): Add CpuSERIALIZE.
2446 * i386-opc.h (enum): Add CpuSERIALIZE.
2447 (i386_cpu_flags): Add cpuserialize.
2448 * i386-opc.tbl: Add SERIALIZE insns.
2449 * i386-init.h: Regenerate.
2450 * i386-tbl.h: Likewise.
2452 2020-03-26 Alan Modra <amodra@gmail.com>
2454 * disassemble.h (opcodes_assert): Declare.
2455 (OPCODES_ASSERT): Define.
2456 * disassemble.c: Don't include assert.h. Include opintl.h.
2457 (opcodes_assert): New function.
2458 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2459 (bfd_h8_disassemble): Reduce size of data array. Correctly
2460 calculate maxlen. Omit insn decoding when insn length exceeds
2461 maxlen. Exit from nibble loop when looking for E, before
2462 accessing next data byte. Move processing of E outside loop.
2463 Replace tests of maxlen in loop with assertions.
2465 2020-03-26 Alan Modra <amodra@gmail.com>
2467 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2469 2020-03-25 Alan Modra <amodra@gmail.com>
2471 * z80-dis.c (suffix): Init mybuf.
2473 2020-03-22 Alan Modra <amodra@gmail.com>
2475 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2476 successflly read from section.
2478 2020-03-22 Alan Modra <amodra@gmail.com>
2480 * arc-dis.c (find_format): Use ISO C string concatenation rather
2481 than line continuation within a string. Don't access needs_limm
2482 before testing opcode != NULL.
2484 2020-03-22 Alan Modra <amodra@gmail.com>
2486 * ns32k-dis.c (print_insn_arg): Update comment.
2487 (print_insn_ns32k): Reduce size of index_offset array, and
2488 initialize, passing -1 to print_insn_arg for args that are not
2489 an index. Don't exit arg loop early. Abort on bad arg number.
2491 2020-03-22 Alan Modra <amodra@gmail.com>
2493 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2494 * s12z-opc.c: Formatting.
2495 (operands_f): Return an int.
2496 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2497 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2498 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2499 (exg_sex_discrim): Likewise.
2500 (create_immediate_operand, create_bitfield_operand),
2501 (create_register_operand_with_size, create_register_all_operand),
2502 (create_register_all16_operand, create_simple_memory_operand),
2503 (create_memory_operand, create_memory_auto_operand): Don't
2504 segfault on malloc failure.
2505 (z_ext24_decode): Return an int status, negative on fail, zero
2507 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2508 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2509 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2510 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2511 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2512 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2513 (loop_primitive_decode, shift_decode, psh_pul_decode),
2514 (bit_field_decode): Similarly.
2515 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2516 to return value, update callers.
2517 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2518 Don't segfault on NULL operand.
2519 (decode_operation): Return OP_INVALID on first fail.
2520 (decode_s12z): Check all reads, returning -1 on fail.
2522 2020-03-20 Alan Modra <amodra@gmail.com>
2524 * metag-dis.c (print_insn_metag): Don't ignore status from
2527 2020-03-20 Alan Modra <amodra@gmail.com>
2529 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2530 Initialize parts of buffer not written when handling a possible
2531 2-byte insn at end of section. Don't attempt decoding of such
2532 an insn by the 4-byte machinery.
2534 2020-03-20 Alan Modra <amodra@gmail.com>
2536 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2537 partially filled buffer. Prevent lookup of 4-byte insns when
2538 only VLE 2-byte insns are possible due to section size. Print
2539 ".word" rather than ".long" for 2-byte leftovers.
2541 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2544 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2546 2020-03-13 Jan Beulich <jbeulich@suse.com>
2548 * i386-dis.c (X86_64_0D): Rename to ...
2549 (X86_64_0E): ... this.
2551 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2553 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2554 * Makefile.in: Regenerated.
2556 2020-03-09 Jan Beulich <jbeulich@suse.com>
2558 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2560 * i386-tbl.h: Re-generate.
2562 2020-03-09 Jan Beulich <jbeulich@suse.com>
2564 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2565 vprot*, vpsha*, and vpshl*.
2566 * i386-tbl.h: Re-generate.
2568 2020-03-09 Jan Beulich <jbeulich@suse.com>
2570 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2571 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2572 * i386-tbl.h: Re-generate.
2574 2020-03-09 Jan Beulich <jbeulich@suse.com>
2576 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2577 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2578 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2579 * i386-tbl.h: Re-generate.
2581 2020-03-09 Jan Beulich <jbeulich@suse.com>
2583 * i386-gen.c (struct template_arg, struct template_instance,
2584 struct template_param, struct template, templates,
2585 parse_template, expand_templates): New.
2586 (process_i386_opcodes): Various local variables moved to
2587 expand_templates. Call parse_template and expand_templates.
2588 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2589 * i386-tbl.h: Re-generate.
2591 2020-03-06 Jan Beulich <jbeulich@suse.com>
2593 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2594 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2595 register and memory source templates. Replace VexW= by VexW*
2597 * i386-tbl.h: Re-generate.
2599 2020-03-06 Jan Beulich <jbeulich@suse.com>
2601 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2602 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2603 * i386-tbl.h: Re-generate.
2605 2020-03-06 Jan Beulich <jbeulich@suse.com>
2607 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2608 * i386-tbl.h: Re-generate.
2610 2020-03-06 Jan Beulich <jbeulich@suse.com>
2612 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2613 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2614 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2615 VexW0 on SSE2AVX variants.
2616 (vmovq): Drop NoRex64 from XMM/XMM variants.
2617 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2618 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2619 applicable use VexW0.
2620 * i386-tbl.h: Re-generate.
2622 2020-03-06 Jan Beulich <jbeulich@suse.com>
2624 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2625 * i386-opc.h (Rex64): Delete.
2626 (struct i386_opcode_modifier): Remove rex64 field.
2627 * i386-opc.tbl (crc32): Drop Rex64.
2628 Replace Rex64 with Size64 everywhere else.
2629 * i386-tbl.h: Re-generate.
2631 2020-03-06 Jan Beulich <jbeulich@suse.com>
2633 * i386-dis.c (OP_E_memory): Exclude recording of used address
2634 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2635 addressed memory operands for MPX insns.
2637 2020-03-06 Jan Beulich <jbeulich@suse.com>
2639 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2640 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2641 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2642 (ptwrite): Split into non-64-bit and 64-bit forms.
2643 * i386-tbl.h: Re-generate.
2645 2020-03-06 Jan Beulich <jbeulich@suse.com>
2647 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2649 * i386-tbl.h: Re-generate.
2651 2020-03-04 Jan Beulich <jbeulich@suse.com>
2653 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2654 (prefix_table): Move vmmcall here. Add vmgexit.
2655 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2656 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2657 (cpu_flags): Add CpuSEV_ES entry.
2658 * i386-opc.h (CpuSEV_ES): New.
2659 (union i386_cpu_flags): Add cpusev_es field.
2660 * i386-opc.tbl (vmgexit): New.
2661 * i386-init.h, i386-tbl.h: Re-generate.
2663 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2665 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2667 * i386-opc.h (IGNORESIZE): New.
2668 (DEFAULTSIZE): Likewise.
2669 (IgnoreSize): Removed.
2670 (DefaultSize): Likewise.
2671 (MnemonicSize): New.
2672 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2674 * i386-opc.tbl (IgnoreSize): New.
2675 (DefaultSize): Likewise.
2676 * i386-tbl.h: Regenerated.
2678 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2681 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2684 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2687 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2688 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2689 * i386-tbl.h: Regenerated.
2691 2020-02-26 Alan Modra <amodra@gmail.com>
2693 * aarch64-asm.c: Indent labels correctly.
2694 * aarch64-dis.c: Likewise.
2695 * aarch64-gen.c: Likewise.
2696 * aarch64-opc.c: Likewise.
2697 * alpha-dis.c: Likewise.
2698 * i386-dis.c: Likewise.
2699 * nds32-asm.c: Likewise.
2700 * nfp-dis.c: Likewise.
2701 * visium-dis.c: Likewise.
2703 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2705 * arc-regs.h (int_vector_base): Make it available for all ARC
2708 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2710 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2713 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2715 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2716 c.mv/c.li if rs1 is zero.
2718 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2720 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2721 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2723 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2724 * i386-opc.h (CpuABM): Removed.
2726 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2727 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2728 popcnt. Remove CpuABM from lzcnt.
2729 * i386-init.h: Regenerated.
2730 * i386-tbl.h: Likewise.
2732 2020-02-17 Jan Beulich <jbeulich@suse.com>
2734 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2735 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2736 VexW1 instead of open-coding them.
2737 * i386-tbl.h: Re-generate.
2739 2020-02-17 Jan Beulich <jbeulich@suse.com>
2741 * i386-opc.tbl (AddrPrefixOpReg): Define.
2742 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2743 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2744 templates. Drop NoRex64.
2745 * i386-tbl.h: Re-generate.
2747 2020-02-17 Jan Beulich <jbeulich@suse.com>
2750 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2751 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2752 into Intel syntax instance (with Unpsecified) and AT&T one
2754 (vcvtneps2bf16): Likewise, along with folding the two so far
2756 * i386-tbl.h: Re-generate.
2758 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2760 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2761 CPU_ANY_SSE4A_FLAGS.
2763 2020-02-17 Alan Modra <amodra@gmail.com>
2765 * i386-gen.c (cpu_flag_init): Correct last change.
2767 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2769 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2772 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2774 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2777 2020-02-14 Jan Beulich <jbeulich@suse.com>
2780 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2781 destination for Cpu64-only variant.
2782 (movzx): Fold patterns.
2783 * i386-tbl.h: Re-generate.
2785 2020-02-13 Jan Beulich <jbeulich@suse.com>
2787 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2788 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2789 CPU_ANY_SSE4_FLAGS entry.
2790 * i386-init.h: Re-generate.
2792 2020-02-12 Jan Beulich <jbeulich@suse.com>
2794 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2795 with Unspecified, making the present one AT&T syntax only.
2796 * i386-tbl.h: Re-generate.
2798 2020-02-12 Jan Beulich <jbeulich@suse.com>
2800 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2801 * i386-tbl.h: Re-generate.
2803 2020-02-12 Jan Beulich <jbeulich@suse.com>
2806 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2807 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2808 Amd64 and Intel64 templates.
2809 (call, jmp): Likewise for far indirect variants. Dro
2811 * i386-tbl.h: Re-generate.
2813 2020-02-11 Jan Beulich <jbeulich@suse.com>
2815 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2816 * i386-opc.h (ShortForm): Delete.
2817 (struct i386_opcode_modifier): Remove shortform field.
2818 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2819 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2820 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2821 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2823 * i386-tbl.h: Re-generate.
2825 2020-02-11 Jan Beulich <jbeulich@suse.com>
2827 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2828 fucompi): Drop ShortForm from operand-less templates.
2829 * i386-tbl.h: Re-generate.
2831 2020-02-11 Alan Modra <amodra@gmail.com>
2833 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2834 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2835 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2836 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2837 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2839 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2841 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2842 (cde_opcodes): Add VCX* instructions.
2844 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2845 Matthew Malcomson <matthew.malcomson@arm.com>
2847 * arm-dis.c (struct cdeopcode32): New.
2848 (CDE_OPCODE): New macro.
2849 (cde_opcodes): New disassembly table.
2850 (regnames): New option to table.
2851 (cde_coprocs): New global variable.
2852 (print_insn_cde): New
2853 (print_insn_thumb32): Use print_insn_cde.
2854 (parse_arm_disassembler_options): Parse coprocN args.
2856 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2859 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2861 * i386-opc.h (AMD64): Removed.
2862 (Intel64): Likewose.
2864 (INTEL64): Likewise.
2865 (INTEL64ONLY): Likewise.
2866 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2867 * i386-opc.tbl (Amd64): New.
2868 (Intel64): Likewise.
2869 (Intel64Only): Likewise.
2870 Replace AMD64 with Amd64. Update sysenter/sysenter with
2871 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2872 * i386-tbl.h: Regenerated.
2874 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2877 * z80-dis.c: Add support for GBZ80 opcodes.
2879 2020-02-04 Alan Modra <amodra@gmail.com>
2881 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2883 2020-02-03 Alan Modra <amodra@gmail.com>
2885 * m32c-ibld.c: Regenerate.
2887 2020-02-01 Alan Modra <amodra@gmail.com>
2889 * frv-ibld.c: Regenerate.
2891 2020-01-31 Jan Beulich <jbeulich@suse.com>
2893 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2894 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2895 (OP_E_memory): Replace xmm_mdq_mode case label by
2896 vex_scalar_w_dq_mode one.
2897 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2899 2020-01-31 Jan Beulich <jbeulich@suse.com>
2901 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2902 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2903 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2904 (intel_operand_size): Drop vex_w_dq_mode case label.
2906 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2908 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2909 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2911 2020-01-30 Alan Modra <amodra@gmail.com>
2913 * m32c-ibld.c: Regenerate.
2915 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2917 * bpf-opc.c: Regenerate.
2919 2020-01-30 Jan Beulich <jbeulich@suse.com>
2921 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2922 (dis386): Use them to replace C2/C3 table entries.
2923 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2924 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2925 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2926 * i386-tbl.h: Re-generate.
2928 2020-01-30 Jan Beulich <jbeulich@suse.com>
2930 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2932 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2934 * i386-tbl.h: Re-generate.
2936 2020-01-30 Alan Modra <amodra@gmail.com>
2938 * tic4x-dis.c (tic4x_dp): Make unsigned.
2940 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2941 Jan Beulich <jbeulich@suse.com>
2944 * i386-dis.c (MOVSXD_Fixup): New function.
2945 (movsxd_mode): New enum.
2946 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2947 (intel_operand_size): Handle movsxd_mode.
2948 (OP_E_register): Likewise.
2950 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2951 register on movsxd. Add movsxd with 16-bit destination register
2952 for AMD64 and Intel64 ISAs.
2953 * i386-tbl.h: Regenerated.
2955 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2958 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2959 * aarch64-asm-2.c: Regenerate
2960 * aarch64-dis-2.c: Likewise.
2961 * aarch64-opc-2.c: Likewise.
2963 2020-01-21 Jan Beulich <jbeulich@suse.com>
2965 * i386-opc.tbl (sysret): Drop DefaultSize.
2966 * i386-tbl.h: Re-generate.
2968 2020-01-21 Jan Beulich <jbeulich@suse.com>
2970 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2972 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2973 * i386-tbl.h: Re-generate.
2975 2020-01-20 Nick Clifton <nickc@redhat.com>
2977 * po/de.po: Updated German translation.
2978 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2979 * po/uk.po: Updated Ukranian translation.
2981 2020-01-20 Alan Modra <amodra@gmail.com>
2983 * hppa-dis.c (fput_const): Remove useless cast.
2985 2020-01-20 Alan Modra <amodra@gmail.com>
2987 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2989 2020-01-18 Nick Clifton <nickc@redhat.com>
2991 * configure: Regenerate.
2992 * po/opcodes.pot: Regenerate.
2994 2020-01-18 Nick Clifton <nickc@redhat.com>
2996 Binutils 2.34 branch created.
2998 2020-01-17 Christian Biesinger <cbiesinger@google.com>
3000 * opintl.h: Fix spelling error (seperate).
3002 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
3004 * i386-opc.tbl: Add {vex} pseudo prefix.
3005 * i386-tbl.h: Regenerated.
3007 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
3010 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
3011 (neon_opcodes): Likewise.
3012 (select_arm_features): Make sure we enable MVE bits when selecting
3013 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
3016 2020-01-16 Jan Beulich <jbeulich@suse.com>
3018 * i386-opc.tbl: Drop stale comment from XOP section.
3020 2020-01-16 Jan Beulich <jbeulich@suse.com>
3022 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
3023 (extractps): Add VexWIG to SSE2AVX forms.
3024 * i386-tbl.h: Re-generate.
3026 2020-01-16 Jan Beulich <jbeulich@suse.com>
3028 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
3029 Size64 from and use VexW1 on SSE2AVX forms.
3030 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
3031 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
3032 * i386-tbl.h: Re-generate.
3034 2020-01-15 Alan Modra <amodra@gmail.com>
3036 * tic4x-dis.c (tic4x_version): Make unsigned long.
3037 (optab, optab_special, registernames): New file scope vars.
3038 (tic4x_print_register): Set up registernames rather than
3039 malloc'd registertable.
3040 (tic4x_disassemble): Delete optable and optable_special. Use
3041 optab and optab_special instead. Throw away old optab,
3042 optab_special and registernames when info->mach changes.
3044 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
3047 * z80-dis.c (suffix): Use .db instruction to generate double
3050 2020-01-14 Alan Modra <amodra@gmail.com>
3052 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
3053 values to unsigned before shifting.
3055 2020-01-13 Thomas Troeger <tstroege@gmx.de>
3057 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
3059 (print_insn_thumb16, print_insn_thumb32): Likewise.
3060 (print_insn): Initialize the insn info.
3061 * i386-dis.c (print_insn): Initialize the insn info fields, and
3064 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
3066 * arc-opc.c (C_NE): Make it required.
3068 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
3070 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
3071 reserved register name.
3073 2020-01-13 Alan Modra <amodra@gmail.com>
3075 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
3076 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
3078 2020-01-13 Alan Modra <amodra@gmail.com>
3080 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
3081 result of wasm_read_leb128 in a uint64_t and check that bits
3082 are not lost when copying to other locals. Use uint32_t for
3083 most locals. Use PRId64 when printing int64_t.
3085 2020-01-13 Alan Modra <amodra@gmail.com>
3087 * score-dis.c: Formatting.
3088 * score7-dis.c: Formatting.
3090 2020-01-13 Alan Modra <amodra@gmail.com>
3092 * score-dis.c (print_insn_score48): Use unsigned variables for
3093 unsigned values. Don't left shift negative values.
3094 (print_insn_score32): Likewise.
3095 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
3097 2020-01-13 Alan Modra <amodra@gmail.com>
3099 * tic4x-dis.c (tic4x_print_register): Remove dead code.
3101 2020-01-13 Alan Modra <amodra@gmail.com>
3103 * fr30-ibld.c: Regenerate.
3105 2020-01-13 Alan Modra <amodra@gmail.com>
3107 * xgate-dis.c (print_insn): Don't left shift signed value.
3108 (ripBits): Formatting, use 1u.
3110 2020-01-10 Alan Modra <amodra@gmail.com>
3112 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3113 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
3115 2020-01-10 Alan Modra <amodra@gmail.com>
3117 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3118 and XRREG value earlier to avoid a shift with negative exponent.
3119 * m10200-dis.c (disassemble): Similarly.
3121 2020-01-09 Nick Clifton <nickc@redhat.com>
3124 * z80-dis.c (ld_ii_ii): Use correct cast.
3126 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
3129 * z80-dis.c (ld_ii_ii): Use character constant when checking
3132 2020-01-09 Jan Beulich <jbeulich@suse.com>
3134 * i386-dis.c (SEP_Fixup): New.
3136 (dis386_twobyte): Use it for sysenter/sysexit.
3137 (enum x86_64_isa): Change amd64 enumerator to value 1.
3138 (OP_J): Compare isa64 against intel64 instead of amd64.
3139 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3141 * i386-tbl.h: Re-generate.
3143 2020-01-08 Alan Modra <amodra@gmail.com>
3145 * z8k-dis.c: Include libiberty.h
3146 (instr_data_s): Make max_fetched unsigned.
3147 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3148 Don't exceed byte_info bounds.
3149 (output_instr): Make num_bytes unsigned.
3150 (unpack_instr): Likewise for nibl_count and loop.
3151 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3153 * z8k-opc.h: Regenerate.
3155 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
3157 * arc-tbl.h (llock): Use 'LLOCK' as class.
3159 (scond): Use 'SCOND' as class.
3161 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3164 2020-01-06 Alan Modra <amodra@gmail.com>
3166 * m32c-ibld.c: Regenerate.
3168 2020-01-06 Alan Modra <amodra@gmail.com>
3171 * z80-dis.c (suffix): Don't use a local struct buffer copy.
3172 Peek at next byte to prevent recursion on repeated prefix bytes.
3173 Ensure uninitialised "mybuf" is not accessed.
3174 (print_insn_z80): Don't zero n_fetch and n_used here,..
3175 (print_insn_z80_buf): ..do it here instead.
3177 2020-01-04 Alan Modra <amodra@gmail.com>
3179 * m32r-ibld.c: Regenerate.
3181 2020-01-04 Alan Modra <amodra@gmail.com>
3183 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3185 2020-01-04 Alan Modra <amodra@gmail.com>
3187 * crx-dis.c (match_opcode): Avoid shift left of signed value.
3189 2020-01-04 Alan Modra <amodra@gmail.com>
3191 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3193 2020-01-03 Jan Beulich <jbeulich@suse.com>
3195 * aarch64-tbl.h (aarch64_opcode_table): Use
3196 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3198 2020-01-03 Jan Beulich <jbeulich@suse.com>
3200 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3201 forms of SUDOT and USDOT.
3203 2020-01-03 Jan Beulich <jbeulich@suse.com>
3205 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3207 * aarch64-dis-2.c: Re-generate.
3209 2020-01-03 Jan Beulich <jbeulich@suse.com>
3211 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3213 * aarch64-dis-2.c: Re-generate.
3215 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
3217 * z80-dis.c: Add support for eZ80 and Z80 instructions.
3219 2020-01-01 Alan Modra <amodra@gmail.com>
3221 Update year range in copyright notice of all files.
3223 For older changes see ChangeLog-2019
3225 Copyright (C) 2020 Free Software Foundation, Inc.
3227 Copying and distribution of this file, with or without modification,
3228 are permitted in any medium without royalty provided the copyright
3229 notice and this notice are preserved.
3235 version-control: never