opcodes/ChangeLog

   1 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
   2             Edmar Wienskoski <edmar.wienskoski@nxp.com>
   3
   4         * ppc-opc.c (insert_evuimm2_ex0): New function.
   5         (extract_evuimm2_ex0): Likewise.
   6         (insert_evuimm4_ex0): Likewise.
   7         (extract_evuimm4_ex0): Likewise.
   8         (insert_evuimm8_ex0): Likewise.
   9         (extract_evuimm8_ex0): Likewise.
  10         (insert_evuimm_lt16): Likewise.
  11         (extract_evuimm_lt16): Likewise.
  12         (insert_rD_rS_even): Likewise.
  13         (extract_rD_rS_even): Likewise.
  14         (insert_off_lsp): Likewise.
  15         (extract_off_lsp): Likewise.
  16         (RD_EVEN): New operand.
  17         (RS_EVEN): Likewise.
  18         (RSQ): Adjust.
  19         (EVUIMM_LT16): New operand.
  20         (HTM_SI): Adjust.
  21         (EVUIMM_2_EX0): New operand.
  22         (EVUIMM_4): Adjust.
  23         (EVUIMM_4_EX0): New operand.
  24         (EVUIMM_8): Adjust.
  25         (EVUIMM_8_EX0): New operand.
  26         (WS): Adjust.
  27         (VX_OFF): New operand.
  28         (VX_LSP): New macro.
  29         (VX_LSP_MASK): Likewise.
  30         (VX_LSP_OFF_MASK): Likewise.
  31         (PPC_OPCODE_LSP): Likewise.
  32         (vle_opcodes): Add LSP opcodes.
  33         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
  34
  35 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
  36
  37         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
  38         register operands in CRC instructions.
  39         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
  40         comments.
  41
  42 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         * disassemble.c (disassembler): Mark big and mach with
  45         ATTRIBUTE_UNUSED.
  46
  47 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
  48
  49         * disassemble.c (disassembler): Remove arch/mach/endian
  50         assertions.
  51
  52 2017-07-25  Nick Clifton  <nickc@redhat.com>
  53
  54         PR 21739
  55         * arc-opc.c (insert_rhv2): Use lower case first letter in error
  56         message.
  57         (insert_r0): Likewise.
  58         (insert_r1): Likewise.
  59         (insert_r2): Likewise.
  60         (insert_r3): Likewise.
  61         (insert_sp): Likewise.
  62         (insert_gp): Likewise.
  63         (insert_pcl): Likewise.
  64         (insert_blink): Likewise.
  65         (insert_ilink1): Likewise.
  66         (insert_ilink2): Likewise.
  67         (insert_ras): Likewise.
  68         (insert_rbs): Likewise.
  69         (insert_rcs): Likewise.
  70         (insert_simm3s): Likewise.
  71         (insert_rrange): Likewise.
  72         (insert_r13el): Likewise.
  73         (insert_fpel): Likewise.
  74         (insert_blinkel): Likewise.
  75         (insert_pclel): Likewise.
  76         (insert_nps_bitop_size_2b): Likewise.
  77         (insert_nps_imm_offset): Likewise.
  78         (insert_nps_imm_entry): Likewise.
  79         (insert_nps_size_16bit): Likewise.
  80         (insert_nps_##NAME##_pos): Likewise.
  81         (insert_nps_##NAME): Likewise.
  82         (insert_nps_bitop_ins_ext): Likewise.
  83         (insert_nps_##NAME): Likewise.
  84         (insert_nps_min_hofs): Likewise.
  85         (insert_nps_##NAME): Likewise.
  86         (insert_nps_rbdouble_64): Likewise.
  87         (insert_nps_misc_imm_offset): Likewise.
  88         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
  89         option description.
  90
  91 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
  92             Jiong Wang  <jiong.wang@arm.com>
  93
  94         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
  95         correct the print.
  96         * aarch64-dis-2.c: Regenerated.
  97
  98 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  99
 100         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 101         table.
 102
 103 2017-07-20  Nick Clifton  <nickc@redhat.com>
 104
 105         * po/de.po: Updated German translation.
 106
 107 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 108
 109         * arc-regs.h (sec_stat): New aux register.
 110         (aux_kernel_sp): Likewise.
 111         (aux_sec_u_sp): Likewise.
 112         (aux_sec_k_sp): Likewise.
 113         (sec_vecbase_build): Likewise.
 114         (nsc_table_top): Likewise.
 115         (nsc_table_base): Likewise.
 116         (ersec_stat): Likewise.
 117         (aux_sec_except): Likewise.
 118
 119 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 120
 121         * arc-opc.c (extract_uimm12_20): New function.
 122         (UIMM12_20): New operand.
 123         (SIMM3_5_S): Adjust.
 124         * arc-tbl.h (sjli): Add new instruction.
 125
 126 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 127             John Eric Martin  <John.Martin@emmicro-us.com>
 128
 129         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 130         (UIMM3_23): Adjust accordingly.
 131         * arc-regs.h: Add/correct jli_base register.
 132         * arc-tbl.h (jli_s): Likewise.
 133
 134 2017-07-18  Nick Clifton  <nickc@redhat.com>
 135
 136         PR 21775
 137         * aarch64-opc.c: Fix spelling typos.
 138         * i386-dis.c: Likewise.
 139
 140 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 141
 142         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 143         max_addr_offset and octets variables to size_t.
 144
 145 2017-07-12  Alan Modra  <amodra@gmail.com>
 146
 147         * po/da.po: Update from translationproject.org/latest/opcodes/.
 148         * po/de.po: Likewise.
 149         * po/es.po: Likewise.
 150         * po/fi.po: Likewise.
 151         * po/fr.po: Likewise.
 152         * po/id.po: Likewise.
 153         * po/it.po: Likewise.
 154         * po/nl.po: Likewise.
 155         * po/pt_BR.po: Likewise.
 156         * po/ro.po: Likewise.
 157         * po/sv.po: Likewise.
 158         * po/tr.po: Likewise.
 159         * po/uk.po: Likewise.
 160         * po/vi.po: Likewise.
 161         * po/zh_CN.po: Likewise.
 162
 163 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 164             Alan Modra  <amodra@gmail.com>
 165
 166         * cgen.sh: Mark generated files read-only.
 167         * epiphany-asm.c: Regenerate.
 168         * epiphany-desc.c: Regenerate.
 169         * epiphany-desc.h: Regenerate.
 170         * epiphany-dis.c: Regenerate.
 171         * epiphany-ibld.c: Regenerate.
 172         * epiphany-opc.c: Regenerate.
 173         * epiphany-opc.h: Regenerate.
 174         * fr30-asm.c: Regenerate.
 175         * fr30-desc.c: Regenerate.
 176         * fr30-desc.h: Regenerate.
 177         * fr30-dis.c: Regenerate.
 178         * fr30-ibld.c: Regenerate.
 179         * fr30-opc.c: Regenerate.
 180         * fr30-opc.h: Regenerate.
 181         * frv-asm.c: Regenerate.
 182         * frv-desc.c: Regenerate.
 183         * frv-desc.h: Regenerate.
 184         * frv-dis.c: Regenerate.
 185         * frv-ibld.c: Regenerate.
 186         * frv-opc.c: Regenerate.
 187         * frv-opc.h: Regenerate.
 188         * ip2k-asm.c: Regenerate.
 189         * ip2k-desc.c: Regenerate.
 190         * ip2k-desc.h: Regenerate.
 191         * ip2k-dis.c: Regenerate.
 192         * ip2k-ibld.c: Regenerate.
 193         * ip2k-opc.c: Regenerate.
 194         * ip2k-opc.h: Regenerate.
 195         * iq2000-asm.c: Regenerate.
 196         * iq2000-desc.c: Regenerate.
 197         * iq2000-desc.h: Regenerate.
 198         * iq2000-dis.c: Regenerate.
 199         * iq2000-ibld.c: Regenerate.
 200         * iq2000-opc.c: Regenerate.
 201         * iq2000-opc.h: Regenerate.
 202         * lm32-asm.c: Regenerate.
 203         * lm32-desc.c: Regenerate.
 204         * lm32-desc.h: Regenerate.
 205         * lm32-dis.c: Regenerate.
 206         * lm32-ibld.c: Regenerate.
 207         * lm32-opc.c: Regenerate.
 208         * lm32-opc.h: Regenerate.
 209         * lm32-opinst.c: Regenerate.
 210         * m32c-asm.c: Regenerate.
 211         * m32c-desc.c: Regenerate.
 212         * m32c-desc.h: Regenerate.
 213         * m32c-dis.c: Regenerate.
 214         * m32c-ibld.c: Regenerate.
 215         * m32c-opc.c: Regenerate.
 216         * m32c-opc.h: Regenerate.
 217         * m32r-asm.c: Regenerate.
 218         * m32r-desc.c: Regenerate.
 219         * m32r-desc.h: Regenerate.
 220         * m32r-dis.c: Regenerate.
 221         * m32r-ibld.c: Regenerate.
 222         * m32r-opc.c: Regenerate.
 223         * m32r-opc.h: Regenerate.
 224         * m32r-opinst.c: Regenerate.
 225         * mep-asm.c: Regenerate.
 226         * mep-desc.c: Regenerate.
 227         * mep-desc.h: Regenerate.
 228         * mep-dis.c: Regenerate.
 229         * mep-ibld.c: Regenerate.
 230         * mep-opc.c: Regenerate.
 231         * mep-opc.h: Regenerate.
 232         * mt-asm.c: Regenerate.
 233         * mt-desc.c: Regenerate.
 234         * mt-desc.h: Regenerate.
 235         * mt-dis.c: Regenerate.
 236         * mt-ibld.c: Regenerate.
 237         * mt-opc.c: Regenerate.
 238         * mt-opc.h: Regenerate.
 239         * or1k-asm.c: Regenerate.
 240         * or1k-desc.c: Regenerate.
 241         * or1k-desc.h: Regenerate.
 242         * or1k-dis.c: Regenerate.
 243         * or1k-ibld.c: Regenerate.
 244         * or1k-opc.c: Regenerate.
 245         * or1k-opc.h: Regenerate.
 246         * or1k-opinst.c: Regenerate.
 247         * xc16x-asm.c: Regenerate.
 248         * xc16x-desc.c: Regenerate.
 249         * xc16x-desc.h: Regenerate.
 250         * xc16x-dis.c: Regenerate.
 251         * xc16x-ibld.c: Regenerate.
 252         * xc16x-opc.c: Regenerate.
 253         * xc16x-opc.h: Regenerate.
 254         * xstormy16-asm.c: Regenerate.
 255         * xstormy16-desc.c: Regenerate.
 256         * xstormy16-desc.h: Regenerate.
 257         * xstormy16-dis.c: Regenerate.
 258         * xstormy16-ibld.c: Regenerate.
 259         * xstormy16-opc.c: Regenerate.
 260         * xstormy16-opc.h: Regenerate.
 261
 262 2017-07-07  Alan Modra  <amodra@gmail.com>
 263
 264         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 265         * m32c-dis.c: Regenerate.
 266         * mep-dis.c: Regenerate.
 267
 268 2017-07-05  Borislav Petkov  <bp@suse.de>
 269
 270         * i386-dis.c: Enable ModRM.reg /6 aliases.
 271
 272 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 273
 274         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 275         with vmrs and vmsr.
 276
 277 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 278
 279         * configure: Regenerate.
 280
 281 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 282
 283         * po/opcodes.pot: Regenerate.
 284
 285 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 286
 287         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 288         entries to the MSA ASE instruction block.
 289
 290 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 291             Maciej W. Rozycki  <macro@imgtec.com>
 292
 293         * micromips-opc.c (XPA, XPAVZ): New macros.
 294         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 295         "mthgc0".
 296
 297 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 298             Maciej W. Rozycki  <macro@imgtec.com>
 299
 300         * micromips-opc.c (I36): New macro.
 301         (micromips_opcodes): Add "eretnc".
 302
 303 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 304             Andrew Bennett  <andrew.bennett@imgtec.com>
 305
 306         * mips-dis.c (mips_calculate_combination_ases): Handle the
 307         ASE_XPA_VIRT flag.
 308         (parse_mips_ase_option): New function.
 309         (parse_mips_dis_option): Factor out ASE option handling to the
 310         new function.  Call `mips_calculate_combination_ases'.
 311         * mips-opc.c (XPAVZ): New macro.
 312         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 313         "mfhgc0", "mthc0" and "mthgc0".
 314
 315 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 316
 317         * mips-dis.c (mips_calculate_combination_ases): New function.
 318         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 319         calculation to the new function.
 320         (set_default_mips_dis_options): Call the new function.
 321
 322 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 323
 324         * arc-dis.c (parse_disassembler_options): Use
 325         FOR_EACH_DISASSEMBLER_OPTION.
 326
 327 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 328
 329         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 330         disassembler option strings.
 331         (parse_cpu_option): Likewise.
 332
 333 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 334
 335         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 336         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 337         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 338         (aarch64_feature_dotprod, DOT_INSN): New.
 339         (udot, sdot): New.
 340         * aarch64-dis-2.c: Regenerated.
 341
 342 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 343
 344         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 345
 346 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 347             Matthew Fortune  <matthew.fortune@imgtec.com>
 348             Andrew Bennett  <andrew.bennett@imgtec.com>
 349
 350         * mips-formats.h (INT_BIAS): New macro.
 351         (INT_ADJ): Redefine in INT_BIAS terms.
 352         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 353         (mips_print_save_restore): New function.
 354         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 355         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 356         call.
 357         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 358         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 359         OP_SAVE_RESTORE_LIST handling, factored out from here.
 360         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 361         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 362         (mips_builtin_opcodes): Add "restore" and "save" entries.
 363         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 364         (IAMR2): New macro.
 365         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 366
 367 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 368
 369         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 370         alias; do not mark SLTI instruction as an alias.
 371
 372 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 373
 374         * i386-dis.c (RM_0FAE_REG_5): Removed.
 375         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 376         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 377         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 378         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 379         PREFIX_MOD_3_0F01_REG_5_RM_0.
 380         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 381         PREFIX_MOD_3_0FAE_REG_5.
 382         (mod_table): Update MOD_0FAE_REG_5.
 383         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 384         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 385         * i386-tbl.h: Regenerated.
 386
 387 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 388
 389         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 390         * i386-opc.tbl: Likewise.
 391         * i386-tbl.h: Regenerated.
 392
 393 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 394
 395         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 396         and "jmp{&|}".
 397         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 398         prefix.
 399
 400 2017-06-19  Nick Clifton  <nickc@redhat.com>
 401
 402         PR binutils/21614
 403         * score-dis.c (score_opcodes): Add sentinel.
 404
 405 2017-06-16  Alan Modra  <amodra@gmail.com>
 406
 407         * rx-decode.c: Regenerate.
 408
 409 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 410
 411         PR binutils/21594
 412         * i386-dis.c (OP_E_register): Check valid bnd register.
 413         (OP_G): Likewise.
 414
 415 2017-06-15  Nick Clifton  <nickc@redhat.com>
 416
 417         PR binutils/21595
 418         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 419         range value.
 420
 421 2017-06-15  Nick Clifton  <nickc@redhat.com>
 422
 423         PR binutils/21588
 424         * rl78-decode.opc (OP_BUF_LEN): Define.
 425         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 426         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 427         array.
 428         * rl78-decode.c: Regenerate.
 429
 430 2017-06-15  Nick Clifton  <nickc@redhat.com>
 431
 432         PR binutils/21586
 433         * bfin-dis.c (gregs): Clip index to prevent overflow.
 434         (regs): Likewise.
 435         (regs_lo): Likewise.
 436         (regs_hi): Likewise.
 437
 438 2017-06-14  Nick Clifton  <nickc@redhat.com>
 439
 440         PR binutils/21576
 441         * score7-dis.c (score_opcodes): Add sentinel.
 442
 443 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 444
 445         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 446         * arm-dis.c: Likewise.
 447         * ia64-dis.c: Likewise.
 448         * mips-dis.c: Likewise.
 449         * spu-dis.c: Likewise.
 450         * disassemble.h (print_insn_aarch64): New declaration, moved from
 451         include/dis-asm.h.
 452         (print_insn_big_arm, print_insn_big_mips): Likewise.
 453         (print_insn_i386, print_insn_ia64): Likewise.
 454         (print_insn_little_arm, print_insn_little_mips): Likewise.
 455
 456 2017-06-14  Nick Clifton  <nickc@redhat.com>
 457
 458         PR binutils/21587
 459         * rx-decode.opc: Include libiberty.h
 460         (GET_SCALE): New macro - validates access to SCALE array.
 461         (GET_PSCALE): New macro - validates access to PSCALE array.
 462         (DIs, SIs, S2Is, rx_disp): Use new macros.
 463         * rx-decode.c: Regenerate.
 464
 465 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 466
 467         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 468
 469 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 470
 471         * arc-dis.c (enforced_isa_mask): Declare.
 472         (cpu_types): Likewise.
 473         (parse_cpu_option): New function.
 474         (parse_disassembler_options): Use it.
 475         (print_insn_arc): Use enforced_isa_mask.
 476         (print_arc_disassembler_options): Document new options.
 477
 478 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 479
 480         * alpha-dis.c: Include disassemble.h, don't include
 481         dis-asm.h.
 482         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 483         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 484         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 485         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 486         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 487         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 488         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 489         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 490         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 491         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 492         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 493         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 494         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 495         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 496         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 497         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 498         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 499         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 500         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 501         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 502         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 503         * z80-dis.c, z8k-dis.c: Likewise.
 504         * disassemble.h: New file.
 505
 506 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 507
 508         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 509         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 510
 511 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 512
 513         * disassemble.c (disassembler): Add arguments a, big and mach.
 514         Use them.
 515
 516 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 517
 518         * i386-dis.c (NOTRACK_Fixup): New.
 519         (NOTRACK): Likewise.
 520         (NOTRACK_PREFIX): Likewise.
 521         (last_active_prefix): Likewise.
 522         (reg_table): Use NOTRACK on indirect call and jmp.
 523         (ckprefix): Set last_active_prefix.
 524         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 525         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 526         * i386-opc.h (NoTrackPrefixOk): New.
 527         (i386_opcode_modifier): Add notrackprefixok.
 528         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 529         Add notrack.
 530         * i386-tbl.h: Regenerated.
 531
 532 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 533
 534         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 535         (X_IMM2): Define.
 536         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 537         bfd_mach_sparc_v9m8.
 538         (print_insn_sparc): Handle new operand types.
 539         * sparc-opc.c (MASK_M8): Define.
 540         (v6): Add MASK_M8.
 541         (v6notlet): Likewise.
 542         (v7): Likewise.
 543         (v8): Likewise.
 544         (v9): Likewise.
 545         (v9a): Likewise.
 546         (v9b): Likewise.
 547         (v9c): Likewise.
 548         (v9d): Likewise.
 549         (v9e): Likewise.
 550         (v9v): Likewise.
 551         (v9m): Likewise.
 552         (v9andleon): Likewise.
 553         (m8): Define.
 554         (HWS_VM8): Define.
 555         (HWS2_VM8): Likewise.
 556         (sparc_opcode_archs): Add entry for "m8".
 557         (sparc_opcodes): Add OSA2017 and M8 instructions
 558         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 559         fpx{ll,ra,rl}64x,
 560         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 561         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 562         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 563         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 564         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 565         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 566         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 567         ASI_CORE_SELECT_COMMIT_NHT.
 568
 569 2017-05-18  Alan Modra  <amodra@gmail.com>
 570
 571         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 572         * aarch64-dis.c: Likewise.
 573         * aarch64-gen.c: Likewise.
 574         * aarch64-opc.c: Likewise.
 575
 576 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 577             Matthew Fortune  <matthew.fortune@imgtec.com>
 578
 579         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 580         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 581         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 582         (print_insn_arg) <OP_REG28>: Add handler.
 583         (validate_insn_args) <OP_REG28>: Handle.
 584         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 585         32-bit encoding and 9-bit immediates.
 586         (print_insn_mips16): Handle MIPS16 instructions that require
 587         32-bit encoding and MFC0/MTC0 operand decoding.
 588         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 589         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 590         (RD_C0, WR_C0, E2, E2MT): New macros.
 591         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 592         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 593         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 594         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 595         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 596         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 597         instructions, "swl", "swr", "sync" and its "sync_acquire",
 598         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 599         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 600         regular/extended entries for original MIPS16 ISA revision
 601         instructions whose extended forms are subdecoded in the MIPS16e2
 602         ISA revision: "li", "sll" and "srl".
 603
 604 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 605
 606         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 607         reference in CP0 move operand decoding.
 608
 609 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 610
 611         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 612         type to hexadecimal.
 613         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 614
 615 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 616
 617         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 618         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 619         "sync_rmb" and "sync_wmb" as aliases.
 620         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 621         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 622
 623 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 624
 625         * arc-dis.c (parse_option): Update quarkse_em option..
 626         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 627         QUARKSE1.
 628         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 629
 630 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 631
 632         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 633
 634 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 635
 636         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 637         register.
 638
 639 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 640
 641         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 642         and branches and not synthetic data instructions.
 643
 644 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 645
 646         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 647
 648 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 649
 650         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 651         * arc-opc.c (insert_r13el): New function.
 652         (R13_EL): Define.
 653         * arc-tbl.h: Add new enter/leave variants.
 654
 655 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 656
 657         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 658
 659 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 660
 661         * mips-dis.c (print_mips_disassembler_options): Add
 662         `no-aliases'.
 663
 664 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 665
 666         * mips16-opc.c (AL): New macro.
 667         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 668         of "ld" and "lw" as aliases.
 669
 670 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 671
 672         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 673         arguments.
 674
 675 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 676             Alan Modra  <amodra@gmail.com>
 677
 678         * ppc-opc.c (ELEV): Define.
 679         (vle_opcodes): Add se_rfgi and e_sc.
 680         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 681         for E200Z4.
 682
 683 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 684
 685         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 686
 687 2017-04-21  Nick Clifton  <nickc@redhat.com>
 688
 689         PR binutils/21380
 690         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 691         LD3R and LD4R.
 692
 693 2017-04-13  Alan Modra  <amodra@gmail.com>
 694
 695         * epiphany-desc.c: Regenerate.
 696         * fr30-desc.c: Regenerate.
 697         * frv-desc.c: Regenerate.
 698         * ip2k-desc.c: Regenerate.
 699         * iq2000-desc.c: Regenerate.
 700         * lm32-desc.c: Regenerate.
 701         * m32c-desc.c: Regenerate.
 702         * m32r-desc.c: Regenerate.
 703         * mep-desc.c: Regenerate.
 704         * mt-desc.c: Regenerate.
 705         * or1k-desc.c: Regenerate.
 706         * xc16x-desc.c: Regenerate.
 707         * xstormy16-desc.c: Regenerate.
 708
 709 2017-04-11  Alan Modra  <amodra@gmail.com>
 710
 711         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 712         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 713         PPC_OPCODE_TMR for e6500.
 714         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 715         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 716         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 717         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 718         (PPCHTM): Define as PPC_OPCODE_POWER8.
 719         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 720
 721 2017-04-10  Alan Modra  <amodra@gmail.com>
 722
 723         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 724         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 725         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 726         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 727
 728 2017-04-09  Pip Cet  <pipcet@gmail.com>
 729
 730         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 731         appropriate floating-point precision directly.
 732
 733 2017-04-07  Alan Modra  <amodra@gmail.com>
 734
 735         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 736         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 737         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 738         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 739         vector instructions with E6500 not PPCVEC2.
 740
 741 2017-04-06  Pip Cet  <pipcet@gmail.com>
 742
 743         * Makefile.am: Add wasm32-dis.c.
 744         * configure.ac: Add wasm32-dis.c to wasm32 target.
 745         * disassemble.c: Add wasm32 disassembler code.
 746         * wasm32-dis.c: New file.
 747         * Makefile.in: Regenerate.
 748         * configure: Regenerate.
 749         * po/POTFILES.in: Regenerate.
 750         * po/opcodes.pot: Regenerate.
 751
 752 2017-04-05  Pedro Alves  <palves@redhat.com>
 753
 754         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 755         * arm-dis.c (parse_arm_disassembler_options): Constify.
 756         * ppc-dis.c (powerpc_init_dialect): Constify local.
 757         * vax-dis.c (parse_disassembler_options): Constify.
 758
 759 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 760
 761         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 762         RISCV_GP_SYMBOL.
 763
 764 2017-03-30  Pip Cet  <pipcet@gmail.com>
 765
 766         * configure.ac: Add (empty) bfd_wasm32_arch target.
 767         * configure: Regenerate
 768         * po/opcodes.pot: Regenerate.
 769
 770 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 771
 772         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 773         OSA2015.
 774         * opcodes/sparc-opc.c (asi_table): New ASIs.
 775
 776 2017-03-29  Alan Modra  <amodra@gmail.com>
 777
 778         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 779         "raw" option.
 780         (lookup_powerpc): Don't special case -1 dialect.  Handle
 781         PPC_OPCODE_RAW.
 782         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 783         lookup_powerpc call, pass it on second.
 784
 785 2017-03-27  Alan Modra  <amodra@gmail.com>
 786
 787         PR 21303
 788         * ppc-dis.c (struct ppc_mopt): Comment.
 789         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 790
 791 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 792
 793         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 794         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 795         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 796         (insert_nps_misc_imm_offset): New function.
 797         (extract_nps_misc imm_offset): New function.
 798         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 799         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 800
 801 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 802
 803         * s390-mkopc.c (main): Remove vx2 check.
 804         * s390-opc.txt: Remove vx2 instruction flags.
 805
 806 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 807
 808         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 809         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 810         (insert_nps_imm_offset): New function.
 811         (extract_nps_imm_offset): New function.
 812         (insert_nps_imm_entry): New function.
 813         (extract_nps_imm_entry): New function.
 814
 815 2017-03-17  Alan Modra  <amodra@gmail.com>
 816
 817         PR 21248
 818         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 819         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 820         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 821
 822 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 823
 824         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 825         <c.andi>: Likewise.
 826         <c.addiw> Likewise.
 827
 828 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 829
 830         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 831
 832 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 833
 834         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 835         <srl> Likewise.
 836         <srai> Likewise.
 837         <sra> Likewise.
 838
 839 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 840
 841         * i386-gen.c (opcode_modifiers): Replace S with Load.
 842         * i386-opc.h (S): Removed.
 843         (Load): New.
 844         (i386_opcode_modifier): Replace s with load.
 845         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 846         and {evex}.  Replace S with Load.
 847         * i386-tbl.h: Regenerated.
 848
 849 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 850
 851         * i386-opc.tbl: Use CpuCET on rdsspq.
 852         * i386-tbl.h: Regenerated.
 853
 854 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 855
 856         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 857         <vsx>: Do not use PPC_OPCODE_VSX3;
 858
 859 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 860
 861         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 862
 863 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 866         (MOD_0F1E_PREFIX_1): Likewise.
 867         (MOD_0F38F5_PREFIX_2): Likewise.
 868         (MOD_0F38F6_PREFIX_0): Likewise.
 869         (RM_0F1E_MOD_3_REG_7): Likewise.
 870         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 871         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 872         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 873         (PREFIX_0F1E): Likewise.
 874         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 875         (PREFIX_0F38F5): Likewise.
 876         (dis386_twobyte): Use PREFIX_0F1E.
 877         (reg_table): Add REG_0F1E_MOD_3.
 878         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 879         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 880         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 881         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 882         (three_byte_table): Use PREFIX_0F38F5.
 883         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 884         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 885         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 886         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 887         PREFIX_MOD_3_0F01_REG_5_RM_2.
 888         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 889         (cpu_flags): Add CpuCET.
 890         * i386-opc.h (CpuCET): New enum.
 891         (CpuUnused): Commented out.
 892         (i386_cpu_flags): Add cpucet.
 893         * i386-opc.tbl: Add Intel CET instructions.
 894         * i386-init.h: Regenerated.
 895         * i386-tbl.h: Likewise.
 896
 897 2017-03-06  Alan Modra  <amodra@gmail.com>
 898
 899         PR 21124
 900         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 901         (extract_raq, extract_ras, extract_rbx): New functions.
 902         (powerpc_operands): Use opposite corresponding insert function.
 903         (Q_MASK): Define.
 904         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 905         register restriction.
 906
 907 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 908
 909         * disassemble.c Include "safe-ctype.h".
 910         (disassemble_init_for_target): Handle s390 init.
 911         (remove_whitespace_and_extra_commas): New function.
 912         (disassembler_options_cmp): Likewise.
 913         * arm-dis.c: Include "libiberty.h".
 914         (NUM_ELEM): Delete.
 915         (regnames): Use long disassembler style names.
 916         Add force-thumb and no-force-thumb options.
 917         (NUM_ARM_REGNAMES): Rename from this...
 918         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 919         (get_arm_regname_num_options): Delete.
 920         (set_arm_regname_option): Likewise.
 921         (get_arm_regnames): Likewise.
 922         (parse_disassembler_options): Likewise.
 923         (parse_arm_disassembler_option): Rename from this...
 924         (parse_arm_disassembler_options): ...to this.  Make static.
 925         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 926         (print_insn): Use parse_arm_disassembler_options.
 927         (disassembler_options_arm): New function.
 928         (print_arm_disassembler_options): Handle updated regnames.
 929         * ppc-dis.c: Include "libiberty.h".
 930         (ppc_opts): Add "32" and "64" entries.
 931         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 932         (powerpc_init_dialect): Add break to switch statement.
 933         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 934         (disassembler_options_powerpc): New function.
 935         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 936         Remove printing of "32" and "64".
 937         * s390-dis.c: Include "libiberty.h".
 938         (init_flag): Remove unneeded variable.
 939         (struct s390_options_t): New structure type.
 940         (options): New structure.
 941         (init_disasm): Rename from this...
 942         (disassemble_init_s390): ...to this.  Add initializations for
 943         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 944         (print_insn_s390): Delete call to init_disasm.
 945         (disassembler_options_s390): New function.
 946         (print_s390_disassembler_options): Print using information from
 947         struct 'options'.
 948         * po/opcodes.pot: Regenerate.
 949
 950 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 951
 952         * i386-dis.c (PCMPESTR_Fixup): New.
 953         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 954         (prefix_table): Use PCMPESTR_Fixup.
 955         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 956         PCMPESTR_Fixup.
 957         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 958         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 959         Split 64-bit and non-64-bit variants.
 960         * opcodes/i386-tbl.h: Re-generate.
 961
 962 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 963
 964         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 965         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 966         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 967         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 968         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 969         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 970         (OP_SVE_V_HSD): New macros.
 971         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 972         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 973         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 974         (aarch64_opcode_table): Add new SVE instructions.
 975         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 976         for rotation operands.  Add new SVE operands.
 977         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 978         (ins_sve_quad_index): Likewise.
 979         (ins_imm_rotate): Split into...
 980         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 981         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 982         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 983         functions.
 984         (aarch64_ins_sve_addr_ri_s4): New function.
 985         (aarch64_ins_sve_quad_index): Likewise.
 986         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 987         * aarch64-asm-2.c: Regenerate.
 988         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 989         (ext_sve_quad_index): Likewise.
 990         (ext_imm_rotate): Split into...
 991         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 992         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 993         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 994         functions.
 995         (aarch64_ext_sve_addr_ri_s4): New function.
 996         (aarch64_ext_sve_quad_index): Likewise.
 997         (aarch64_ext_sve_index): Allow quad indices.
 998         (do_misc_decoding): Likewise.
 999         * aarch64-dis-2.c: Regenerate.
1000         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1001         aarch64_field_kinds.
1002         (OPD_F_OD_MASK): Widen by one bit.
1003         (OPD_F_NO_ZR): Bump accordingly.
1004         (get_operand_field_width): New function.
1005         * aarch64-opc.c (fields): Add new SVE fields.
1006         (operand_general_constraint_met_p): Handle new SVE operands.
1007         (aarch64_print_operand): Likewise.
1008         * aarch64-opc-2.c: Regenerate.
1009
1010 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1011
1012         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1013         (aarch64_feature_compnum): ...this.
1014         (SIMD_V8_3): Replace with...
1015         (COMPNUM): ...this.
1016         (CNUM_INSN): New macro.
1017         (aarch64_opcode_table): Use it for the complex number instructions.
1018
1019 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1022
1023 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1024
1025         Add support for associating SPARC ASIs with an architecture level.
1026         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1027         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1028         decoding of SPARC ASIs.
1029
1030 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1033         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1034
1035 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1036
1037         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1038         1 (instead of to itself). Correct typo.
1039
1040 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1041
1042         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1043         pseudoinstructions.
1044
1045 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1046
1047         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1048         (aarch64_sys_reg_supported_p): Handle them.
1049
1050 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1051
1052         * arc-opc.c (UIMM6_20R): Define.
1053         (SIMM12_20): Use above.
1054         (SIMM12_20R): Define.
1055         (SIMM3_5_S): Use above.
1056         (UIMM7_A32_11R_S): Define.
1057         (UIMM7_9_S): Use above.
1058         (UIMM3_13R_S): Define.
1059         (SIMM11_A32_7_S): Use above.
1060         (SIMM9_8R): Define.
1061         (UIMM10_A32_8_S): Use above.
1062         (UIMM8_8R_S): Define.
1063         (W6): Use above.
1064         (arc_relax_opcodes): Use all above defines.
1065
1066 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1067
1068         * arc-regs.h: Distinguish some of the registers different on
1069         ARC700 and HS38 cpus.
1070
1071 2017-02-14  Alan Modra  <amodra@gmail.com>
1072
1073         PR 21118
1074         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1075         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1076
1077 2017-02-11  Stafford Horne  <shorne@gmail.com>
1078             Alan Modra  <amodra@gmail.com>
1079
1080         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1081         Use insn_bytes_value and insn_int_value directly instead.  Don't
1082         free allocated memory until function exit.
1083
1084 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1085
1086         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1087
1088 2017-02-03  Nick Clifton  <nickc@redhat.com>
1089
1090         PR 21096
1091         * aarch64-opc.c (print_register_list): Ensure that the register
1092         list index will fir into the tb buffer.
1093         (print_register_offset_address): Likewise.
1094         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1095
1096 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1097
1098         PR 21056
1099         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1100         instructions when the previous fetch packet ends with a 32-bit
1101         instruction.
1102
1103 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1104
1105         * pru-opc.c: Remove vague reference to a future GDB port.
1106
1107 2017-01-20  Nick Clifton  <nickc@redhat.com>
1108
1109         * po/ga.po: Updated Irish translation.
1110
1111 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1112
1113         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1114
1115 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1116
1117         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1118         if FETCH_DATA returns 0.
1119         (m68k_scan_mask): Likewise.
1120         (print_insn_m68k): Update code to handle -1 return value.
1121
1122 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1123
1124         * m68k-dis.c (enum print_insn_arg_error): New.
1125         (NEXTBYTE): Replace -3 with
1126         PRINT_INSN_ARG_MEMORY_ERROR.
1127         (NEXTULONG): Likewise.
1128         (NEXTSINGLE): Likewise.
1129         (NEXTDOUBLE): Likewise.
1130         (NEXTDOUBLE): Likewise.
1131         (NEXTPACKED): Likewise.
1132         (FETCH_ARG): Likewise.
1133         (FETCH_DATA): Update comments.
1134         (print_insn_arg): Update comments. Replace magic numbers with
1135         enum.
1136         (match_insn_m68k): Likewise.
1137
1138 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1139
1140         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1141         * i386-dis-evex.h (evex_table): Updated.
1142         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1143         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1144         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1145         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1146         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1147         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1148         * i386-init.h: Regenerate.
1149         * i386-tbl.h: Ditto.
1150
1151 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1152
1153         * msp430-dis.c (msp430_singleoperand): Return -1 if
1154         msp430dis_opcode_signed returns false.
1155         (msp430_doubleoperand): Likewise.
1156         (msp430_branchinstr): Return -1 if
1157         msp430dis_opcode_unsigned returns false.
1158         (msp430x_calla_instr): Likewise.
1159         (print_insn_msp430): Likewise.
1160
1161 2017-01-05  Nick Clifton  <nickc@redhat.com>
1162
1163         PR 20946
1164         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1165         could not be matched.
1166         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1167         NULL.
1168
1169 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1170
1171         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1172         (aarch64_opcode_table): Use RCPC_INSN.
1173
1174 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1175
1176         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1177         extension.
1178         * riscv-opcodes/all-opcodes: Likewise.
1179
1180 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1181
1182         * riscv-dis.c (print_insn_args): Add fall through comment.
1183
1184 2017-01-03  Nick Clifton  <nickc@redhat.com>
1185
1186         * po/sr.po: New Serbian translation.
1187         * configure.ac (ALL_LINGUAS): Add sr.
1188         * configure: Regenerate.
1189
1190 2017-01-02  Alan Modra  <amodra@gmail.com>
1191
1192         * epiphany-desc.h: Regenerate.
1193         * epiphany-opc.h: Regenerate.
1194         * fr30-desc.h: Regenerate.
1195         * fr30-opc.h: Regenerate.
1196         * frv-desc.h: Regenerate.
1197         * frv-opc.h: Regenerate.
1198         * ip2k-desc.h: Regenerate.
1199         * ip2k-opc.h: Regenerate.
1200         * iq2000-desc.h: Regenerate.
1201         * iq2000-opc.h: Regenerate.
1202         * lm32-desc.h: Regenerate.
1203         * lm32-opc.h: Regenerate.
1204         * m32c-desc.h: Regenerate.
1205         * m32c-opc.h: Regenerate.
1206         * m32r-desc.h: Regenerate.
1207         * m32r-opc.h: Regenerate.
1208         * mep-desc.h: Regenerate.
1209         * mep-opc.h: Regenerate.
1210         * mt-desc.h: Regenerate.
1211         * mt-opc.h: Regenerate.
1212         * or1k-desc.h: Regenerate.
1213         * or1k-opc.h: Regenerate.
1214         * xc16x-desc.h: Regenerate.
1215         * xc16x-opc.h: Regenerate.
1216         * xstormy16-desc.h: Regenerate.
1217         * xstormy16-opc.h: Regenerate.
1218
1219 2017-01-02  Alan Modra  <amodra@gmail.com>
1220
1221         Update year range in copyright notice of all files.
1222
1223 For older changes see ChangeLog-2016
1224 \f
1225 Copyright (C) 2017 Free Software Foundation, Inc.
1226
1227 Copying and distribution of this file, with or without modification,
1228 are permitted in any medium without royalty provided the copyright
1229 notice and this notice are preserved.
1230
1231 Local Variables:
1232 mode: change-log
1233 left-margin: 8
1234 fill-column: 74
1235 version-control: never
1236 End: