* m68k-dis.c: Use ISC C90.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2005-06-23 Ben Elliston <bje@gnu.org>
2
3 * m68k-dis.c: Use ISC C90.
4 * m68k-opc.c: Formatting fixes.
5
6 2005-06-16 David Ung <davidu@mips.com>
7
8 * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
9 instructions to the table; seb/seh/sew/zeb/zeh/zew.
10
11 2005-06-15 Dave Brolley <brolley@redhat.com>
12
13 Contribute Morpho ms1 on behalf of Red Hat
14 * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
15 ms1-opc.h: New files, Morpho ms1 target.
16
17 2004-05-14 Stan Cox <scox@redhat.com>
18
19 * disassemble.c (ARCH_ms1): Define.
20 (disassembler): Handle bfd_arch_ms1
21
22 2004-05-13 Michael Snyder <msnyder@redhat.com>
23
24 * Makefile.am, Makefile.in: Add ms1 target.
25 * configure.in: Ditto.
26
27 2005-06-08 Zack Weinberg <zack@codesourcery.com>
28
29 * arm-opc.h: Delete; fold contents into ...
30 * arm-dis.c: ... here. Move includes of internal COFF headers
31 next to includes of internal ELF headers.
32 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
33 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
34 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
35 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
36 (iwmmxt_wwnames, iwmmxt_wwssnames):
37 Make const.
38 (regnames): Remove iWMMXt coprocessor register sets.
39 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
40 (get_arm_regnames): Adjust fourth argument to match above changes.
41 (set_iwmmxt_regnames): Delete.
42 (print_insn_arm): Constify 'c'. Use ISO syntax for function
43 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
44 and iwmmxt_cregnames, not set_iwmmxt_regnames.
45 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
46 ISO syntax for function pointer calls.
47
48 2005-06-07 Zack Weinberg <zack@codesourcery.com>
49
50 * arm-dis.c: Split up the comments describing the format codes, so
51 that the ARM and 16-bit Thumb opcode tables each have comments
52 preceding them that describe all the codes, and only the codes,
53 valid in those tables. (32-bit Thumb table is already like this.)
54 Reorder the lists in all three comments to match the order in
55 which the codes are implemented.
56 Remove all forward declarations of static functions. Convert all
57 function definitions to ISO C format.
58 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
59 Return nothing.
60 (print_insn_thumb16): Remove unused case 'I'.
61 (print_insn): Update for changed calling convention of subroutines.
62
63 2005-05-25 Jan Beulich <jbeulich@novell.com>
64
65 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
66 hex (but retain it being displayed as signed). Remove redundant
67 checks. Add handling of displacements for 16-bit addressing in Intel
68 mode.
69
70 2005-05-25 Jan Beulich <jbeulich@novell.com>
71
72 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
73 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
74 masking of 'rm' in 16-bit memory address handling.
75
76 2005-05-19 Anton Blanchard <anton@samba.org>
77
78 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
79 (print_ppc_disassembler_options): Document it.
80 * ppc-opc.c (SVC_LEV): Define.
81 (LEV): Allow optional operand.
82 (POWER5): Define.
83 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
84 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
85
86 2005-05-19 Kelley Cook <kcook@gcc.gnu.org>
87
88 * Makefile.in: Regenerate.
89
90 2005-05-17 Zack Weinberg <zack@codesourcery.com>
91
92 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
93 instructions. Adjust disassembly of some opcodes to match
94 unified syntax.
95 (thumb32_opcodes): New table.
96 (print_insn_thumb): Rename print_insn_thumb16; don't handle
97 two-halfword branches here.
98 (print_insn_thumb32): New function.
99 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
100 and print_insn_thumb32. Be consistent about order of
101 halfwords when printing 32-bit instructions.
102
103 2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
104
105 PR 843
106 * i386-dis.c (branch_v_mode): New.
107 (indirEv): Use branch_v_mode instead of v_mode.
108 (OP_E): Handle branch_v_mode.
109
110 2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
111
112 * d10v-dis.c (dis_2_short): Support 64bit host.
113
114 2005-05-07 Nick Clifton <nickc@redhat.com>
115
116 * po/nl.po: Updated translation.
117
118 2005-05-07 Nick Clifton <nickc@redhat.com>
119
120 * Update the address and phone number of the FSF organization in
121 the GPL notices in the following files:
122 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
123 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
124 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
125 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
126 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
127 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
128 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
129 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
130 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
131 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
132 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
133 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
134 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
135 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
136 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
137 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
138 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
139 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
140 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
141 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
142 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
143 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
144 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
145 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
146 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
147 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
148 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
149 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
150 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
151 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
152 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
153 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
154 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
155
156 2005-05-05 James E Wilson <wilson@specifixinc.com>
157
158 * ia64-opc.c: Include sysdep.h before libiberty.h.
159
160 2005-05-05 Nick Clifton <nickc@redhat.com>
161
162 * configure.in (ALL_LINGUAS): Add vi.
163 * configure: Regenerate.
164 * po/vi.po: New.
165
166 2005-04-26 Jerome Guitton <guitton@gnat.com>
167
168 * configure.in: Fix the check for basename declaration.
169 * configure: Regenerate.
170
171 2005-04-19 Alan Modra <amodra@bigpond.net.au>
172
173 * ppc-opc.c (RTO): Define.
174 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
175 entries to suit PPC440.
176
177 2005-04-18 Mark Kettenis <kettenis@gnu.org>
178
179 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
180 Add xcrypt-ctr.
181
182 2005-04-14 Nick Clifton <nickc@redhat.com>
183
184 * po/fi.po: New translation: Finnish.
185 * configure.in (ALL_LINGUAS): Add fi.
186 * configure: Regenerate.
187
188 2005-04-14 Alan Modra <amodra@bigpond.net.au>
189
190 * Makefile.am (NO_WERROR): Define.
191 * configure.in: Invoke AM_BINUTILS_WARNINGS.
192 * Makefile.in: Regenerate.
193 * aclocal.m4: Regenerate.
194 * configure: Regenerate.
195
196 2005-04-04 Nick Clifton <nickc@redhat.com>
197
198 * fr30-asm.c: Regenerate.
199 * frv-asm.c: Regenerate.
200 * iq2000-asm.c: Regenerate.
201 * m32r-asm.c: Regenerate.
202 * openrisc-asm.c: Regenerate.
203
204 2005-04-01 Jan Beulich <jbeulich@novell.com>
205
206 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
207 visible operands in Intel mode. The first operand of monitor is
208 %rax in 64-bit mode.
209
210 2005-04-01 Jan Beulich <jbeulich@novell.com>
211
212 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
213 easier future additions.
214
215 2005-03-31 Jerome Guitton <guitton@gnat.com>
216
217 * configure.in: Check for basename.
218 * configure: Regenerate.
219 * config.in: Ditto.
220
221 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
222
223 * i386-dis.c (SEG_Fixup): New.
224 (Sv): New.
225 (dis386): Use "Sv" for 0x8c and 0x8e.
226
227 2005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
228 Nick Clifton <nickc@redhat.com>
229
230 * vax-dis.c: (entry_addr): New varible: An array of user supplied
231 function entry mask addresses.
232 (entry_addr_occupied_slots): New variable: The number of occupied
233 elements in entry_addr.
234 (entry_addr_total_slots): New variable: The total number of
235 elements in entry_addr.
236 (parse_disassembler_options): New function. Fills in the entry_addr
237 array.
238 (free_entry_array): New function. Release the memory used by the
239 entry addr array. Suppressed because there is no way to call it.
240 (is_function_entry): Check if a given address is a function's
241 start address by looking at supplied entry mask addresses and
242 symbol information, if available.
243 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
244
245 2005-03-23 H.J. Lu <hongjiu.lu@intel.com>
246
247 * cris-dis.c (print_with_operands): Use ~31L for long instead
248 of ~31.
249
250 2005-03-20 H.J. Lu <hongjiu.lu@intel.com>
251
252 * mmix-opc.c (O): Revert the last change.
253 (Z): Likewise.
254
255 2005-03-19 H.J. Lu <hongjiu.lu@intel.com>
256
257 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
258 (Z): Likewise.
259
260 2005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
261
262 * mmix-opc.c (O, Z): Force expression as unsigned long.
263
264 2005-03-18 Nick Clifton <nickc@redhat.com>
265
266 * ip2k-asm.c: Regenerate.
267 * op/opcodes.pot: Regenerate.
268
269 2005-03-16 Nick Clifton <nickc@redhat.com>
270 Ben Elliston <bje@au.ibm.com>
271
272 * configure.in (werror): New switch: Add -Werror to the
273 compiler command line. Enabled by default. Disable via
274 --disable-werror.
275 * configure: Regenerate.
276
277 2005-03-16 Alan Modra <amodra@bigpond.net.au>
278
279 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
280 BOOKE.
281
282 2005-03-15 Alan Modra <amodra@bigpond.net.au>
283
284 * po/es.po: Commit new Spanish translation.
285
286 * po/fr.po: Commit new French translation.
287
288 2005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
289
290 * vax-dis.c: Fix spelling error
291 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
292 of just "Entry mask: < r1 ... >"
293
294 2005-03-12 Zack Weinberg <zack@codesourcery.com>
295
296 * arm-dis.c (arm_opcodes): Document %E and %V.
297 Add entries for v6T2 ARM instructions:
298 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
299 (print_insn_arm): Add support for %E and %V.
300 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
301
302 2005-03-10 Jeff Baker <jbaker@qnx.com>
303 Alan Modra <amodra@bigpond.net.au>
304
305 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
306 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
307 (SPRG_MASK): Delete.
308 (XSPRG_MASK): Mask off extra bits now part of sprg field.
309 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
310 mfsprg4..7 after msprg and consolidate.
311
312 2005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
313
314 * vax-dis.c (entry_mask_bit): New array.
315 (print_insn_vax): Decode function entry mask.
316
317 2005-03-07 Aldy Hernandez <aldyh@redhat.com>
318
319 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
320
321 2005-03-05 Alan Modra <amodra@bigpond.net.au>
322
323 * po/opcodes.pot: Regenerate.
324
325 2005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
326
327 * arc-dis.c (a4_decoding_class): New enum.
328 (dsmOneArcInst): Use the enum values for the decoding class.
329 Remove redundant case in the switch for decodingClass value 11.
330
331 2005-03-02 Jan Beulich <jbeulich@novell.com>
332
333 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
334 accesses.
335 (OP_C): Consider lock prefix in non-64-bit modes.
336
337 2005-02-24 Alan Modra <amodra@bigpond.net.au>
338
339 * cris-dis.c (format_hex): Remove ineffective warning fix.
340 * crx-dis.c (make_instruction): Warning fix.
341 * frv-asm.c: Regenerate.
342
343 2005-02-23 Nick Clifton <nickc@redhat.com>
344
345 * cgen-dis.in: Use bfd_byte for buffers that are passed to
346 read_memory.
347
348 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
349
350 * crx-dis.c (make_instruction): Move argument structure into inner
351 scope and ensure that all of its fields are initialised before
352 they are used.
353
354 * fr30-asm.c: Regenerate.
355 * fr30-dis.c: Regenerate.
356 * frv-asm.c: Regenerate.
357 * frv-dis.c: Regenerate.
358 * ip2k-asm.c: Regenerate.
359 * ip2k-dis.c: Regenerate.
360 * iq2000-asm.c: Regenerate.
361 * iq2000-dis.c: Regenerate.
362 * m32r-asm.c: Regenerate.
363 * m32r-dis.c: Regenerate.
364 * openrisc-asm.c: Regenerate.
365 * openrisc-dis.c: Regenerate.
366 * xstormy16-asm.c: Regenerate.
367 * xstormy16-dis.c: Regenerate.
368
369 2005-02-22 Alan Modra <amodra@bigpond.net.au>
370
371 * arc-ext.c: Warning fixes.
372 * arc-ext.h: Likewise.
373 * cgen-opc.c: Likewise.
374 * ia64-gen.c: Likewise.
375 * maxq-dis.c: Likewise.
376 * ns32k-dis.c: Likewise.
377 * w65-dis.c: Likewise.
378 * ia64-asmtab.c: Regenerate.
379
380 2005-02-22 Alan Modra <amodra@bigpond.net.au>
381
382 * fr30-desc.c: Regenerate.
383 * fr30-desc.h: Regenerate.
384 * fr30-opc.c: Regenerate.
385 * fr30-opc.h: Regenerate.
386 * frv-desc.c: Regenerate.
387 * frv-desc.h: Regenerate.
388 * frv-opc.c: Regenerate.
389 * frv-opc.h: Regenerate.
390 * ip2k-desc.c: Regenerate.
391 * ip2k-desc.h: Regenerate.
392 * ip2k-opc.c: Regenerate.
393 * ip2k-opc.h: Regenerate.
394 * iq2000-desc.c: Regenerate.
395 * iq2000-desc.h: Regenerate.
396 * iq2000-opc.c: Regenerate.
397 * iq2000-opc.h: Regenerate.
398 * m32r-desc.c: Regenerate.
399 * m32r-desc.h: Regenerate.
400 * m32r-opc.c: Regenerate.
401 * m32r-opc.h: Regenerate.
402 * m32r-opinst.c: Regenerate.
403 * openrisc-desc.c: Regenerate.
404 * openrisc-desc.h: Regenerate.
405 * openrisc-opc.c: Regenerate.
406 * openrisc-opc.h: Regenerate.
407 * xstormy16-desc.c: Regenerate.
408 * xstormy16-desc.h: Regenerate.
409 * xstormy16-opc.c: Regenerate.
410 * xstormy16-opc.h: Regenerate.
411
412 2005-02-21 Alan Modra <amodra@bigpond.net.au>
413
414 * Makefile.am: Run "make dep-am"
415 * Makefile.in: Regenerate.
416
417 2005-02-15 Nick Clifton <nickc@redhat.com>
418
419 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
420 compile time warnings.
421 (print_keyword): Likewise.
422 (default_print_insn): Likewise.
423
424 * fr30-desc.c: Regenerated.
425 * fr30-desc.h: Regenerated.
426 * fr30-dis.c: Regenerated.
427 * fr30-opc.c: Regenerated.
428 * fr30-opc.h: Regenerated.
429 * frv-desc.c: Regenerated.
430 * frv-dis.c: Regenerated.
431 * frv-opc.c: Regenerated.
432 * ip2k-asm.c: Regenerated.
433 * ip2k-desc.c: Regenerated.
434 * ip2k-desc.h: Regenerated.
435 * ip2k-dis.c: Regenerated.
436 * ip2k-opc.c: Regenerated.
437 * ip2k-opc.h: Regenerated.
438 * iq2000-desc.c: Regenerated.
439 * iq2000-dis.c: Regenerated.
440 * iq2000-opc.c: Regenerated.
441 * m32r-asm.c: Regenerated.
442 * m32r-desc.c: Regenerated.
443 * m32r-desc.h: Regenerated.
444 * m32r-dis.c: Regenerated.
445 * m32r-opc.c: Regenerated.
446 * m32r-opc.h: Regenerated.
447 * m32r-opinst.c: Regenerated.
448 * openrisc-desc.c: Regenerated.
449 * openrisc-desc.h: Regenerated.
450 * openrisc-dis.c: Regenerated.
451 * openrisc-opc.c: Regenerated.
452 * openrisc-opc.h: Regenerated.
453 * xstormy16-desc.c: Regenerated.
454 * xstormy16-desc.h: Regenerated.
455 * xstormy16-dis.c: Regenerated.
456 * xstormy16-opc.c: Regenerated.
457 * xstormy16-opc.h: Regenerated.
458
459 2005-02-14 H.J. Lu <hongjiu.lu@intel.com>
460
461 * dis-buf.c (perror_memory): Use sprintf_vma to print out
462 address.
463
464 2005-02-11 Nick Clifton <nickc@redhat.com>
465
466 * iq2000-asm.c: Regenerate.
467
468 * frv-dis.c: Regenerate.
469
470 2005-02-07 Jim Blandy <jimb@redhat.com>
471
472 * Makefile.am (CGEN): Load guile.scm before calling the main
473 application script.
474 * Makefile.in: Regenerated.
475 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
476 Simply pass the cgen-opc.scm path to ${cgen} as its first
477 argument; ${cgen} itself now contains the '-s', or whatever is
478 appropriate for the Scheme being used.
479
480 2005-01-31 Andrew Cagney <cagney@gnu.org>
481
482 * configure: Regenerate to track ../gettext.m4.
483
484 2005-01-31 Jan Beulich <jbeulich@novell.com>
485
486 * ia64-gen.c (NELEMS): Define.
487 (shrink): Generate alias with missing second predicate register when
488 opcode has two outputs and these are both predicates.
489 * ia64-opc-i.c (FULL17): Define.
490 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
491 here to generate output template.
492 (TBITCM, TNATCM): Undefine after use.
493 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
494 first input. Add ld16 aliases without ar.csd as second output. Add
495 st16 aliases without ar.csd as second input. Add cmpxchg aliases
496 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
497 ar.ccv as third/fourth inputs. Consolidate through...
498 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
499 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
500 * ia64-asmtab.c: Regenerate.
501
502 2005-01-27 Andrew Cagney <cagney@gnu.org>
503
504 * configure: Regenerate to track ../gettext.m4 change.
505
506 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
507
508 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
509 * frv-asm.c: Rebuilt.
510 * frv-desc.c: Rebuilt.
511 * frv-desc.h: Rebuilt.
512 * frv-dis.c: Rebuilt.
513 * frv-ibld.c: Rebuilt.
514 * frv-opc.c: Rebuilt.
515 * frv-opc.h: Rebuilt.
516
517 2005-01-24 Andrew Cagney <cagney@gnu.org>
518
519 * configure: Regenerate, ../gettext.m4 was updated.
520
521 2005-01-21 Fred Fish <fnf@specifixinc.com>
522
523 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
524 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
525 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
526 * mips-dis.c: Ditto.
527
528 2005-01-20 Alan Modra <amodra@bigpond.net.au>
529
530 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
531
532 2005-01-19 Fred Fish <fnf@specifixinc.com>
533
534 * mips-dis.c (no_aliases): New disassembly option flag.
535 (set_default_mips_dis_options): Init no_aliases to zero.
536 (parse_mips_dis_option): Handle no-aliases option.
537 (print_insn_mips): Ignore table entries that are aliases
538 if no_aliases is set.
539 (print_insn_mips16): Ditto.
540 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
541 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
542 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
543 * mips16-opc.c (mips16_opcodes): Ditto.
544
545 2005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
546
547 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
548 (inheritance diagram): Add missing edge.
549 (arch_sh1_up): Rename arch_sh_up to match external name to make life
550 easier for the testsuite.
551 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
552 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
553 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
554 arch_sh2a_or_sh4_up child.
555 (sh_table): Do renaming as above.
556 Correct comment for ldc.l for gas testsuite to read.
557 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
558 Correct comments for movy.w and movy.l for gas testsuite to read.
559 Correct comments for fmov.d and fmov.s for gas testsuite to read.
560
561 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
562
563 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
564
565 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
566
567 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
568
569 2005-01-10 Andreas Schwab <schwab@suse.de>
570
571 * disassemble.c (disassemble_init_for_target) <case
572 bfd_arch_ia64>: Set skip_zeroes to 16.
573 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
574
575 2004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
576
577 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
578
579 2004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
580
581 * avr-dis.c: Prettyprint. Added printing of symbol names in all
582 memory references. Convert avr_operand() to C90 formatting.
583
584 2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
585
586 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
587
588 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
589
590 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
591 (no_op_insn): Initialize array with instructions that have no
592 operands.
593 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
594
595 2004-11-29 Richard Earnshaw <rearnsha@arm.com>
596
597 * arm-dis.c: Correct top-level comment.
598
599 2004-11-27 Richard Earnshaw <rearnsha@arm.com>
600
601 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
602 architecuture defining the insn.
603 (arm_opcodes, thumb_opcodes): Delete. Move to ...
604 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
605 field.
606 Also include opcode/arm.h.
607 * Makefile.am (arm-dis.lo): Update dependency list.
608 * Makefile.in: Regenerate.
609
610 2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
611
612 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
613 reflect the change to the short immediate syntax.
614
615 2004-11-19 Alan Modra <amodra@bigpond.net.au>
616
617 * or32-opc.c (debug): Warning fix.
618 * po/POTFILES.in: Regenerate.
619
620 * maxq-dis.c: Formatting.
621 (print_insn): Warning fix.
622
623 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
624
625 * arm-dis.c (WORD_ADDRESS): Define.
626 (print_insn): Use it. Correct big-endian end-of-section handling.
627
628 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
629 Vineet Sharma <vineets@noida.hcltech.com>
630
631 * maxq-dis.c: New file.
632 * disassemble.c (ARCH_maxq): Define.
633 (disassembler): Add 'print_insn_maxq_little' for handling maxq
634 instructions..
635 * configure.in: Add case for bfd_maxq_arch.
636 * configure: Regenerate.
637 * Makefile.am: Add support for maxq-dis.c
638 * Makefile.in: Regenerate.
639 * aclocal.m4: Regenerate.
640
641 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
642
643 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
644 mode.
645 * crx-dis.c: Likewise.
646
647 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
648
649 Generally, handle CRISv32.
650 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
651 (struct cris_disasm_data): New type.
652 (format_reg, format_hex, cris_constraint, print_flags)
653 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
654 callers changed.
655 (format_sup_reg, print_insn_crisv32_with_register_prefix)
656 (print_insn_crisv32_without_register_prefix)
657 (print_insn_crisv10_v32_with_register_prefix)
658 (print_insn_crisv10_v32_without_register_prefix)
659 (cris_parse_disassembler_options): New functions.
660 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
661 parameter. All callers changed.
662 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
663 failure.
664 (cris_constraint) <case 'Y', 'U'>: New cases.
665 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
666 for constraint 'n'.
667 (print_with_operands) <case 'Y'>: New case.
668 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
669 <case 'N', 'Y', 'Q'>: New cases.
670 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
671 (print_insn_cris_with_register_prefix)
672 (print_insn_cris_without_register_prefix): Call
673 cris_parse_disassembler_options.
674 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
675 for CRISv32 and the size of immediate operands. New v32-only
676 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
677 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
678 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
679 Change brp to be v3..v10.
680 (cris_support_regs): New vector.
681 (cris_opcodes): Update head comment. New format characters '[',
682 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
683 Add new opcodes for v32 and adjust existing opcodes to accommodate
684 differences to earlier variants.
685 (cris_cond15s): New vector.
686
687 2004-11-04 Jan Beulich <jbeulich@novell.com>
688
689 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
690 (indirEb): Remove.
691 (Mp): Use f_mode rather than none at all.
692 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
693 replaces what previously was x_mode; x_mode now means 128-bit SSE
694 operands.
695 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
696 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
697 pinsrw's second operand is Edqw.
698 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
699 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
700 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
701 mode when an operand size override is present or always suffixing.
702 More instructions will need to be added to this group.
703 (putop): Handle new macro chars 'C' (short/long suffix selector),
704 'I' (Intel mode override for following macro char), and 'J' (for
705 adding the 'l' prefix to far branches in AT&T mode). When an
706 alternative was specified in the template, honor macro character when
707 specified for Intel mode.
708 (OP_E): Handle new *_mode values. Correct pointer specifications for
709 memory operands. Consolidate output of index register.
710 (OP_G): Handle new *_mode values.
711 (OP_I): Handle const_1_mode.
712 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
713 respective opcode prefix bits have been consumed.
714 (OP_EM, OP_EX): Provide some default handling for generating pointer
715 specifications.
716
717 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
718
719 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
720 COP_INST macro.
721
722 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
723
724 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
725 (getregliststring): Support HI/LO and user registers.
726 * crx-opc.c (crx_instruction): Update data structure according to the
727 rearrangement done in CRX opcode header file.
728 (crx_regtab): Likewise.
729 (crx_optab): Likewise.
730 (crx_instruction): Reorder load/stor instructions, remove unsupported
731 formats.
732 support new Co-Processor instruction 'cpi'.
733
734 2004-10-27 Nick Clifton <nickc@redhat.com>
735
736 * opcodes/iq2000-asm.c: Regenerate.
737 * opcodes/iq2000-desc.c: Regenerate.
738 * opcodes/iq2000-desc.h: Regenerate.
739 * opcodes/iq2000-dis.c: Regenerate.
740 * opcodes/iq2000-ibld.c: Regenerate.
741 * opcodes/iq2000-opc.c: Regenerate.
742 * opcodes/iq2000-opc.h: Regenerate.
743
744 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
745
746 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
747 us4, us5 (respectively).
748 Remove unsupported 'popa' instruction.
749 Reverse operands order in store co-processor instructions.
750
751 2004-10-15 Alan Modra <amodra@bigpond.net.au>
752
753 * Makefile.am: Run "make dep-am"
754 * Makefile.in: Regenerate.
755
756 2004-10-12 Bob Wilson <bob.wilson@acm.org>
757
758 * xtensa-dis.c: Use ISO C90 formatting.
759
760 2004-10-09 Alan Modra <amodra@bigpond.net.au>
761
762 * ppc-opc.c: Revert 2004-09-09 change.
763
764 2004-10-07 Bob Wilson <bob.wilson@acm.org>
765
766 * xtensa-dis.c (state_names): Delete.
767 (fetch_data): Use xtensa_isa_maxlength.
768 (print_xtensa_operand): Replace operand parameter with opcode/operand
769 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
770 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
771 instruction bundles. Use xmalloc instead of malloc.
772
773 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
774
775 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
776 initializers.
777
778 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
779
780 * crx-opc.c (crx_instruction): Support Co-processor insns.
781 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
782 (getregliststring): Change function to use the above enum.
783 (print_arg): Handle CO-Processor insns.
784 (crx_cinvs): Add 'b' option to invalidate the branch-target
785 cache.
786
787 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
788
789 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
790 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
791 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
792 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
793 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
794
795 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
796
797 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
798 rather than add it.
799
800 2004-09-30 Paul Brook <paul@codesourcery.com>
801
802 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
803 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
804
805 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
806
807 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
808 (CONFIG_STATUS_DEPENDENCIES): New.
809 (Makefile): Removed.
810 (config.status): Likewise.
811 * Makefile.in: Regenerated.
812
813 2004-09-17 Alan Modra <amodra@bigpond.net.au>
814
815 * Makefile.am: Run "make dep-am".
816 * Makefile.in: Regenerate.
817 * aclocal.m4: Regenerate.
818 * configure: Regenerate.
819 * po/POTFILES.in: Regenerate.
820 * po/opcodes.pot: Regenerate.
821
822 2004-09-11 Andreas Schwab <schwab@suse.de>
823
824 * configure: Rebuild.
825
826 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
827
828 * ppc-opc.c (L): Make this field not optional.
829
830 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
831
832 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
833 Fix parameter to 'm[t|f]csr' insns.
834
835 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
836
837 * configure.in: Autoupdate to autoconf 2.59.
838 * aclocal.m4: Rebuild with aclocal 1.4p6.
839 * configure: Rebuild with autoconf 2.59.
840 * Makefile.in: Rebuild with automake 1.4p6 (picking up
841 bfd changes for autoconf 2.59 on the way).
842 * config.in: Rebuild with autoheader 2.59.
843
844 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
845
846 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
847
848 2004-07-30 Michal Ludvig <mludvig@suse.cz>
849
850 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
851 (GRPPADLCK2): New define.
852 (twobyte_has_modrm): True for 0xA6.
853 (grps): GRPPADLCK2 for opcode 0xA6.
854
855 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
856
857 Introduce SH2a support.
858 * sh-opc.h (arch_sh2a_base): Renumber.
859 (arch_sh2a_nofpu_base): Remove.
860 (arch_sh_base_mask): Adjust.
861 (arch_opann_mask): New.
862 (arch_sh2a, arch_sh2a_nofpu): Adjust.
863 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
864 (sh_table): Adjust whitespace.
865 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
866 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
867 instruction list throughout.
868 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
869 of arch_sh2a in instruction list throughout.
870 (arch_sh2e_up): Accomodate above changes.
871 (arch_sh2_up): Ditto.
872 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
873 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
874 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
875 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
876 * sh-opc.h (arch_sh2a_nofpu): New.
877 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
878 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
879 instruction.
880 2004-01-20 DJ Delorie <dj@redhat.com>
881 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
882 2003-12-29 DJ Delorie <dj@redhat.com>
883 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
884 sh_opcode_info, sh_table): Add sh2a support.
885 (arch_op32): New, to tag 32-bit opcodes.
886 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
887 2003-12-02 Michael Snyder <msnyder@redhat.com>
888 * sh-opc.h (arch_sh2a): Add.
889 * sh-dis.c (arch_sh2a): Handle.
890 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
891
892 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
893
894 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
895
896 2004-07-22 Nick Clifton <nickc@redhat.com>
897
898 PR/280
899 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
900 insns - this is done by objdump itself.
901 * h8500-dis.c (print_insn_h8500): Likewise.
902
903 2004-07-21 Jan Beulich <jbeulich@novell.com>
904
905 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
906 regardless of address size prefix in effect.
907 (ptr_reg): Size or address registers does not depend on rex64, but
908 on the presence of an address size override.
909 (OP_MMX): Use rex.x only for xmm registers.
910 (OP_EM): Use rex.z only for xmm registers.
911
912 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
913
914 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
915 move/branch operations to the bottom so that VR5400 multimedia
916 instructions take precedence in disassembly.
917
918 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
919
920 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
921 ISA-specific "break" encoding.
922
923 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
924
925 * arm-opc.h: Fix typo in comment.
926
927 2004-07-11 Andreas Schwab <schwab@suse.de>
928
929 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
930
931 2004-07-09 Andreas Schwab <schwab@suse.de>
932
933 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
934
935 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
936
937 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
938 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
939 (crx-dis.lo): New target.
940 (crx-opc.lo): Likewise.
941 * Makefile.in: Regenerate.
942 * configure.in: Handle bfd_crx_arch.
943 * configure: Regenerate.
944 * crx-dis.c: New file.
945 * crx-opc.c: New file.
946 * disassemble.c (ARCH_crx): Define.
947 (disassembler): Handle ARCH_crx.
948
949 2004-06-29 James E Wilson <wilson@specifixinc.com>
950
951 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
952 * ia64-asmtab.c: Regnerate.
953
954 2004-06-28 Alan Modra <amodra@bigpond.net.au>
955
956 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
957 (extract_fxm): Don't test dialect.
958 (XFXFXM_MASK): Include the power4 bit.
959 (XFXM): Add p4 param.
960 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
961
962 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
963
964 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
965 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
966
967 2004-06-26 Alan Modra <amodra@bigpond.net.au>
968
969 * ppc-opc.c (BH, XLBH_MASK): Define.
970 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
971
972 2004-06-24 Alan Modra <amodra@bigpond.net.au>
973
974 * i386-dis.c (x_mode): Comment.
975 (two_source_ops): File scope.
976 (float_mem): Correct fisttpll and fistpll.
977 (float_mem_mode): New table.
978 (dofloat): Use it.
979 (OP_E): Correct intel mode PTR output.
980 (ptr_reg): Use open_char and close_char.
981 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
982 operands. Set two_source_ops.
983
984 2004-06-15 Alan Modra <amodra@bigpond.net.au>
985
986 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
987 instead of _raw_size.
988
989 2004-06-08 Jakub Jelinek <jakub@redhat.com>
990
991 * ia64-gen.c (in_iclass): Handle more postinc st
992 and ld variants.
993 * ia64-asmtab.c: Rebuilt.
994
995 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
996
997 * s390-opc.txt: Correct architecture mask for some opcodes.
998 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
999 in the esa mode as well.
1000
1001 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
1002
1003 * sh-dis.c (target_arch): Make unsigned.
1004 (print_insn_sh): Replace (most of) switch with a call to
1005 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
1006 * sh-opc.h: Redefine architecture flags values.
1007 Add sh3-nommu architecture.
1008 Reorganise <arch>_up macros so they make more visual sense.
1009 (SH_MERGE_ARCH_SET): Define new macro.
1010 (SH_VALID_BASE_ARCH_SET): Likewise.
1011 (SH_VALID_MMU_ARCH_SET): Likewise.
1012 (SH_VALID_CO_ARCH_SET): Likewise.
1013 (SH_VALID_ARCH_SET): Likewise.
1014 (SH_MERGE_ARCH_SET_VALID): Likewise.
1015 (SH_ARCH_SET_HAS_FPU): Likewise.
1016 (SH_ARCH_SET_HAS_DSP): Likewise.
1017 (SH_ARCH_UNKNOWN_ARCH): Likewise.
1018 (sh_get_arch_from_bfd_mach): Add prototype.
1019 (sh_get_arch_up_from_bfd_mach): Likewise.
1020 (sh_get_bfd_mach_from_arch_set): Likewise.
1021 (sh_merge_bfd_arc): Likewise.
1022
1023 2004-05-24 Peter Barada <peter@the-baradas.com>
1024
1025 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
1026 into new match_insn_m68k function. Loop over canidate
1027 matches and select first that completely matches.
1028 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1029 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
1030 to verify addressing for MAC/EMAC.
1031 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1032 reigster halves since 'fpu' and 'spl' look misleading.
1033 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1034 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1035 first, tighten up match masks.
1036 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1037 'size' from special case code in print_insn_m68k to
1038 determine decode size of insns.
1039
1040 2004-05-19 Alan Modra <amodra@bigpond.net.au>
1041
1042 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1043 well as when -mpower4.
1044
1045 2004-05-13 Nick Clifton <nickc@redhat.com>
1046
1047 * po/fr.po: Updated French translation.
1048
1049 2004-05-05 Peter Barada <peter@the-baradas.com>
1050
1051 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1052 variants in arch_mask. Only set m68881/68851 for 68k chips.
1053 * m68k-op.c: Switch from ColdFire chips to core variants.
1054
1055 2004-05-05 Alan Modra <amodra@bigpond.net.au>
1056
1057 PR 147.
1058 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1059
1060 2004-04-29 Ben Elliston <bje@au.ibm.com>
1061
1062 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1063 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
1064
1065 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1066
1067 * sh-dis.c (print_insn_sh): Print the value in constant pool
1068 as a symbol if it looks like a symbol.
1069
1070 2004-04-22 Peter Barada <peter@the-baradas.com>
1071
1072 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1073 appropriate ColdFire architectures.
1074 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1075 mask addressing.
1076 Add EMAC instructions, fix MAC instructions. Remove
1077 macmw/macml/msacmw/msacml instructions since mask addressing now
1078 supported.
1079
1080 2004-04-20 Jakub Jelinek <jakub@redhat.com>
1081
1082 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1083 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1084 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1085 macro. Adjust all users.
1086
1087 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
1088
1089 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1090 separately.
1091
1092 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1093
1094 * m32r-asm.c: Regenerate.
1095
1096 2004-03-29 Stan Shebs <shebs@apple.com>
1097
1098 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1099 used.
1100
1101 2004-03-19 Alan Modra <amodra@bigpond.net.au>
1102
1103 * aclocal.m4: Regenerate.
1104 * config.in: Regenerate.
1105 * configure: Regenerate.
1106 * po/POTFILES.in: Regenerate.
1107 * po/opcodes.pot: Regenerate.
1108
1109 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1110
1111 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1112 PPC_OPERANDS_GPR_0.
1113 * ppc-opc.c (RA0): Define.
1114 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1115 (RAOPT): Rename from RAO. Update all uses.
1116 (powerpc_opcodes): Use RA0 as appropriate.
1117
1118 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
1119
1120 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
1121
1122 2004-03-15 Alan Modra <amodra@bigpond.net.au>
1123
1124 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1125
1126 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1127
1128 * i386-dis.c (GRPPLOCK): Delete.
1129 (grps): Delete GRPPLOCK entry.
1130
1131 2004-03-12 Alan Modra <amodra@bigpond.net.au>
1132
1133 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1134 (M, Mp): Use OP_M.
1135 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1136 (GRPPADLCK): Define.
1137 (dis386): Use NOP_Fixup on "nop".
1138 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1139 (twobyte_has_modrm): Set for 0xa7.
1140 (padlock_table): Delete. Move to..
1141 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1142 and clflush.
1143 (print_insn): Revert PADLOCK_SPECIAL code.
1144 (OP_E): Delete sfence, lfence, mfence checks.
1145
1146 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1147
1148 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1149 (INVLPG_Fixup): New function.
1150 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1151
1152 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1153
1154 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1155 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1156 (padlock_table): New struct with PadLock instructions.
1157 (print_insn): Handle PADLOCK_SPECIAL.
1158
1159 2004-03-12 Alan Modra <amodra@bigpond.net.au>
1160
1161 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1162 (OP_E): Twiddle clflush to sfence here.
1163
1164 2004-03-08 Nick Clifton <nickc@redhat.com>
1165
1166 * po/de.po: Updated German translation.
1167
1168 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1169
1170 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1171 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1172 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1173 accordingly.
1174
1175 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
1176
1177 * frv-asm.c: Regenerate.
1178 * frv-desc.c: Regenerate.
1179 * frv-desc.h: Regenerate.
1180 * frv-dis.c: Regenerate.
1181 * frv-ibld.c: Regenerate.
1182 * frv-opc.c: Regenerate.
1183 * frv-opc.h: Regenerate.
1184
1185 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
1186
1187 * frv-desc.c, frv-opc.c: Regenerate.
1188
1189 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
1190
1191 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1192
1193 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1194
1195 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1196 Also correct mistake in the comment.
1197
1198 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1199
1200 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1201 ensure that double registers have even numbers.
1202 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1203 that reserved instruction 0xfffd does not decode the same
1204 as 0xfdfd (ftrv).
1205 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1206 REG_N refers to a double register.
1207 Add REG_N_B01 nibble type and use it instead of REG_NM
1208 in ftrv.
1209 Adjust the bit patterns in a few comments.
1210
1211 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
1212
1213 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
1214
1215 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
1216
1217 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1218
1219 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
1220
1221 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1222
1223 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
1224
1225 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1226 mtivor32, mtivor33, mtivor34.
1227
1228 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
1229
1230 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
1231
1232 2004-02-10 Petko Manolov <petkan@nucleusys.com>
1233
1234 * arm-opc.h Maverick accumulator register opcode fixes.
1235
1236 2004-02-13 Ben Elliston <bje@wasabisystems.com>
1237
1238 * m32r-dis.c: Regenerate.
1239
1240 2004-01-27 Michael Snyder <msnyder@redhat.com>
1241
1242 * sh-opc.h (sh_table): "fsrra", not "fssra".
1243
1244 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1245
1246 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1247 contraints.
1248
1249 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1250
1251 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1252
1253 2004-01-19 Alan Modra <amodra@bigpond.net.au>
1254
1255 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1256 1. Don't print scale factor on AT&T mode when index missing.
1257
1258 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
1259
1260 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1261 when loaded into XR registers.
1262
1263 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
1264
1265 * frv-desc.h: Regenerate.
1266 * frv-desc.c: Regenerate.
1267 * frv-opc.c: Regenerate.
1268
1269 2004-01-13 Michael Snyder <msnyder@redhat.com>
1270
1271 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1272
1273 2004-01-09 Paul Brook <paul@codesourcery.com>
1274
1275 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1276 specific opcodes.
1277
1278 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
1279
1280 * Makefile.am (libopcodes_la_DEPENDENCIES)
1281 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1282 comment about the problem.
1283 * Makefile.in: Regenerate.
1284
1285 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
1286
1287 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1288 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1289 cut&paste errors in shifting/truncating numerical operands.
1290 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1291 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1292 (parse_uslo16): Likewise.
1293 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1294 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1295 (parse_s12): Likewise.
1296 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1297 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1298 (parse_uslo16): Likewise.
1299 (parse_uhi16): Parse gothi and gotfuncdeschi.
1300 (parse_d12): Parse got12 and gotfuncdesc12.
1301 (parse_s12): Likewise.
1302
1303 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1304
1305 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1306 instruction which looks similar to an 'rla' instruction.
1307
1308 For older changes see ChangeLog-0203
1309 \f
1310 Local Variables:
1311 mode: change-log
1312 left-margin: 8
1313 fill-column: 74
1314 version-control: never
1315 End:
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