1 2018-09-13 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
5 * i386-tbl.h: Re-generate.
7 2018-09-13 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
11 * i386-tbl.h: Re-generate.
13 2018-09-13 Jan Beulich <jbeulich@suse.com>
15 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
17 * i386-tbl.h: Re-generate.
19 2018-09-13 Jan Beulich <jbeulich@suse.com>
21 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
23 * i386-tbl.h: Re-generate.
25 2018-09-13 Jan Beulich <jbeulich@suse.com>
27 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
29 * i386-tbl.h: Re-generate.
31 2018-09-13 Jan Beulich <jbeulich@suse.com>
33 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
35 * i386-tbl.h: Re-generate.
37 2018-09-13 Jan Beulich <jbeulich@suse.com>
39 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
40 * i386-tbl.h: Re-generate.
42 2018-09-13 Jan Beulich <jbeulich@suse.com>
44 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
45 * i386-tbl.h: Re-generate.
47 2018-09-13 Jan Beulich <jbeulich@suse.com>
49 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
51 * i386-tbl.h: Re-generate.
53 2018-09-13 Jan Beulich <jbeulich@suse.com>
55 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
57 * i386-tbl.h: Re-generate.
59 2018-09-13 Jan Beulich <jbeulich@suse.com>
61 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
62 * i386-tbl.h: Re-generate.
64 2018-09-13 Jan Beulich <jbeulich@suse.com>
66 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
67 * i386-tbl.h: Re-generate.
69 2018-09-13 Jan Beulich <jbeulich@suse.com>
71 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
72 * i386-tbl.h: Re-generate.
74 2018-09-13 Jan Beulich <jbeulich@suse.com>
76 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
78 * i386-tbl.h: Re-generate.
80 2018-09-13 Jan Beulich <jbeulich@suse.com>
82 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
84 * i386-tbl.h: Re-generate.
86 2018-09-13 Jan Beulich <jbeulich@suse.com>
88 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
90 * i386-tbl.h: Re-generate.
92 2018-09-13 Jan Beulich <jbeulich@suse.com>
94 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
95 * i386-tbl.h: Re-generate.
97 2018-09-13 Jan Beulich <jbeulich@suse.com>
99 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
100 * i386-tbl.h: Re-generate.
102 2018-09-13 Jan Beulich <jbeulich@suse.com>
104 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
105 * i386-tbl.h: Re-generate.
107 2018-09-13 Jan Beulich <jbeulich@suse.com>
109 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
110 (vpbroadcastw, rdpid): Drop NoRex64.
111 * i386-tbl.h: Re-generate.
113 2018-09-13 Jan Beulich <jbeulich@suse.com>
115 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
116 store templates, adding D.
117 * i386-tbl.h: Re-generate.
119 2018-09-13 Jan Beulich <jbeulich@suse.com>
121 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
122 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
123 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
124 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
125 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
126 Fold load and store templates where possible, adding D. Drop
127 IgnoreSize where it was pointlessly present. Drop redundant
129 * i386-tbl.h: Re-generate.
131 2018-09-13 Jan Beulich <jbeulich@suse.com>
133 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
134 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
135 (intel_operand_size): Handle v_bndmk_mode.
136 (OP_E_memory): Likewise. Produce (bad) when also riprel.
138 2018-09-08 John Darrington <john@darrington.wattle.id.au>
140 * disassemble.c (ARCH_s12z): Define if ARCH_all.
142 2018-08-31 Kito Cheng <kito@andestech.com>
144 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
145 compressed floating point instructions.
147 2018-08-30 Kito Cheng <kito@andestech.com>
149 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
150 riscv_opcode.xlen_requirement.
151 * riscv-opc.c (riscv_opcodes): Update for struct change.
153 2018-08-29 Martin Aberg <maberg@gaisler.com>
155 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
156 psr (PWRPSR) instruction.
158 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
160 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
162 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
164 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
166 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
168 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
169 loongson3a as an alias of gs464 for compatibility.
170 * mips-opc.c (mips_opcodes): Change Comments.
172 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
174 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
176 (print_mips_disassembler_options): Document -M loongson-ext.
177 * mips-opc.c (LEXT2): New macro.
178 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
180 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
182 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
184 (parse_mips_ase_option): Handle -M loongson-ext option.
185 (print_mips_disassembler_options): Document -M loongson-ext.
186 * mips-opc.c (IL3A): Delete.
187 * mips-opc.c (LEXT): New macro.
188 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
191 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
193 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
195 (parse_mips_ase_option): Handle -M loongson-cam option.
196 (print_mips_disassembler_options): Document -M loongson-cam.
197 * mips-opc.c (LCAM): New macro.
198 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
201 2018-08-21 Alan Modra <amodra@gmail.com>
203 * ppc-dis.c (operand_value_powerpc): Init "invalid".
204 (skip_optional_operands): Count optional operands, and update
205 ppc_optional_operand_value call.
206 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
207 (extract_vlensi): Likewise.
208 (extract_fxm): Return default value for missing optional operand.
209 (extract_ls, extract_raq, extract_tbr): Likewise.
210 (insert_sxl, extract_sxl): New functions.
211 (insert_esync, extract_esync): Remove Power9 handling and simplify.
212 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
213 flag and extra entry.
214 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
217 2018-08-20 Alan Modra <amodra@gmail.com>
219 * sh-opc.h (MASK): Simplify.
221 2018-08-18 John Darrington <john@darrington.wattle.id.au>
223 * s12z-dis.c (bm_decode): Deal with cases where the mode is
224 BM_RESERVED0 or BM_RESERVED1
225 (bm_rel_decode, bm_n_bytes): Ditto.
227 2018-08-18 John Darrington <john@darrington.wattle.id.au>
231 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
233 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
234 address with the addr32 prefix and without base nor index
237 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
239 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
240 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
241 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
242 (cpu_flags): Add CpuCMOV and CpuFXSR.
243 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
244 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
245 * i386-init.h: Regenerated.
246 * i386-tbl.h: Likewise.
248 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
250 * arc-regs.h: Update auxiliary registers.
252 2018-08-06 Jan Beulich <jbeulich@suse.com>
254 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
255 (RegIP, RegIZ): Define.
256 * i386-reg.tbl: Adjust comments.
257 (rip): Use Qword instead of BaseIndex. Use RegIP.
258 (eip): Use Dword instead of BaseIndex. Use RegIP.
259 (riz): Add Qword. Use RegIZ.
260 (eiz): Add Dword. Use RegIZ.
261 * i386-tbl.h: Re-generate.
263 2018-08-03 Jan Beulich <jbeulich@suse.com>
265 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
266 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
267 vpmovzxdq, vpmovzxwd): Remove NoRex64.
268 * i386-tbl.h: Re-generate.
270 2018-08-03 Jan Beulich <jbeulich@suse.com>
272 * i386-gen.c (operand_types): Remove Mem field.
273 * i386-opc.h (union i386_operand_type): Remove mem field.
274 * i386-init.h, i386-tbl.h: Re-generate.
276 2018-08-01 Alan Modra <amodra@gmail.com>
278 * po/POTFILES.in: Regenerate.
280 2018-07-31 Nick Clifton <nickc@redhat.com>
282 * po/sv.po: Updated Swedish translation.
284 2018-07-31 Jan Beulich <jbeulich@suse.com>
286 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
287 * i386-init.h, i386-tbl.h: Re-generate.
289 2018-07-31 Jan Beulich <jbeulich@suse.com>
291 * i386-opc.h (ZEROING_MASKING) Rename to ...
292 (DYNAMIC_MASKING): ... this. Adjust comment.
293 * i386-opc.tbl (MaskingMorZ): Define.
294 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
295 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
296 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
297 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
298 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
299 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
300 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
301 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
302 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
304 2018-07-31 Jan Beulich <jbeulich@suse.com>
306 * i386-opc.tbl: Use element rather than vector size for AVX512*
307 scatter/gather insns.
308 * i386-tbl.h: Re-generate.
310 2018-07-31 Jan Beulich <jbeulich@suse.com>
312 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
313 (cpu_flags): Drop CpuVREX.
314 * i386-opc.h (CpuVREX): Delete.
315 (union i386_cpu_flags): Remove cpuvrex.
316 * i386-init.h, i386-tbl.h: Re-generate.
318 2018-07-30 Jim Wilson <jimw@sifive.com>
320 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
322 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
324 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
326 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
327 * Makefile.in: Regenerated.
328 * configure.ac: Add C-SKY.
329 * configure: Regenerated.
330 * csky-dis.c: New file.
331 * csky-opc.h: New file.
332 * disassemble.c (ARCH_csky): Define.
333 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
334 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
336 2018-07-27 Alan Modra <amodra@gmail.com>
338 * ppc-opc.c (insert_sprbat): Correct function parameter and
340 (extract_sprbat): Likewise, variable too.
342 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
343 Alan Modra <amodra@gmail.com>
345 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
346 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
347 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
348 support disjointed BAT.
349 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
350 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
351 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
353 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
354 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
356 * i386-gen.c (adjust_broadcast_modifier): New function.
357 (process_i386_opcode_modifier): Add an argument for operands.
358 Adjust the Broadcast value based on operands.
359 (output_i386_opcode): Pass operand_types to
360 process_i386_opcode_modifier.
361 (process_i386_opcodes): Pass NULL as operands to
362 process_i386_opcode_modifier.
363 * i386-opc.h (BYTE_BROADCAST): New.
364 (WORD_BROADCAST): Likewise.
365 (DWORD_BROADCAST): Likewise.
366 (QWORD_BROADCAST): Likewise.
367 (i386_opcode_modifier): Expand broadcast to 3 bits.
368 * i386-tbl.h: Regenerated.
370 2018-07-24 Alan Modra <amodra@gmail.com>
373 * or1k-desc.h: Regenerate.
375 2018-07-24 Jan Beulich <jbeulich@suse.com>
377 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
378 vcvtusi2ss, and vcvtusi2sd.
379 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
380 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
381 * i386-tbl.h: Re-generate.
383 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
385 * arc-opc.c (extract_w6): Fix extending the sign.
387 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
389 * arc-tbl.h (vewt): Allow it for ARC EM family.
391 2018-07-23 Alan Modra <amodra@gmail.com>
394 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
395 opcode variants for mtspr/mfspr encodings.
397 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
398 Maciej W. Rozycki <macro@mips.com>
400 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
401 loongson3a descriptors.
402 (parse_mips_ase_option): Handle -M loongson-mmi option.
403 (print_mips_disassembler_options): Document -M loongson-mmi.
404 * mips-opc.c (LMMI): New macro.
405 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
408 2018-07-19 Jan Beulich <jbeulich@suse.com>
410 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
411 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
412 IgnoreSize and [XYZ]MMword where applicable.
413 * i386-tbl.h: Re-generate.
415 2018-07-19 Jan Beulich <jbeulich@suse.com>
417 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
418 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
419 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
420 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
421 * i386-tbl.h: Re-generate.
423 2018-07-19 Jan Beulich <jbeulich@suse.com>
425 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
426 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
427 VPCLMULQDQ templates into their respective AVX512VL counterparts
428 where possible, using Disp8ShiftVL and CheckRegSize instead of
429 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
430 * i386-tbl.h: Re-generate.
432 2018-07-19 Jan Beulich <jbeulich@suse.com>
434 * i386-opc.tbl: Fold AVX512DQ templates into their respective
435 AVX512VL counterparts where possible, using Disp8ShiftVL and
436 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
437 IgnoreSize) as appropriate.
438 * i386-tbl.h: Re-generate.
440 2018-07-19 Jan Beulich <jbeulich@suse.com>
442 * i386-opc.tbl: Fold AVX512BW templates into their respective
443 AVX512VL counterparts where possible, using Disp8ShiftVL and
444 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
445 IgnoreSize) as appropriate.
446 * i386-tbl.h: Re-generate.
448 2018-07-19 Jan Beulich <jbeulich@suse.com>
450 * i386-opc.tbl: Fold AVX512CD templates into their respective
451 AVX512VL counterparts where possible, using Disp8ShiftVL and
452 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
453 IgnoreSize) as appropriate.
454 * i386-tbl.h: Re-generate.
456 2018-07-19 Jan Beulich <jbeulich@suse.com>
458 * i386-opc.h (DISP8_SHIFT_VL): New.
459 * i386-opc.tbl (Disp8ShiftVL): Define.
460 (various): Fold AVX512VL templates into their respective
461 AVX512F counterparts where possible, using Disp8ShiftVL and
462 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
463 IgnoreSize) as appropriate.
464 * i386-tbl.h: Re-generate.
466 2018-07-19 Jan Beulich <jbeulich@suse.com>
468 * Makefile.am: Change dependencies and rule for
469 $(srcdir)/i386-init.h.
470 * Makefile.in: Re-generate.
471 * i386-gen.c (process_i386_opcodes): New local variable
472 "marker". Drop opening of input file. Recognize marker and line
474 * i386-opc.tbl (OPCODE_I386_H): Define.
475 (i386-opc.h): Include it.
478 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
481 * i386-opc.h (Byte): Update comments.
490 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
492 * i386-tbl.h: Regenerated.
494 2018-07-12 Sudakshina Das <sudi.das@arm.com>
496 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
497 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
498 * aarch64-asm-2.c: Regenerate.
499 * aarch64-dis-2.c: Regenerate.
500 * aarch64-opc-2.c: Regenerate.
502 2018-07-12 Tamar Christina <tamar.christina@arm.com>
505 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
506 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
507 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
508 sqdmulh, sqrdmulh): Use Em16.
510 2018-07-11 Sudakshina Das <sudi.das@arm.com>
512 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
513 csdb together with them.
514 (thumb32_opcodes): Likewise.
516 2018-07-11 Jan Beulich <jbeulich@suse.com>
518 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
519 requiring 32-bit registers as operands 2 and 3. Improve
521 (mwait, mwaitx): Fold templates. Improve comments.
522 OPERAND_TYPE_INOUTPORTREG.
523 * i386-tbl.h: Re-generate.
525 2018-07-11 Jan Beulich <jbeulich@suse.com>
527 * i386-gen.c (operand_type_init): Remove
528 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
529 OPERAND_TYPE_INOUTPORTREG.
530 * i386-init.h: Re-generate.
532 2018-07-11 Jan Beulich <jbeulich@suse.com>
534 * i386-opc.tbl (wrssd, wrussd): Add Dword.
535 (wrssq, wrussq): Add Qword.
536 * i386-tbl.h: Re-generate.
538 2018-07-11 Jan Beulich <jbeulich@suse.com>
540 * i386-opc.h: Rename OTMax to OTNum.
541 (OTNumOfUints): Adjust calculation.
542 (OTUnused): Directly alias to OTNum.
544 2018-07-09 Maciej W. Rozycki <macro@mips.com>
546 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
548 (lea_reg_xys): Likewise.
549 (print_insn_loop_primitive): Rename `reg' local variable to
552 2018-07-06 Tamar Christina <tamar.christina@arm.com>
555 * aarch64-tbl.h (ldarh): Fix disassembly mask.
557 2018-07-06 Tamar Christina <tamar.christina@arm.com>
560 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
561 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
563 2018-07-02 Maciej W. Rozycki <macro@mips.com>
566 * mips-dis.c (mips_option_arg_t): New enumeration.
567 (mips_options): New variable.
568 (disassembler_options_mips): New function.
569 (print_mips_disassembler_options): Reimplement in terms of
570 `disassembler_options_mips'.
571 * arm-dis.c (disassembler_options_arm): Adapt to using the
572 `disasm_options_and_args_t' structure.
573 * ppc-dis.c (disassembler_options_powerpc): Likewise.
574 * s390-dis.c (disassembler_options_s390): Likewise.
576 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
578 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
580 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
581 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
582 * testsuite/ld-arm/tls-longplt.d: Likewise.
584 2018-06-29 Tamar Christina <tamar.christina@arm.com>
587 * aarch64-asm-2.c: Regenerate.
588 * aarch64-dis-2.c: Likewise.
589 * aarch64-opc-2.c: Likewise.
590 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
591 * aarch64-opc.c (operand_general_constraint_met_p,
592 aarch64_print_operand): Likewise.
593 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
594 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
596 (AARCH64_OPERANDS): Add Em2.
598 2018-06-26 Nick Clifton <nickc@redhat.com>
600 * po/uk.po: Updated Ukranian translation.
601 * po/de.po: Updated German translation.
602 * po/pt_BR.po: Updated Brazilian Portuguese translation.
604 2018-06-26 Nick Clifton <nickc@redhat.com>
606 * nfp-dis.c: Fix spelling mistake.
608 2018-06-24 Nick Clifton <nickc@redhat.com>
610 * configure: Regenerate.
611 * po/opcodes.pot: Regenerate.
613 2018-06-24 Nick Clifton <nickc@redhat.com>
617 2018-06-19 Tamar Christina <tamar.christina@arm.com>
619 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
620 * aarch64-asm-2.c: Regenerate.
621 * aarch64-dis-2.c: Likewise.
623 2018-06-21 Maciej W. Rozycki <macro@mips.com>
625 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
626 `-M ginv' option description.
628 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
631 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
634 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
636 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
637 * configure.ac: Remove AC_PREREQ.
638 * Makefile.in: Re-generate.
639 * aclocal.m4: Re-generate.
640 * configure: Re-generate.
642 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
644 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
645 mips64r6 descriptors.
646 (parse_mips_ase_option): Handle -Mginv option.
647 (print_mips_disassembler_options): Document -Mginv.
648 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
650 (mips_opcodes): Define ginvi and ginvt.
652 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
653 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
655 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
656 * mips-opc.c (CRC, CRC64): New macros.
657 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
658 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
661 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
664 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
665 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
667 2018-06-06 Alan Modra <amodra@gmail.com>
669 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
670 setjmp. Move init for some other vars later too.
672 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
674 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
675 (dis_private): Add new fields for property section tracking.
676 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
677 (xtensa_instruction_fits): New functions.
678 (fetch_data): Bump minimal fetch size to 4.
679 (print_insn_xtensa): Make struct dis_private static.
680 Load and prepare property table on section change.
681 Don't disassemble literals. Don't disassemble instructions that
682 cross property table boundaries.
684 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
686 * configure: Regenerated.
688 2018-06-01 Jan Beulich <jbeulich@suse.com>
690 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
691 * i386-tbl.h: Re-generate.
693 2018-06-01 Jan Beulich <jbeulich@suse.com>
695 * i386-opc.tbl (sldt, str): Add NoRex64.
696 * i386-tbl.h: Re-generate.
698 2018-06-01 Jan Beulich <jbeulich@suse.com>
700 * i386-opc.tbl (invpcid): Add Oword.
701 * i386-tbl.h: Re-generate.
703 2018-06-01 Alan Modra <amodra@gmail.com>
705 * sysdep.h (_bfd_error_handler): Don't declare.
706 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
707 * rl78-decode.opc: Likewise.
708 * msp430-decode.c: Regenerate.
709 * rl78-decode.c: Regenerate.
711 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
713 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
714 * i386-init.h : Regenerated.
716 2018-05-25 Alan Modra <amodra@gmail.com>
718 * Makefile.in: Regenerate.
719 * po/POTFILES.in: Regenerate.
721 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
723 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
724 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
725 (insert_bab, extract_bab, insert_btab, extract_btab,
726 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
727 (BAT, BBA VBA RBS XB6S): Delete macros.
728 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
729 (BB, BD, RBX, XC6): Update for new macros.
730 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
731 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
732 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
733 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
735 2018-05-18 John Darrington <john@darrington.wattle.id.au>
737 * Makefile.am: Add support for s12z architecture.
738 * configure.ac: Likewise.
739 * disassemble.c: Likewise.
740 * disassemble.h: Likewise.
741 * Makefile.in: Regenerate.
742 * configure: Regenerate.
743 * s12z-dis.c: New file.
746 2018-05-18 Alan Modra <amodra@gmail.com>
748 * nfp-dis.c: Don't #include libbfd.h.
749 (init_nfp3200_priv): Use bfd_get_section_contents.
750 (nit_nfp6000_mecsr_sec): Likewise.
752 2018-05-17 Nick Clifton <nickc@redhat.com>
754 * po/zh_CN.po: Updated simplified Chinese translation.
756 2018-05-16 Tamar Christina <tamar.christina@arm.com>
759 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
760 * aarch64-dis-2.c: Regenerate.
762 2018-05-15 Tamar Christina <tamar.christina@arm.com>
765 * aarch64-asm.c (opintl.h): Include.
766 (aarch64_ins_sysreg): Enforce read/write constraints.
767 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
768 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
769 (F_REG_READ, F_REG_WRITE): New.
770 * aarch64-opc.c (aarch64_print_operand): Generate notes for
772 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
773 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
774 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
775 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
776 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
777 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
778 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
779 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
780 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
781 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
782 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
783 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
784 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
785 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
786 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
787 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
788 msr (F_SYS_WRITE), mrs (F_SYS_READ).
790 2018-05-15 Tamar Christina <tamar.christina@arm.com>
793 * aarch64-dis.c (no_notes: New.
794 (parse_aarch64_dis_option): Support notes.
795 (aarch64_decode_insn, print_operands): Likewise.
796 (print_aarch64_disassembler_options): Document notes.
797 * aarch64-opc.c (aarch64_print_operand): Support notes.
799 2018-05-15 Tamar Christina <tamar.christina@arm.com>
802 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
803 and take error struct.
804 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
805 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
806 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
807 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
808 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
809 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
810 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
811 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
812 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
813 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
814 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
815 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
816 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
817 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
818 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
819 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
820 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
821 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
822 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
823 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
824 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
825 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
826 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
827 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
828 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
829 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
830 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
831 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
832 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
833 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
834 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
835 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
836 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
837 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
838 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
839 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
840 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
841 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
842 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
843 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
844 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
845 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
846 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
847 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
848 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
849 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
850 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
851 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
852 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
853 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
854 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
855 (determine_disassembling_preference, aarch64_decode_insn,
856 print_insn_aarch64_word, print_insn_data): Take errors struct.
857 (print_insn_aarch64): Use errors.
858 * aarch64-asm-2.c: Regenerate.
859 * aarch64-dis-2.c: Regenerate.
860 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
861 boolean in aarch64_insert_operan.
862 (print_operand_extractor): Likewise.
863 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
865 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
867 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
869 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
871 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
873 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
875 * cr16-opc.c (cr16_instruction): Comment typo fix.
876 * hppa-dis.c (print_insn_hppa): Likewise.
878 2018-05-08 Jim Wilson <jimw@sifive.com>
880 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
881 (match_c_slli64, match_srxi_as_c_srxi): New.
882 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
883 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
884 <c.slli, c.srli, c.srai>: Use match_s_slli.
885 <c.slli64, c.srli64, c.srai64>: New.
887 2018-05-08 Alan Modra <amodra@gmail.com>
889 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
890 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
891 partition opcode space for index lookup.
893 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
895 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
896 <insn_length>: ...with this. Update usage.
897 Remove duplicate call to *info->memory_error_func.
899 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
900 H.J. Lu <hongjiu.lu@intel.com>
902 * i386-dis.c (Gva): New.
903 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
904 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
905 (prefix_table): New instructions (see prefix above).
906 (mod_table): New instructions (see prefix above).
907 (OP_G): Handle va_mode.
908 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
910 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
911 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
912 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
913 * i386-opc.tbl: Add movidir{i,64b}.
914 * i386-init.h: Regenerated.
915 * i386-tbl.h: Likewise.
917 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
919 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
921 * i386-opc.h (AddrPrefixOp0): Renamed to ...
922 (AddrPrefixOpReg): This.
923 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
924 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
926 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
928 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
929 (vle_num_opcodes): Likewise.
930 (spe2_num_opcodes): Likewise.
931 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
933 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
934 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
937 2018-05-01 Tamar Christina <tamar.christina@arm.com>
939 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
941 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
943 Makefile.am: Added nfp-dis.c.
944 configure.ac: Added bfd_nfp_arch.
945 disassemble.h: Added print_insn_nfp prototype.
946 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
947 nfp-dis.c: New, for NFP support.
948 po/POTFILES.in: Added nfp-dis.c to the list.
949 Makefile.in: Regenerate.
950 configure: Regenerate.
952 2018-04-26 Jan Beulich <jbeulich@suse.com>
954 * i386-opc.tbl: Fold various non-memory operand AVX512VL
955 templates into their base ones.
956 * i386-tlb.h: Re-generate.
958 2018-04-26 Jan Beulich <jbeulich@suse.com>
960 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
961 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
962 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
963 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
964 * i386-init.h: Re-generate.
966 2018-04-26 Jan Beulich <jbeulich@suse.com>
968 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
969 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
970 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
971 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
973 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
975 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
977 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
978 cpuregzmm, and cpuregmask.
979 * i386-init.h: Re-generate.
980 * i386-tbl.h: Re-generate.
982 2018-04-26 Jan Beulich <jbeulich@suse.com>
984 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
985 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
986 * i386-init.h: Re-generate.
988 2018-04-26 Jan Beulich <jbeulich@suse.com>
990 * i386-gen.c (VexImmExt): Delete.
991 * i386-opc.h (VexImmExt, veximmext): Delete.
992 * i386-opc.tbl: Drop all VexImmExt uses.
993 * i386-tlb.h: Re-generate.
995 2018-04-25 Jan Beulich <jbeulich@suse.com>
997 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
999 * i386-tlb.h: Re-generate.
1001 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1003 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1005 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1007 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1009 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1010 (cpu_flags): Add CpuCLDEMOTE.
1011 * i386-init.h: Regenerate.
1012 * i386-opc.h (enum): Add CpuCLDEMOTE,
1013 (i386_cpu_flags): Add cpucldemote.
1014 * i386-opc.tbl: Add cldemote.
1015 * i386-tbl.h: Regenerate.
1017 2018-04-16 Alan Modra <amodra@gmail.com>
1019 * Makefile.am: Remove sh5 and sh64 support.
1020 * configure.ac: Likewise.
1021 * disassemble.c: Likewise.
1022 * disassemble.h: Likewise.
1023 * sh-dis.c: Likewise.
1024 * sh64-dis.c: Delete.
1025 * sh64-opc.c: Delete.
1026 * sh64-opc.h: Delete.
1027 * Makefile.in: Regenerate.
1028 * configure: Regenerate.
1029 * po/POTFILES.in: Regenerate.
1031 2018-04-16 Alan Modra <amodra@gmail.com>
1033 * Makefile.am: Remove w65 support.
1034 * configure.ac: Likewise.
1035 * disassemble.c: Likewise.
1036 * disassemble.h: Likewise.
1037 * w65-dis.c: Delete.
1038 * w65-opc.h: Delete.
1039 * Makefile.in: Regenerate.
1040 * configure: Regenerate.
1041 * po/POTFILES.in: Regenerate.
1043 2018-04-16 Alan Modra <amodra@gmail.com>
1045 * configure.ac: Remove we32k support.
1046 * configure: Regenerate.
1048 2018-04-16 Alan Modra <amodra@gmail.com>
1050 * Makefile.am: Remove m88k support.
1051 * configure.ac: Likewise.
1052 * disassemble.c: Likewise.
1053 * disassemble.h: Likewise.
1054 * m88k-dis.c: Delete.
1055 * Makefile.in: Regenerate.
1056 * configure: Regenerate.
1057 * po/POTFILES.in: Regenerate.
1059 2018-04-16 Alan Modra <amodra@gmail.com>
1061 * Makefile.am: Remove i370 support.
1062 * configure.ac: Likewise.
1063 * disassemble.c: Likewise.
1064 * disassemble.h: Likewise.
1065 * i370-dis.c: Delete.
1066 * i370-opc.c: Delete.
1067 * Makefile.in: Regenerate.
1068 * configure: Regenerate.
1069 * po/POTFILES.in: Regenerate.
1071 2018-04-16 Alan Modra <amodra@gmail.com>
1073 * Makefile.am: Remove h8500 support.
1074 * configure.ac: Likewise.
1075 * disassemble.c: Likewise.
1076 * disassemble.h: Likewise.
1077 * h8500-dis.c: Delete.
1078 * h8500-opc.h: Delete.
1079 * Makefile.in: Regenerate.
1080 * configure: Regenerate.
1081 * po/POTFILES.in: Regenerate.
1083 2018-04-16 Alan Modra <amodra@gmail.com>
1085 * configure.ac: Remove tahoe support.
1086 * configure: Regenerate.
1088 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1090 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1092 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1094 * i386-tbl.h: Regenerated.
1096 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1098 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1099 PREFIX_MOD_1_0FAE_REG_6.
1101 (OP_E_register): Use va_mode.
1102 * i386-dis-evex.h (prefix_table):
1103 New instructions (see prefixes above).
1104 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1105 (cpu_flags): Likewise.
1106 * i386-opc.h (enum): Likewise.
1107 (i386_cpu_flags): Likewise.
1108 * i386-opc.tbl: Add umonitor, umwait, tpause.
1109 * i386-init.h: Regenerate.
1110 * i386-tbl.h: Likewise.
1112 2018-04-11 Alan Modra <amodra@gmail.com>
1114 * opcodes/i860-dis.c: Delete.
1115 * opcodes/i960-dis.c: Delete.
1116 * Makefile.am: Remove i860 and i960 support.
1117 * configure.ac: Likewise.
1118 * disassemble.c: Likewise.
1119 * disassemble.h: Likewise.
1120 * Makefile.in: Regenerate.
1121 * configure: Regenerate.
1122 * po/POTFILES.in: Regenerate.
1124 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1127 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1129 (print_insn): Clear vex instead of vex.evex.
1131 2018-04-04 Nick Clifton <nickc@redhat.com>
1133 * po/es.po: Updated Spanish translation.
1135 2018-03-28 Jan Beulich <jbeulich@suse.com>
1137 * i386-gen.c (opcode_modifiers): Delete VecESize.
1138 * i386-opc.h (VecESize): Delete.
1139 (struct i386_opcode_modifier): Delete vecesize.
1140 * i386-opc.tbl: Drop VecESize.
1141 * i386-tlb.h: Re-generate.
1143 2018-03-28 Jan Beulich <jbeulich@suse.com>
1145 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1146 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1147 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1148 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1149 * i386-tlb.h: Re-generate.
1151 2018-03-28 Jan Beulich <jbeulich@suse.com>
1153 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1155 * i386-tlb.h: Re-generate.
1157 2018-03-28 Jan Beulich <jbeulich@suse.com>
1159 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1160 (vex_len_table): Drop Y for vcvt*2si.
1161 (putop): Replace plain 'Y' handling by abort().
1163 2018-03-28 Nick Clifton <nickc@redhat.com>
1166 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1167 instructions with only a base address register.
1168 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1169 handle AARHC64_OPND_SVE_ADDR_R.
1170 (aarch64_print_operand): Likewise.
1171 * aarch64-asm-2.c: Regenerate.
1172 * aarch64_dis-2.c: Regenerate.
1173 * aarch64-opc-2.c: Regenerate.
1175 2018-03-22 Jan Beulich <jbeulich@suse.com>
1177 * i386-opc.tbl: Drop VecESize from register only insn forms and
1178 memory forms not allowing broadcast.
1179 * i386-tlb.h: Re-generate.
1181 2018-03-22 Jan Beulich <jbeulich@suse.com>
1183 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1184 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1185 sha256*): Drop Disp<N>.
1187 2018-03-22 Jan Beulich <jbeulich@suse.com>
1189 * i386-dis.c (EbndS, bnd_swap_mode): New.
1190 (prefix_table): Use EbndS.
1191 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1192 * i386-opc.tbl (bndmov): Move misplaced Load.
1193 * i386-tlb.h: Re-generate.
1195 2018-03-22 Jan Beulich <jbeulich@suse.com>
1197 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1198 templates allowing memory operands and folded ones for register
1200 * i386-tlb.h: Re-generate.
1202 2018-03-22 Jan Beulich <jbeulich@suse.com>
1204 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1205 256-bit templates. Drop redundant leftover Disp<N>.
1206 * i386-tlb.h: Re-generate.
1208 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1210 * riscv-opc.c (riscv_insn_types): New.
1212 2018-03-13 Nick Clifton <nickc@redhat.com>
1214 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1216 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1218 * i386-opc.tbl: Add Optimize to clr.
1219 * i386-tbl.h: Regenerated.
1221 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1223 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1224 * i386-opc.h (OldGcc): Removed.
1225 (i386_opcode_modifier): Remove oldgcc.
1226 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1227 instructions for old (<= 2.8.1) versions of gcc.
1228 * i386-tbl.h: Regenerated.
1230 2018-03-08 Jan Beulich <jbeulich@suse.com>
1232 * i386-opc.h (EVEXDYN): New.
1233 * i386-opc.tbl: Fold various AVX512VL templates.
1234 * i386-tlb.h: Re-generate.
1236 2018-03-08 Jan Beulich <jbeulich@suse.com>
1238 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1239 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1240 vpexpandd, vpexpandq): Fold AFX512VF templates.
1241 * i386-tlb.h: Re-generate.
1243 2018-03-08 Jan Beulich <jbeulich@suse.com>
1245 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1246 Fold 128- and 256-bit VEX-encoded templates.
1247 * i386-tlb.h: Re-generate.
1249 2018-03-08 Jan Beulich <jbeulich@suse.com>
1251 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1252 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1253 vpexpandd, vpexpandq): Fold AVX512F templates.
1254 * i386-tlb.h: Re-generate.
1256 2018-03-08 Jan Beulich <jbeulich@suse.com>
1258 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1259 64-bit templates. Drop Disp<N>.
1260 * i386-tlb.h: Re-generate.
1262 2018-03-08 Jan Beulich <jbeulich@suse.com>
1264 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1265 and 256-bit templates.
1266 * i386-tlb.h: Re-generate.
1268 2018-03-08 Jan Beulich <jbeulich@suse.com>
1270 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1271 * i386-tlb.h: Re-generate.
1273 2018-03-08 Jan Beulich <jbeulich@suse.com>
1275 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1277 * i386-tlb.h: Re-generate.
1279 2018-03-08 Jan Beulich <jbeulich@suse.com>
1281 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1282 * i386-tlb.h: Re-generate.
1284 2018-03-08 Jan Beulich <jbeulich@suse.com>
1286 * i386-gen.c (opcode_modifiers): Delete FloatD.
1287 * i386-opc.h (FloatD): Delete.
1288 (struct i386_opcode_modifier): Delete floatd.
1289 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1291 * i386-tlb.h: Re-generate.
1293 2018-03-08 Jan Beulich <jbeulich@suse.com>
1295 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1297 2018-03-08 Jan Beulich <jbeulich@suse.com>
1299 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1300 * i386-tlb.h: Re-generate.
1302 2018-03-08 Jan Beulich <jbeulich@suse.com>
1304 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1306 * i386-tlb.h: Re-generate.
1308 2018-03-07 Alan Modra <amodra@gmail.com>
1310 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1312 * disassemble.h (print_insn_rs6000): Delete.
1313 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1314 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1315 (print_insn_rs6000): Delete.
1317 2018-03-03 Alan Modra <amodra@gmail.com>
1319 * sysdep.h (opcodes_error_handler): Define.
1320 (_bfd_error_handler): Declare.
1321 * Makefile.am: Remove stray #.
1322 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1324 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1325 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1326 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1327 opcodes_error_handler to print errors. Standardize error messages.
1328 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1329 and include opintl.h.
1330 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1331 * i386-gen.c: Standardize error messages.
1332 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1333 * Makefile.in: Regenerate.
1334 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1335 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1336 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1337 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1338 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1339 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1340 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1341 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1342 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1343 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1344 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1345 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1346 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1348 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1350 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1351 vpsub[bwdq] instructions.
1352 * i386-tbl.h: Regenerated.
1354 2018-03-01 Alan Modra <amodra@gmail.com>
1356 * configure.ac (ALL_LINGUAS): Sort.
1357 * configure: Regenerate.
1359 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1361 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1362 macro by assignements.
1364 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1367 * i386-gen.c (opcode_modifiers): Add Optimize.
1368 * i386-opc.h (Optimize): New enum.
1369 (i386_opcode_modifier): Add optimize.
1370 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1371 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1372 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1373 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1374 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1376 * i386-tbl.h: Regenerated.
1378 2018-02-26 Alan Modra <amodra@gmail.com>
1380 * crx-dis.c (getregliststring): Allocate a large enough buffer
1381 to silence false positive gcc8 warning.
1383 2018-02-22 Shea Levy <shea@shealevy.com>
1385 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1387 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1389 * i386-opc.tbl: Add {rex},
1390 * i386-tbl.h: Regenerated.
1392 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1394 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1395 (mips16_opcodes): Replace `M' with `m' for "restore".
1397 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1399 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1401 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1403 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1404 variable to `function_index'.
1406 2018-02-13 Nick Clifton <nickc@redhat.com>
1409 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1410 about truncation of printing.
1412 2018-02-12 Henry Wong <henry@stuffedcow.net>
1414 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1416 2018-02-05 Nick Clifton <nickc@redhat.com>
1418 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1420 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1422 * i386-dis.c (enum): Add pconfig.
1423 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1424 (cpu_flags): Add CpuPCONFIG.
1425 * i386-opc.h (enum): Add CpuPCONFIG.
1426 (i386_cpu_flags): Add cpupconfig.
1427 * i386-opc.tbl: Add PCONFIG instruction.
1428 * i386-init.h: Regenerate.
1429 * i386-tbl.h: Likewise.
1431 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1433 * i386-dis.c (enum): Add PREFIX_0F09.
1434 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1435 (cpu_flags): Add CpuWBNOINVD.
1436 * i386-opc.h (enum): Add CpuWBNOINVD.
1437 (i386_cpu_flags): Add cpuwbnoinvd.
1438 * i386-opc.tbl: Add WBNOINVD instruction.
1439 * i386-init.h: Regenerate.
1440 * i386-tbl.h: Likewise.
1442 2018-01-17 Jim Wilson <jimw@sifive.com>
1444 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1446 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1448 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1449 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1450 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1451 (cpu_flags): Add CpuIBT, CpuSHSTK.
1452 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1453 (i386_cpu_flags): Add cpuibt, cpushstk.
1454 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1455 * i386-init.h: Regenerate.
1456 * i386-tbl.h: Likewise.
1458 2018-01-16 Nick Clifton <nickc@redhat.com>
1460 * po/pt_BR.po: Updated Brazilian Portugese translation.
1461 * po/de.po: Updated German translation.
1463 2018-01-15 Jim Wilson <jimw@sifive.com>
1465 * riscv-opc.c (match_c_nop): New.
1466 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1468 2018-01-15 Nick Clifton <nickc@redhat.com>
1470 * po/uk.po: Updated Ukranian translation.
1472 2018-01-13 Nick Clifton <nickc@redhat.com>
1474 * po/opcodes.pot: Regenerated.
1476 2018-01-13 Nick Clifton <nickc@redhat.com>
1478 * configure: Regenerate.
1480 2018-01-13 Nick Clifton <nickc@redhat.com>
1482 2.30 branch created.
1484 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1486 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1487 * i386-tbl.h: Regenerate.
1489 2018-01-10 Jan Beulich <jbeulich@suse.com>
1491 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1492 * i386-tbl.h: Re-generate.
1494 2018-01-10 Jan Beulich <jbeulich@suse.com>
1496 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1497 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1498 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1499 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1500 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1501 Disp8MemShift of AVX512VL forms.
1502 * i386-tbl.h: Re-generate.
1504 2018-01-09 Jim Wilson <jimw@sifive.com>
1506 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1507 then the hi_addr value is zero.
1509 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1511 * arm-dis.c (arm_opcodes): Add csdb.
1512 (thumb32_opcodes): Add csdb.
1514 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1516 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1517 * aarch64-asm-2.c: Regenerate.
1518 * aarch64-dis-2.c: Regenerate.
1519 * aarch64-opc-2.c: Regenerate.
1521 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1524 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1525 Remove AVX512 vmovd with 64-bit operands.
1526 * i386-tbl.h: Regenerated.
1528 2018-01-05 Jim Wilson <jimw@sifive.com>
1530 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1533 2018-01-03 Alan Modra <amodra@gmail.com>
1535 Update year range in copyright notice of all files.
1537 2018-01-02 Jan Beulich <jbeulich@suse.com>
1539 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1540 and OPERAND_TYPE_REGZMM entries.
1542 For older changes see ChangeLog-2017
1544 Copyright (C) 2018 Free Software Foundation, Inc.
1546 Copying and distribution of this file, with or without modification,
1547 are permitted in any medium without royalty provided the copyright
1548 notice and this notice are preserved.
1554 version-control: never