opcodes/ChangeLog

   1 2019-07-17  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (static_assert): Define.
   4         (main): Use it.
   5         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
   6         (Opcode_Modifier_Num): ... this.
   7         (Mem): Delete.
   8
   9 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-gen.c (operand_types): Move RegMem ...
  12         (opcode_modifiers): ... here.
  13         * i386-opc.h (RegMem): Move to opcode modifer enum.
  14         (union i386_operand_type): Move regmem field ...
  15         (struct i386_opcode_modifier): ... here.
  16         * i386-opc.tbl (RegMem): Define.
  17         (mov, movq): Move RegMem on segment, control, debug, and test
  18         register flavors.
  19         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
  20         to non-SSE2AVX flavor.
  21         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
  22         Move RegMem on register only flavors. Drop IgnoreSize from
  23         legacy encoding flavors.
  24         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
  25         flavors.
  26         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
  27         register only flavors.
  28         (vmovd): Move RegMem and drop IgnoreSize on register only
  29         flavor. Change opcode and operand order to store form.
  30         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  31
  32 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-gen.c (operand_type_init, operand_types): Replace SReg
  35         entries.
  36         * i386-opc.h (SReg2, SReg3): Replace by ...
  37         (SReg): ... this.
  38         (union i386_operand_type): Replace sreg fields.
  39         * i386-opc.tbl (mov, ): Use SReg.
  40         (push, pop): Likewies. Drop i386 and x86-64 specific segment
  41         register flavors.
  42         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
  43         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  44
  45 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
  46
  47         * bpf-desc.c: Regenerate.
  48         * bpf-opc.c: Likewise.
  49         * bpf-opc.h: Likewise.
  50
  51 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
  52
  53         * bpf-desc.c: Regenerate.
  54         * bpf-opc.c: Likewise.
  55
  56 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
  57
  58         * arm-dis.c (print_insn_coprocessor): Rename index to
  59         index_operand.
  60
  61 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
  62
  63         * riscv-opc.c (riscv_insn_types): Add r4 type.
  64
  65         * riscv-opc.c (riscv_insn_types): Add b and j type.
  66
  67         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
  68         format for sb type and correct s type.
  69
  70 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  71
  72         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
  73         SVE FMOV alias of FCPY.
  74
  75 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  76
  77         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
  78         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
  79
  80 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  81
  82         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
  83         registers in an instruction prefixed by MOVPRFX.
  84
  85 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
  86
  87         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
  88         sve_size_13 icode to account for variant behaviour of
  89         pmull{t,b}.
  90         * aarch64-dis-2.c: Regenerate.
  91         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
  92         sve_size_13 icode to account for variant behaviour of
  93         pmull{t,b}.
  94         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
  95         (OP_SVE_VVV_Q_D): Add new qualifier.
  96         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
  97         (struct aarch64_opcode): Split pmull{t,b} into those requiring
  98         AES and those not.
  99
 100 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 101
 102         * opcodes/i386-gen.c (operand_type_init): Remove
 103         OPERAND_TYPE_VEC_IMM4 entry.
 104         (operand_types): Remove Vec_Imm4.
 105         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 106         (union i386_operand_type): Remove vec_imm4.
 107         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 108         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 109
 110 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 111
 112         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 113         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 114         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 115         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 116         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 117         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 118         * i386-tbl.h: Re-generate.
 119
 120 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 123         register operands.
 124         * i386-tbl.h: Re-generate.
 125
 126 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 127
 128         * i386-opc.tbl (C): New.
 129         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 130         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 131         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 132         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 133         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 134         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 135         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 136         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 137         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 138         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 139         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 140         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 141         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 142         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 143         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 144         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 145         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 146         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 147         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 148         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 149         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 150         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 151         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 152         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 153         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 154         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 155         flavors.
 156         * i386-tbl.h: Re-generate.
 157
 158 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 159
 160         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 161         register operands.
 162         * i386-tbl.h: Re-generate.
 163
 164 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 167         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 168         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 169         * i386-tbl.h: Re-generate.
 170
 171 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 174         Disp8MemShift from register only templates.
 175         * i386-tbl.h: Re-generate.
 176
 177 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 180         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 181         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 182         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 183         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 184         EVEX_W_0F11_P_3_M_1): Delete.
 185         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 186         EVEX_W_0F11_P_3): New.
 187         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 188         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 189         MOD_EVEX_0F11_PREFIX_3 table entries.
 190         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 191         PREFIX_EVEX_0F11 table entries.
 192         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 193         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 194         EVEX_W_0F11_P_3_M_{0,1} table entries.
 195
 196 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 199         Delete.
 200
 201 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 202
 203         PR binutils/24719
 204         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 205         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 206         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 207         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 208         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 209         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 210         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 211         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 212         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 213         PREFIX_EVEX_0F38C6_REG_6 entries.
 214         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 215         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 216         EVEX_W_0F38C7_R_6_P_2 entries.
 217         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 218         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 219         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 220         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 221         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 222         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 223         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 224
 225 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 228         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 229         VEX_LEN_0F2D_P_3): Delete.
 230         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 231         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 232         (prefix_table): ... here.
 233
 234 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-dis.c (Iq): Delete.
 237         (Id): New.
 238         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 239         TBM insns.
 240         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 241         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 242         (OP_E_memory): Also honor needindex when deciding whether an
 243         address size prefix needs printing.
 244         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 245
 246 2019-06-26  Jim Wilson  <jimw@sifive.com>
 247
 248         PR binutils/24739
 249         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 250         Set info->display_endian to info->endian_code.
 251
 252 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 255         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 256         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 257         OPERAND_TYPE_ACC64 entries.
 258         * i386-init.h: Re-generate.
 259
 260 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 263         Delete.
 264         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 265         of dqa_mode.
 266         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 267         entries here.
 268         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 269         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 270
 271 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 272
 273         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 274         variables.
 275
 276 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 279         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 280         movnti.
 281         * i386-opc.tbl (movnti): Add IgnoreSize.
 282         * i386-tbl.h: Re-generate.
 283
 284 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 285
 286         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 287         * i386-tbl.h: Re-generate.
 288
 289 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 290
 291         * i386-dis-evex.h: Break into ...
 292         * i386-dis-evex-len.h: New file.
 293         * i386-dis-evex-mod.h: Likewise.
 294         * i386-dis-evex-prefix.h: Likewise.
 295         * i386-dis-evex-reg.h: Likewise.
 296         * i386-dis-evex-w.h: Likewise.
 297         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 298         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 299         i386-dis-evex-mod.h.
 300
 301 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 302
 303         PR binutils/24700
 304         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 305         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 306         EVEX_W_0F385B_P_2.
 307         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 308         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 309         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 310         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 311         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 312         EVEX_LEN_0F385B_P_2_W_1.
 313         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 314         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 315         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 316         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 317         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 318         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 319         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 320         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 321         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 322         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 323
 324 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 325
 326         PR binutils/24691
 327         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 328         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 329         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 330         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 331         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 332         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 333         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 334         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 335         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 336         EVEX_LEN_0F3A43_P_2_W_1.
 337         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 338         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 339         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 340         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 341         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 342         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 343         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 344         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 345         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 346         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 347         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 348         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 349
 350 2019-06-14  Nick Clifton  <nickc@redhat.com>
 351
 352         * po/fr.po; Updated French translation.
 353
 354 2019-06-13  Stafford Horne  <shorne@gmail.com>
 355
 356         * or1k-asm.c: Regenerated.
 357         * or1k-desc.c: Regenerated.
 358         * or1k-desc.h: Regenerated.
 359         * or1k-dis.c: Regenerated.
 360         * or1k-ibld.c: Regenerated.
 361         * or1k-opc.c: Regenerated.
 362         * or1k-opc.h: Regenerated.
 363         * or1k-opinst.c: Regenerated.
 364
 365 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 366
 367         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 368
 369 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 370
 371         PR binutils/24633
 372         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 373         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 374         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 375         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 376         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 377         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 378         EVEX_LEN_0F3A1B_P_2_W_1.
 379         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 380         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 381         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 382         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 383         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 384         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 385         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 386         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 387
 388 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 389
 390         PR binutils/24626
 391         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 392         EVEX.vvvv when disassembling VEX and EVEX instructions.
 393         (OP_VEX): Set vex.register_specifier to 0 after readding
 394         vex.register_specifier.
 395         (OP_Vex_2src_1): Likewise.
 396         (OP_Vex_2src_2): Likewise.
 397         (OP_LWP_E): Likewise.
 398         (OP_EX_Vex): Don't check vex.register_specifier.
 399         (OP_XMM_Vex): Likewise.
 400
 401 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 402             Lili Cui  <lili.cui@intel.com>
 403
 404         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 405         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 406         instructions.
 407         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 408         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 409         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 410         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 411         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 412         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 413         * i386-init.h: Regenerated.
 414         * i386-tbl.h: Likewise.
 415
 416 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 417             Lili Cui  <lili.cui@intel.com>
 418
 419         * doc/c-i386.texi: Document enqcmd.
 420         * testsuite/gas/i386/enqcmd-intel.d: New file.
 421         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 422         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 423         * testsuite/gas/i386/enqcmd.d: Likewise.
 424         * testsuite/gas/i386/enqcmd.s: Likewise.
 425         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 426         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 427         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 428         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 429         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 430         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 431         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 432         and x86-64-enqcmd.
 433
 434 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 435
 436         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 437
 438 2019-06-03  Alan Modra  <amodra@gmail.com>
 439
 440         * ppc-dis.c (prefix_opcd_indices): Correct size.
 441
 442 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         PR gas/24625
 445         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 446         Disp8ShiftVL.
 447         * i386-tbl.h: Regenerated.
 448
 449 2019-05-24  Alan Modra  <amodra@gmail.com>
 450
 451         * po/POTFILES.in: Regenerate.
 452
 453 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 454             Alan Modra  <amodra@gmail.com>
 455
 456         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 457         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 458         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 459         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 460         XTOP>): Define and add entries.
 461         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 462         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 463         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 464         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 465
 466 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 467             Alan Modra  <amodra@gmail.com>
 468
 469         * ppc-dis.c (ppc_opts): Add "future" entry.
 470         (PREFIX_OPCD_SEGS): Define.
 471         (prefix_opcd_indices): New array.
 472         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 473         (lookup_prefix): New function.
 474         (print_insn_powerpc): Handle 64-bit prefix instructions.
 475         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 476         (PMRR, POWERXX): Define.
 477         (prefix_opcodes): New instruction table.
 478         (prefix_num_opcodes): New constant.
 479
 480 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 481
 482         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 483         * configure: Regenerated.
 484         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 485         and cpu/bpf.opc.
 486         (HFILES): Add bpf-desc.h and bpf-opc.h.
 487         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 488         bpf-ibld.c and bpf-opc.c.
 489         (BPF_DEPS): Define.
 490         * Makefile.in: Regenerated.
 491         * disassemble.c (ARCH_bpf): Define.
 492         (disassembler): Add case for bfd_arch_bpf.
 493         (disassemble_init_for_target): Likewise.
 494         (enum epbf_isa_attr): Define.
 495         * disassemble.h: extern print_insn_bpf.
 496         * bpf-asm.c: Generated.
 497         * bpf-opc.h: Likewise.
 498         * bpf-opc.c: Likewise.
 499         * bpf-ibld.c: Likewise.
 500         * bpf-dis.c: Likewise.
 501         * bpf-desc.h: Likewise.
 502         * bpf-desc.c: Likewise.
 503
 504 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 505
 506         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 507         and VMSR with the new operands.
 508
 509 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 510
 511         * arm-dis.c (enum mve_instructions): New enum
 512         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 513         and cneg.
 514         (mve_opcodes): New instructions as above.
 515         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 516         csneg and csel.
 517         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 518
 519 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 520
 521         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 522         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 523         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 524         uqshl, urshrl and urshr.
 525         (is_mve_okay_in_it): Add new instructions to TRUE list.
 526         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 527         (print_insn_mve): Updated to accept new %j,
 528         %<bitfield>m and %<bitfield>n patterns.
 529
 530 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 531
 532         * mips-opc.c (mips_builtin_opcodes): Change source register
 533         constraint for DAUI.
 534
 535 2019-05-20  Nick Clifton  <nickc@redhat.com>
 536
 537         * po/fr.po: Updated French translation.
 538
 539 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 540             Michael Collison <michael.collison@arm.com>
 541
 542         * arm-dis.c (thumb32_opcodes): Add new instructions.
 543         (enum mve_instructions): Likewise.
 544         (enum mve_undefined): Add new reasons.
 545         (is_mve_encoding_conflict): Handle new instructions.
 546         (is_mve_undefined): Likewise.
 547         (is_mve_unpredictable): Likewise.
 548         (print_mve_undefined): Likewise.
 549         (print_mve_size): Likewise.
 550
 551 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 552             Michael Collison <michael.collison@arm.com>
 553
 554         * arm-dis.c (thumb32_opcodes): Add new instructions.
 555         (enum mve_instructions): Likewise.
 556         (is_mve_encoding_conflict): Handle new instructions.
 557         (is_mve_undefined): Likewise.
 558         (is_mve_unpredictable): Likewise.
 559         (print_mve_size): Likewise.
 560
 561 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 562             Michael Collison <michael.collison@arm.com>
 563
 564         * arm-dis.c (thumb32_opcodes): Add new instructions.
 565         (enum mve_instructions): Likewise.
 566         (is_mve_encoding_conflict): Likewise.
 567         (is_mve_unpredictable): Likewise.
 568         (print_mve_size): Likewise.
 569
 570 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 571             Michael Collison <michael.collison@arm.com>
 572
 573         * arm-dis.c (thumb32_opcodes): Add new instructions.
 574         (enum mve_instructions): Likewise.
 575         (is_mve_encoding_conflict): Handle new instructions.
 576         (is_mve_undefined): Likewise.
 577         (is_mve_unpredictable): Likewise.
 578         (print_mve_size): Likewise.
 579
 580 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 581             Michael Collison <michael.collison@arm.com>
 582
 583         * arm-dis.c (thumb32_opcodes): Add new instructions.
 584         (enum mve_instructions): Likewise.
 585         (is_mve_encoding_conflict): Handle new instructions.
 586         (is_mve_undefined): Likewise.
 587         (is_mve_unpredictable): Likewise.
 588         (print_mve_size): Likewise.
 589         (print_insn_mve): Likewise.
 590
 591 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 592             Michael Collison <michael.collison@arm.com>
 593
 594         * arm-dis.c (thumb32_opcodes): Add new instructions.
 595         (print_insn_thumb32): Handle new instructions.
 596
 597 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 598             Michael Collison <michael.collison@arm.com>
 599
 600         * arm-dis.c (enum mve_instructions): Add new instructions.
 601         (enum mve_undefined): Add new reasons.
 602         (is_mve_encoding_conflict): Handle new instructions.
 603         (is_mve_undefined): Likewise.
 604         (is_mve_unpredictable): Likewise.
 605         (print_mve_undefined): Likewise.
 606         (print_mve_size): Likewise.
 607         (print_mve_shift_n): Likewise.
 608         (print_insn_mve): Likewise.
 609
 610 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 611             Michael Collison <michael.collison@arm.com>
 612
 613         * arm-dis.c (enum mve_instructions): Add new instructions.
 614         (is_mve_encoding_conflict): Handle new instructions.
 615         (is_mve_unpredictable): Likewise.
 616         (print_mve_rotate): Likewise.
 617         (print_mve_size): Likewise.
 618         (print_insn_mve): Likewise.
 619
 620 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 621             Michael Collison <michael.collison@arm.com>
 622
 623         * arm-dis.c (enum mve_instructions): Add new instructions.
 624         (is_mve_encoding_conflict): Handle new instructions.
 625         (is_mve_unpredictable): Likewise.
 626         (print_mve_size): Likewise.
 627         (print_insn_mve): Likewise.
 628
 629 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 630             Michael Collison <michael.collison@arm.com>
 631
 632         * arm-dis.c (enum mve_instructions): Add new instructions.
 633         (enum mve_undefined): Add new reasons.
 634         (is_mve_encoding_conflict): Handle new instructions.
 635         (is_mve_undefined): Likewise.
 636         (is_mve_unpredictable): Likewise.
 637         (print_mve_undefined): Likewise.
 638         (print_mve_size): Likewise.
 639         (print_insn_mve): Likewise.
 640
 641 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 642             Michael Collison <michael.collison@arm.com>
 643
 644         * arm-dis.c (enum mve_instructions): Add new instructions.
 645         (is_mve_encoding_conflict): Handle new instructions.
 646         (is_mve_undefined): Likewise.
 647         (is_mve_unpredictable): Likewise.
 648         (print_mve_size): Likewise.
 649         (print_insn_mve): Likewise.
 650
 651 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 652             Michael Collison <michael.collison@arm.com>
 653
 654         * arm-dis.c (enum mve_instructions): Add new instructions.
 655         (enum mve_unpredictable): Add new reasons.
 656         (enum mve_undefined): Likewise.
 657         (is_mve_okay_in_it): Handle new isntructions.
 658         (is_mve_encoding_conflict): Likewise.
 659         (is_mve_undefined): Likewise.
 660         (is_mve_unpredictable): Likewise.
 661         (print_mve_vmov_index): Likewise.
 662         (print_simd_imm8): Likewise.
 663         (print_mve_undefined): Likewise.
 664         (print_mve_unpredictable): Likewise.
 665         (print_mve_size): Likewise.
 666         (print_insn_mve): Likewise.
 667
 668 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 669             Michael Collison <michael.collison@arm.com>
 670
 671         * arm-dis.c (enum mve_instructions): Add new instructions.
 672         (enum mve_unpredictable): Add new reasons.
 673         (enum mve_undefined): Likewise.
 674         (is_mve_encoding_conflict): Handle new instructions.
 675         (is_mve_undefined): Likewise.
 676         (is_mve_unpredictable): Likewise.
 677         (print_mve_undefined): Likewise.
 678         (print_mve_unpredictable): Likewise.
 679         (print_mve_rounding_mode): Likewise.
 680         (print_mve_vcvt_size): Likewise.
 681         (print_mve_size): Likewise.
 682         (print_insn_mve): Likewise.
 683
 684 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 685             Michael Collison <michael.collison@arm.com>
 686
 687         * arm-dis.c (enum mve_instructions): Add new instructions.
 688         (enum mve_unpredictable): Add new reasons.
 689         (enum mve_undefined): Likewise.
 690         (is_mve_undefined): Handle new instructions.
 691         (is_mve_unpredictable): Likewise.
 692         (print_mve_undefined): Likewise.
 693         (print_mve_unpredictable): Likewise.
 694         (print_mve_size): Likewise.
 695         (print_insn_mve): Likewise.
 696
 697 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 698             Michael Collison <michael.collison@arm.com>
 699
 700         * arm-dis.c (enum mve_instructions): Add new instructions.
 701         (enum mve_undefined): Add new reasons.
 702         (insns): Add new instructions.
 703         (is_mve_encoding_conflict):
 704         (print_mve_vld_str_addr): New print function.
 705         (is_mve_undefined): Handle new instructions.
 706         (is_mve_unpredictable): Likewise.
 707         (print_mve_undefined): Likewise.
 708         (print_mve_size): Likewise.
 709         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 710         (print_insn_mve):  Handle new operands.
 711
 712 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 713             Michael Collison <michael.collison@arm.com>
 714
 715         * arm-dis.c (enum mve_instructions): Add new instructions.
 716         (enum mve_unpredictable): Add new reasons.
 717         (is_mve_encoding_conflict): Handle new instructions.
 718         (is_mve_unpredictable): Likewise.
 719         (mve_opcodes): Add new instructions.
 720         (print_mve_unpredictable): Handle new reasons.
 721         (print_mve_register_blocks): New print function.
 722         (print_mve_size): Handle new instructions.
 723         (print_insn_mve): Likewise.
 724
 725 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 726             Michael Collison <michael.collison@arm.com>
 727
 728         * arm-dis.c (enum mve_instructions): Add new instructions.
 729         (enum mve_unpredictable): Add new reasons.
 730         (enum mve_undefined): Likewise.
 731         (is_mve_encoding_conflict): Handle new instructions.
 732         (is_mve_undefined): Likewise.
 733         (is_mve_unpredictable): Likewise.
 734         (coprocessor_opcodes): Move NEON VDUP from here...
 735         (neon_opcodes): ... to here.
 736         (mve_opcodes): Add new instructions.
 737         (print_mve_undefined):  Handle new reasons.
 738         (print_mve_unpredictable): Likewise.
 739         (print_mve_size): Handle new instructions.
 740         (print_insn_neon): Handle vdup.
 741         (print_insn_mve): Handle new operands.
 742
 743 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 744             Michael Collison <michael.collison@arm.com>
 745
 746         * arm-dis.c (enum mve_instructions): Add new instructions.
 747         (enum mve_unpredictable): Add new values.
 748         (mve_opcodes): Add new instructions.
 749         (vec_condnames): New array with vector conditions.
 750         (mve_predicatenames): New array with predicate suffixes.
 751         (mve_vec_sizename): New array with vector sizes.
 752         (enum vpt_pred_state): New enum with vector predication states.
 753         (struct vpt_block): New struct type for vpt blocks.
 754         (vpt_block_state): Global struct to keep track of state.
 755         (mve_extract_pred_mask): New helper function.
 756         (num_instructions_vpt_block): Likewise.
 757         (mark_outside_vpt_block): Likewise.
 758         (mark_inside_vpt_block): Likewise.
 759         (invert_next_predicate_state): Likewise.
 760         (update_next_predicate_state): Likewise.
 761         (update_vpt_block_state): Likewise.
 762         (is_vpt_instruction): Likewise.
 763         (is_mve_encoding_conflict): Add entries for new instructions.
 764         (is_mve_unpredictable): Likewise.
 765         (print_mve_unpredictable): Handle new cases.
 766         (print_instruction_predicate): Likewise.
 767         (print_mve_size): New function.
 768         (print_vec_condition): New function.
 769         (print_insn_mve): Handle vpt blocks and new print operands.
 770
 771 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 772
 773         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 774         8, 14 and 15 for Armv8.1-M Mainline.
 775
 776 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 777             Michael Collison <michael.collison@arm.com>
 778
 779         * arm-dis.c (enum mve_instructions): New enum.
 780         (enum mve_unpredictable): Likewise.
 781         (enum mve_undefined): Likewise.
 782         (struct mopcode32): New struct.
 783         (is_mve_okay_in_it): New function.
 784         (is_mve_architecture): Likewise.
 785         (arm_decode_field): Likewise.
 786         (arm_decode_field_multiple): Likewise.
 787         (is_mve_encoding_conflict): Likewise.
 788         (is_mve_undefined): Likewise.
 789         (is_mve_unpredictable): Likewise.
 790         (print_mve_undefined): Likewise.
 791         (print_mve_unpredictable): Likewise.
 792         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 793         (print_insn_mve): New function.
 794         (print_insn_thumb32): Handle MVE architecture.
 795         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 796
 797 2019-05-10  Nick Clifton  <nickc@redhat.com>
 798
 799         PR 24538
 800         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 801         end of the table prematurely.
 802
 803 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 804
 805         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 806         macros for R6.
 807
 808 2019-05-11  Alan Modra  <amodra@gmail.com>
 809
 810         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 811         when -Mraw is in effect.
 812
 813 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 814
 815         * aarch64-dis-2.c: Regenerate.
 816         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 817         (OP_SVE_BBB): New variant set.
 818         (OP_SVE_DDDD): New variant set.
 819         (OP_SVE_HHH): New variant set.
 820         (OP_SVE_HHHU): New variant set.
 821         (OP_SVE_SSS): New variant set.
 822         (OP_SVE_SSSU): New variant set.
 823         (OP_SVE_SHH): New variant set.
 824         (OP_SVE_SBBU): New variant set.
 825         (OP_SVE_DSS): New variant set.
 826         (OP_SVE_DHHU): New variant set.
 827         (OP_SVE_VMV_HSD_BHS): New variant set.
 828         (OP_SVE_VVU_HSD_BHS): New variant set.
 829         (OP_SVE_VVVU_SD_BH): New variant set.
 830         (OP_SVE_VVVU_BHSD): New variant set.
 831         (OP_SVE_VVV_QHD_DBS): New variant set.
 832         (OP_SVE_VVV_HSD_BHS): New variant set.
 833         (OP_SVE_VVV_HSD_BHS2): New variant set.
 834         (OP_SVE_VVV_BHS_HSD): New variant set.
 835         (OP_SVE_VV_BHS_HSD): New variant set.
 836         (OP_SVE_VVV_SD): New variant set.
 837         (OP_SVE_VVU_BHS_HSD): New variant set.
 838         (OP_SVE_VZVV_SD): New variant set.
 839         (OP_SVE_VZVV_BH): New variant set.
 840         (OP_SVE_VZV_SD): New variant set.
 841         (aarch64_opcode_table): Add sve2 instructions.
 842
 843 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 844
 845         * aarch64-asm-2.c: Regenerated.
 846         * aarch64-dis-2.c: Regenerated.
 847         * aarch64-opc-2.c: Regenerated.
 848         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 849         for SVE_SHLIMM_UNPRED_22.
 850         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 851         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 852         operand.
 853
 854 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 855
 856         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 857         sve_size_tsz_bhs iclass encode.
 858         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 859         sve_size_tsz_bhs iclass decode.
 860
 861 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 862
 863         * aarch64-asm-2.c: Regenerated.
 864         * aarch64-dis-2.c: Regenerated.
 865         * aarch64-opc-2.c: Regenerated.
 866         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 867         for SVE_Zm4_11_INDEX.
 868         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 869         (fields): Handle SVE_i2h field.
 870         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 871         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 872
 873 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 874
 875         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 876         sve_shift_tsz_bhsd iclass encode.
 877         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 878         sve_shift_tsz_bhsd iclass decode.
 879
 880 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 881
 882         * aarch64-asm-2.c: Regenerated.
 883         * aarch64-dis-2.c: Regenerated.
 884         * aarch64-opc-2.c: Regenerated.
 885         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 886         (aarch64_encode_variant_using_iclass): Handle
 887         sve_shift_tsz_hsd iclass encode.
 888         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 889         sve_shift_tsz_hsd iclass decode.
 890         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 891         for SVE_SHRIMM_UNPRED_22.
 892         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 893         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 894         operand.
 895
 896 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 897
 898         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 899         sve_size_013 iclass encode.
 900         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 901         sve_size_013 iclass decode.
 902
 903 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 904
 905         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 906         sve_size_bh iclass encode.
 907         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 908         sve_size_bh iclass decode.
 909
 910 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 911
 912         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 913         sve_size_sd2 iclass encode.
 914         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 915         sve_size_sd2 iclass decode.
 916         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 917         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 918
 919 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 920
 921         * aarch64-asm-2.c: Regenerated.
 922         * aarch64-dis-2.c: Regenerated.
 923         * aarch64-opc-2.c: Regenerated.
 924         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 925         for SVE_ADDR_ZX.
 926         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 927         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 928
 929 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 930
 931         * aarch64-asm-2.c: Regenerated.
 932         * aarch64-dis-2.c: Regenerated.
 933         * aarch64-opc-2.c: Regenerated.
 934         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 935         for SVE_Zm3_11_INDEX.
 936         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 937         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 938         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 939         fields.
 940         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 941
 942 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 943
 944         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 945         sve_size_hsd2 iclass encode.
 946         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 947         sve_size_hsd2 iclass decode.
 948         * aarch64-opc.c (fields): Handle SVE_size field.
 949         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 950
 951 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 952
 953         * aarch64-asm-2.c: Regenerated.
 954         * aarch64-dis-2.c: Regenerated.
 955         * aarch64-opc-2.c: Regenerated.
 956         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 957         for SVE_IMM_ROT3.
 958         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 959         (fields): Handle SVE_rot3 field.
 960         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 961         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 962
 963 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 964
 965         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 966         instructions.
 967
 968 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 969
 970         * aarch64-tbl.h
 971         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 972         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 973         aarch64_feature_sve2bitperm): New feature sets.
 974         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 975         for feature set addresses.
 976         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 977         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 978
 979 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 980             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 981
 982         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 983         argument and set ASE_EVA_R6 appropriately.
 984         (set_default_mips_dis_options): Pass ISA to above.
 985         (parse_mips_dis_option): Likewise.
 986         * mips-opc.c (EVAR6): New macro.
 987         (mips_builtin_opcodes): Add llwpe, scwpe.
 988
 989 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 990
 991         * aarch64-asm-2.c: Regenerated.
 992         * aarch64-dis-2.c: Regenerated.
 993         * aarch64-opc-2.c: Regenerated.
 994         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 995         AARCH64_OPND_TME_UIMM16.
 996         (aarch64_print_operand): Likewise.
 997         * aarch64-tbl.h (QL_IMM_NIL): New.
 998         (TME): New.
 999         (_TME_INSN): New.
1000         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1001
1002 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1003
1004         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1005
1006 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1007             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1008
1009         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1010
1011 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1012
1013         * s12z-opc.h: Add extern "C" bracketing to help
1014         users who wish to use this interface in c++ code.
1015
1016 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1017
1018         * s12z-opc.c (bm_decode): Handle bit map operations with the
1019         "reserved0" mode.
1020
1021 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1022
1023         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1024         specifier.  Add entries for VLDR and VSTR of system registers.
1025         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1026         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1027         of %J and %K format specifier.
1028
1029 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1030
1031         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1032         Add new entries for VSCCLRM instruction.
1033         (print_insn_coprocessor): Handle new %C format control code.
1034
1035 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1036
1037         * arm-dis.c (enum isa): New enum.
1038         (struct sopcode32): New structure.
1039         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1040         set isa field of all current entries to ANY.
1041         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1042         Only match an entry if its isa field allows the current mode.
1043
1044 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1045
1046         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1047         CLRM.
1048         (print_insn_thumb32): Add logic to print %n CLRM register list.
1049
1050 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1051
1052         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1053         and %Q patterns.
1054
1055 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1056
1057         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1058         (print_insn_thumb32): Edit the switch case for %Z.
1059
1060 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1061
1062         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1063
1064 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1065
1066         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1067
1068 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1069
1070         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1071
1072 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1073
1074         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1075         Arm register with r13 and r15 unpredictable.
1076         (thumb32_opcodes): New instructions for bfx and bflx.
1077
1078 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1079
1080         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1081
1082 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1083
1084         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1085
1086 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1087
1088         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1089
1090 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1091
1092         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1093
1094 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1095
1096         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1097         "optr". ("operator" is a reserved word in c++).
1098
1099 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1100
1101         * aarch64-opc.c (aarch64_print_operand): Add case for
1102         AARCH64_OPND_Rt_SP.
1103         (verify_constraints): Likewise.
1104         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1105         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1106         to accept Rt|SP as first operand.
1107         (AARCH64_OPERANDS): Add new Rt_SP.
1108         * aarch64-asm-2.c: Regenerated.
1109         * aarch64-dis-2.c: Regenerated.
1110         * aarch64-opc-2.c: Regenerated.
1111
1112 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1113
1114         * aarch64-asm-2.c: Regenerated.
1115         * aarch64-dis-2.c: Likewise.
1116         * aarch64-opc-2.c: Likewise.
1117         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1118
1119 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1120
1121         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1122
1123 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1124
1125         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1126         * i386-init.h: Regenerated.
1127
1128 2019-04-07  Alan Modra  <amodra@gmail.com>
1129
1130         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1131         op_separator to control printing of spaces, comma and parens
1132         rather than need_comma, need_paren and spaces vars.
1133
1134 2019-04-07  Alan Modra  <amodra@gmail.com>
1135
1136         PR 24421
1137         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1138         (print_insn_neon, print_insn_arm): Likewise.
1139
1140 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1141
1142         * i386-dis-evex.h (evex_table): Updated to support BF16
1143         instructions.
1144         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1145         and EVEX_W_0F3872_P_3.
1146         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1147         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1148         * i386-opc.h (enum): Add CpuAVX512_BF16.
1149         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1150         * i386-opc.tbl: Add AVX512 BF16 instructions.
1151         * i386-init.h: Regenerated.
1152         * i386-tbl.h: Likewise.
1153
1154 2019-04-05  Alan Modra  <amodra@gmail.com>
1155
1156         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1157         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1158         to favour printing of "-" branch hint when using the "y" bit.
1159         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1160
1161 2019-04-05  Alan Modra  <amodra@gmail.com>
1162
1163         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1164         opcode until first operand is output.
1165
1166 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1167
1168         PR gas/24349
1169         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1170         (valid_bo_post_v2): Add support for 'at' branch hints.
1171         (insert_bo): Only error on branch on ctr.
1172         (get_bo_hint_mask): New function.
1173         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1174         for inserting 'at' branch hints.
1175         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1176         for extracting 'at' branch hints.
1177         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1178         (BOE): Delete operand.
1179         (BOM, BOP): New operands.
1180         (RM): Update value.
1181         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1182         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1183         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1184         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1185         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1186         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1187         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1188         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1189         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1190         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1191         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1192         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1193         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1194         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1195         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1196         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1197         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1198         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1199         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1200         bttarl+>: New extended mnemonics.
1201
1202 2019-03-28  Alan Modra  <amodra@gmail.com>
1203
1204         PR 24390
1205         * ppc-opc.c (BTF): Define.
1206         (powerpc_opcodes): Use for mtfsb*.
1207         * ppc-dis.c (print_insn_powerpc): Print fields with both
1208         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1209
1210 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1211
1212         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1213         (mapping_symbol_for_insn): Implement new algorithm.
1214         (print_insn): Remove duplicate code.
1215
1216 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1217
1218         * aarch64-dis.c (print_insn_aarch64):
1219         Implement override.
1220
1221 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1222
1223         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1224         order.
1225
1226 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1227
1228         * aarch64-dis.c (last_stop_offset): New.
1229         (print_insn_aarch64): Use stop_offset.
1230
1231 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1232
1233         PR gas/24359
1234         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1235         CPU_ANY_AVX2_FLAGS.
1236         * i386-init.h: Regenerated.
1237
1238 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1239
1240         PR gas/24348
1241         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1242         vmovdqu16, vmovdqu32 and vmovdqu64.
1243         * i386-tbl.h: Regenerated.
1244
1245 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1246
1247         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1248         from vstrszb, vstrszh, and vstrszf.
1249
1250 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1251
1252         * s390-opc.txt: Add instruction descriptions.
1253
1254 2019-02-08  Jim Wilson  <jimw@sifive.com>
1255
1256         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1257         <bne>: Likewise.
1258
1259 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1260
1261         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1262
1263 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1264
1265         PR binutils/23212
1266         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1267         * aarch64-opc.c (verify_elem_sd): New.
1268         (fields): Add FLD_sz entr.
1269         * aarch64-tbl.h (_SIMD_INSN): New.
1270         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1271         fmulx scalar and vector by element isns.
1272
1273 2019-02-07  Nick Clifton  <nickc@redhat.com>
1274
1275         * po/sv.po: Updated Swedish translation.
1276
1277 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1278
1279         * s390-mkopc.c (main): Accept arch13 as cpu string.
1280         * s390-opc.c: Add new instruction formats and instruction opcode
1281         masks.
1282         * s390-opc.txt: Add new arch13 instructions.
1283
1284 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1285
1286         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1287         (aarch64_opcode): Change encoding for stg, stzg
1288         st2g and st2zg.
1289         * aarch64-asm-2.c: Regenerated.
1290         * aarch64-dis-2.c: Regenerated.
1291         * aarch64-opc-2.c: Regenerated.
1292
1293 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1294
1295         * aarch64-asm-2.c: Regenerated.
1296         * aarch64-dis-2.c: Likewise.
1297         * aarch64-opc-2.c: Likewise.
1298         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1299
1300 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1301             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1302
1303         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1304         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1305         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1306         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1307         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1308         case for ldstgv_indexed.
1309         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1310         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1311         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1312         * aarch64-asm-2.c: Regenerated.
1313         * aarch64-dis-2.c: Regenerated.
1314         * aarch64-opc-2.c: Regenerated.
1315
1316 2019-01-23  Nick Clifton  <nickc@redhat.com>
1317
1318         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1319
1320 2019-01-21  Nick Clifton  <nickc@redhat.com>
1321
1322         * po/de.po: Updated German translation.
1323         * po/uk.po: Updated Ukranian translation.
1324
1325 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1326         * mips-dis.c (mips_arch_choices): Fix typo in
1327         gs464, gs464e and gs264e descriptors.
1328
1329 2019-01-19  Nick Clifton  <nickc@redhat.com>
1330
1331         * configure: Regenerate.
1332         * po/opcodes.pot: Regenerate.
1333
1334 2018-06-24  Nick Clifton  <nickc@redhat.com>
1335
1336         2.32 branch created.
1337
1338 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1339
1340         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1341         if it is null.
1342         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1343         zero.
1344
1345 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1346
1347         * configure: Regenerate.
1348
1349 2019-01-07  Alan Modra  <amodra@gmail.com>
1350
1351         * configure: Regenerate.
1352         * po/POTFILES.in: Regenerate.
1353
1354 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1355
1356         * s12z-opc.c: New file.
1357         * s12z-opc.h: New file.
1358         * s12z-dis.c: Removed all code not directly related to display
1359         of instructions.  Used the interface provided by the new files
1360         instead.
1361         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1362         * Makefile.in: Regenerate.
1363         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1364         * configure: Regenerate.
1365
1366 2019-01-01  Alan Modra  <amodra@gmail.com>
1367
1368         Update year range in copyright notice of all files.
1369
1370 For older changes see ChangeLog-2018
1371 \f
1372 Copyright (C) 2019 Free Software Foundation, Inc.
1373
1374 Copying and distribution of this file, with or without modification,
1375 are permitted in any medium without royalty provided the copyright
1376 notice and this notice are preserved.
1377
1378 Local Variables:
1379 mode: change-log
1380 left-margin: 8
1381 fill-column: 74
1382 version-control: never
1383 End: