1 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2 Michael Collison <michael.collison@arm.com>
4 * arm-dis.c (enum mve_instructions): Add new instructions.
5 (enum mve_unpredictable): Add new reasons.
6 (is_mve_encoding_conflict): Handle new instructions.
7 (is_mve_unpredictable): Likewise.
8 (mve_opcodes): Add new instructions.
9 (print_mve_unpredictable): Handle new reasons.
10 (print_mve_register_blocks): New print function.
11 (print_mve_size): Handle new instructions.
12 (print_insn_mve): Likewise.
14 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
15 Michael Collison <michael.collison@arm.com>
17 * arm-dis.c (enum mve_instructions): Add new instructions.
18 (enum mve_unpredictable): Add new reasons.
19 (enum mve_undefined): Likewise.
20 (is_mve_encoding_conflict): Handle new instructions.
21 (is_mve_undefined): Likewise.
22 (is_mve_unpredictable): Likewise.
23 (coprocessor_opcodes): Move NEON VDUP from here...
24 (neon_opcodes): ... to here.
25 (mve_opcodes): Add new instructions.
26 (print_mve_undefined): Handle new reasons.
27 (print_mve_unpredictable): Likewise.
28 (print_mve_size): Handle new instructions.
29 (print_insn_neon): Handle vdup.
30 (print_insn_mve): Handle new operands.
32 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
33 Michael Collison <michael.collison@arm.com>
35 * arm-dis.c (enum mve_instructions): Add new instructions.
36 (enum mve_unpredictable): Add new values.
37 (mve_opcodes): Add new instructions.
38 (vec_condnames): New array with vector conditions.
39 (mve_predicatenames): New array with predicate suffixes.
40 (mve_vec_sizename): New array with vector sizes.
41 (enum vpt_pred_state): New enum with vector predication states.
42 (struct vpt_block): New struct type for vpt blocks.
43 (vpt_block_state): Global struct to keep track of state.
44 (mve_extract_pred_mask): New helper function.
45 (num_instructions_vpt_block): Likewise.
46 (mark_outside_vpt_block): Likewise.
47 (mark_inside_vpt_block): Likewise.
48 (invert_next_predicate_state): Likewise.
49 (update_next_predicate_state): Likewise.
50 (update_vpt_block_state): Likewise.
51 (is_vpt_instruction): Likewise.
52 (is_mve_encoding_conflict): Add entries for new instructions.
53 (is_mve_unpredictable): Likewise.
54 (print_mve_unpredictable): Handle new cases.
55 (print_instruction_predicate): Likewise.
56 (print_mve_size): New function.
57 (print_vec_condition): New function.
58 (print_insn_mve): Handle vpt blocks and new print operands.
60 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
62 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
63 8, 14 and 15 for Armv8.1-M Mainline.
65 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
66 Michael Collison <michael.collison@arm.com>
68 * arm-dis.c (enum mve_instructions): New enum.
69 (enum mve_unpredictable): Likewise.
70 (enum mve_undefined): Likewise.
71 (struct mopcode32): New struct.
72 (is_mve_okay_in_it): New function.
73 (is_mve_architecture): Likewise.
74 (arm_decode_field): Likewise.
75 (arm_decode_field_multiple): Likewise.
76 (is_mve_encoding_conflict): Likewise.
77 (is_mve_undefined): Likewise.
78 (is_mve_unpredictable): Likewise.
79 (print_mve_undefined): Likewise.
80 (print_mve_unpredictable): Likewise.
81 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
82 (print_insn_mve): New function.
83 (print_insn_thumb32): Handle MVE architecture.
84 (select_arm_features): Force thumb for Armv8.1-m Mainline.
86 2019-05-10 Nick Clifton <nickc@redhat.com>
89 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
90 end of the table prematurely.
92 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
94 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
97 2019-05-11 Alan Modra <amodra@gmail.com>
99 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
100 when -Mraw is in effect.
102 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
104 * aarch64-dis-2.c: Regenerate.
105 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
106 (OP_SVE_BBB): New variant set.
107 (OP_SVE_DDDD): New variant set.
108 (OP_SVE_HHH): New variant set.
109 (OP_SVE_HHHU): New variant set.
110 (OP_SVE_SSS): New variant set.
111 (OP_SVE_SSSU): New variant set.
112 (OP_SVE_SHH): New variant set.
113 (OP_SVE_SBBU): New variant set.
114 (OP_SVE_DSS): New variant set.
115 (OP_SVE_DHHU): New variant set.
116 (OP_SVE_VMV_HSD_BHS): New variant set.
117 (OP_SVE_VVU_HSD_BHS): New variant set.
118 (OP_SVE_VVVU_SD_BH): New variant set.
119 (OP_SVE_VVVU_BHSD): New variant set.
120 (OP_SVE_VVV_QHD_DBS): New variant set.
121 (OP_SVE_VVV_HSD_BHS): New variant set.
122 (OP_SVE_VVV_HSD_BHS2): New variant set.
123 (OP_SVE_VVV_BHS_HSD): New variant set.
124 (OP_SVE_VV_BHS_HSD): New variant set.
125 (OP_SVE_VVV_SD): New variant set.
126 (OP_SVE_VVU_BHS_HSD): New variant set.
127 (OP_SVE_VZVV_SD): New variant set.
128 (OP_SVE_VZVV_BH): New variant set.
129 (OP_SVE_VZV_SD): New variant set.
130 (aarch64_opcode_table): Add sve2 instructions.
132 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
134 * aarch64-asm-2.c: Regenerated.
135 * aarch64-dis-2.c: Regenerated.
136 * aarch64-opc-2.c: Regenerated.
137 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
138 for SVE_SHLIMM_UNPRED_22.
139 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
140 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
143 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
145 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
146 sve_size_tsz_bhs iclass encode.
147 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
148 sve_size_tsz_bhs iclass decode.
150 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
152 * aarch64-asm-2.c: Regenerated.
153 * aarch64-dis-2.c: Regenerated.
154 * aarch64-opc-2.c: Regenerated.
155 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
156 for SVE_Zm4_11_INDEX.
157 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
158 (fields): Handle SVE_i2h field.
159 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
160 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
162 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
164 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
165 sve_shift_tsz_bhsd iclass encode.
166 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
167 sve_shift_tsz_bhsd iclass decode.
169 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
171 * aarch64-asm-2.c: Regenerated.
172 * aarch64-dis-2.c: Regenerated.
173 * aarch64-opc-2.c: Regenerated.
174 * aarch64-asm.c (aarch64_ins_sve_shrimm):
175 (aarch64_encode_variant_using_iclass): Handle
176 sve_shift_tsz_hsd iclass encode.
177 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
178 sve_shift_tsz_hsd iclass decode.
179 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
180 for SVE_SHRIMM_UNPRED_22.
181 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
182 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
185 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
187 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
188 sve_size_013 iclass encode.
189 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
190 sve_size_013 iclass decode.
192 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
194 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
195 sve_size_bh iclass encode.
196 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
197 sve_size_bh iclass decode.
199 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
201 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
202 sve_size_sd2 iclass encode.
203 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
204 sve_size_sd2 iclass decode.
205 * aarch64-opc.c (fields): Handle SVE_sz2 field.
206 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
208 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
210 * aarch64-asm-2.c: Regenerated.
211 * aarch64-dis-2.c: Regenerated.
212 * aarch64-opc-2.c: Regenerated.
213 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
215 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
216 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
218 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
220 * aarch64-asm-2.c: Regenerated.
221 * aarch64-dis-2.c: Regenerated.
222 * aarch64-opc-2.c: Regenerated.
223 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
224 for SVE_Zm3_11_INDEX.
225 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
226 (fields): Handle SVE_i3l and SVE_i3h2 fields.
227 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
229 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
231 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
233 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
234 sve_size_hsd2 iclass encode.
235 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
236 sve_size_hsd2 iclass decode.
237 * aarch64-opc.c (fields): Handle SVE_size field.
238 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
240 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
242 * aarch64-asm-2.c: Regenerated.
243 * aarch64-dis-2.c: Regenerated.
244 * aarch64-opc-2.c: Regenerated.
245 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
247 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
248 (fields): Handle SVE_rot3 field.
249 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
250 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
252 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
254 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
257 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
260 (aarch64_feature_sve2, aarch64_feature_sve2aes,
261 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
262 aarch64_feature_sve2bitperm): New feature sets.
263 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
264 for feature set addresses.
265 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
266 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
268 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
269 Faraz Shahbazker <fshahbazker@wavecomp.com>
271 * mips-dis.c (mips_calculate_combination_ases): Add ISA
272 argument and set ASE_EVA_R6 appropriately.
273 (set_default_mips_dis_options): Pass ISA to above.
274 (parse_mips_dis_option): Likewise.
275 * mips-opc.c (EVAR6): New macro.
276 (mips_builtin_opcodes): Add llwpe, scwpe.
278 2019-05-01 Sudakshina Das <sudi.das@arm.com>
280 * aarch64-asm-2.c: Regenerated.
281 * aarch64-dis-2.c: Regenerated.
282 * aarch64-opc-2.c: Regenerated.
283 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
284 AARCH64_OPND_TME_UIMM16.
285 (aarch64_print_operand): Likewise.
286 * aarch64-tbl.h (QL_IMM_NIL): New.
289 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
291 2019-04-29 John Darrington <john@darrington.wattle.id.au>
293 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
295 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
296 Faraz Shahbazker <fshahbazker@wavecomp.com>
298 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
300 2019-04-24 John Darrington <john@darrington.wattle.id.au>
302 * s12z-opc.h: Add extern "C" bracketing to help
303 users who wish to use this interface in c++ code.
305 2019-04-24 John Darrington <john@darrington.wattle.id.au>
307 * s12z-opc.c (bm_decode): Handle bit map operations with the
310 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
312 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
313 specifier. Add entries for VLDR and VSTR of system registers.
314 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
315 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
316 of %J and %K format specifier.
318 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
320 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
321 Add new entries for VSCCLRM instruction.
322 (print_insn_coprocessor): Handle new %C format control code.
324 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
326 * arm-dis.c (enum isa): New enum.
327 (struct sopcode32): New structure.
328 (coprocessor_opcodes): change type of entries to struct sopcode32 and
329 set isa field of all current entries to ANY.
330 (print_insn_coprocessor): Change type of insn to struct sopcode32.
331 Only match an entry if its isa field allows the current mode.
333 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
335 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
337 (print_insn_thumb32): Add logic to print %n CLRM register list.
339 2019-04-15 Sudakshina Das <sudi.das@arm.com>
341 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
344 2019-04-15 Sudakshina Das <sudi.das@arm.com>
346 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
347 (print_insn_thumb32): Edit the switch case for %Z.
349 2019-04-15 Sudakshina Das <sudi.das@arm.com>
351 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
353 2019-04-15 Sudakshina Das <sudi.das@arm.com>
355 * arm-dis.c (thumb32_opcodes): New instruction bfl.
357 2019-04-15 Sudakshina Das <sudi.das@arm.com>
359 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
361 2019-04-15 Sudakshina Das <sudi.das@arm.com>
363 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
364 Arm register with r13 and r15 unpredictable.
365 (thumb32_opcodes): New instructions for bfx and bflx.
367 2019-04-15 Sudakshina Das <sudi.das@arm.com>
369 * arm-dis.c (thumb32_opcodes): New instructions for bf.
371 2019-04-15 Sudakshina Das <sudi.das@arm.com>
373 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
375 2019-04-15 Sudakshina Das <sudi.das@arm.com>
377 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
379 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
381 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
383 2019-04-12 John Darrington <john@darrington.wattle.id.au>
385 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
386 "optr". ("operator" is a reserved word in c++).
388 2019-04-11 Sudakshina Das <sudi.das@arm.com>
390 * aarch64-opc.c (aarch64_print_operand): Add case for
392 (verify_constraints): Likewise.
393 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
394 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
395 to accept Rt|SP as first operand.
396 (AARCH64_OPERANDS): Add new Rt_SP.
397 * aarch64-asm-2.c: Regenerated.
398 * aarch64-dis-2.c: Regenerated.
399 * aarch64-opc-2.c: Regenerated.
401 2019-04-11 Sudakshina Das <sudi.das@arm.com>
403 * aarch64-asm-2.c: Regenerated.
404 * aarch64-dis-2.c: Likewise.
405 * aarch64-opc-2.c: Likewise.
406 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
408 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
410 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
412 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
414 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
415 * i386-init.h: Regenerated.
417 2019-04-07 Alan Modra <amodra@gmail.com>
419 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
420 op_separator to control printing of spaces, comma and parens
421 rather than need_comma, need_paren and spaces vars.
423 2019-04-07 Alan Modra <amodra@gmail.com>
426 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
427 (print_insn_neon, print_insn_arm): Likewise.
429 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
431 * i386-dis-evex.h (evex_table): Updated to support BF16
433 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
434 and EVEX_W_0F3872_P_3.
435 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
436 (cpu_flags): Add bitfield for CpuAVX512_BF16.
437 * i386-opc.h (enum): Add CpuAVX512_BF16.
438 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
439 * i386-opc.tbl: Add AVX512 BF16 instructions.
440 * i386-init.h: Regenerated.
441 * i386-tbl.h: Likewise.
443 2019-04-05 Alan Modra <amodra@gmail.com>
445 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
446 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
447 to favour printing of "-" branch hint when using the "y" bit.
448 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
450 2019-04-05 Alan Modra <amodra@gmail.com>
452 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
453 opcode until first operand is output.
455 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
458 * ppc-opc.c (valid_bo_pre_v2): Add comments.
459 (valid_bo_post_v2): Add support for 'at' branch hints.
460 (insert_bo): Only error on branch on ctr.
461 (get_bo_hint_mask): New function.
462 (insert_boe): Add new 'branch_taken' formal argument. Add support
463 for inserting 'at' branch hints.
464 (extract_boe): Add new 'branch_taken' formal argument. Add support
465 for extracting 'at' branch hints.
466 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
467 (BOE): Delete operand.
468 (BOM, BOP): New operands.
470 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
471 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
472 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
473 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
474 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
475 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
476 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
477 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
478 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
479 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
480 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
481 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
482 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
483 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
484 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
485 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
486 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
487 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
488 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
489 bttarl+>: New extended mnemonics.
491 2019-03-28 Alan Modra <amodra@gmail.com>
494 * ppc-opc.c (BTF): Define.
495 (powerpc_opcodes): Use for mtfsb*.
496 * ppc-dis.c (print_insn_powerpc): Print fields with both
497 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
499 2019-03-25 Tamar Christina <tamar.christina@arm.com>
501 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
502 (mapping_symbol_for_insn): Implement new algorithm.
503 (print_insn): Remove duplicate code.
505 2019-03-25 Tamar Christina <tamar.christina@arm.com>
507 * aarch64-dis.c (print_insn_aarch64):
510 2019-03-25 Tamar Christina <tamar.christina@arm.com>
512 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
515 2019-03-25 Tamar Christina <tamar.christina@arm.com>
517 * aarch64-dis.c (last_stop_offset): New.
518 (print_insn_aarch64): Use stop_offset.
520 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
523 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
525 * i386-init.h: Regenerated.
527 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
530 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
531 vmovdqu16, vmovdqu32 and vmovdqu64.
532 * i386-tbl.h: Regenerated.
534 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
536 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
537 from vstrszb, vstrszh, and vstrszf.
539 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
541 * s390-opc.txt: Add instruction descriptions.
543 2019-02-08 Jim Wilson <jimw@sifive.com>
545 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
548 2019-02-07 Tamar Christina <tamar.christina@arm.com>
550 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
552 2019-02-07 Tamar Christina <tamar.christina@arm.com>
555 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
556 * aarch64-opc.c (verify_elem_sd): New.
557 (fields): Add FLD_sz entr.
558 * aarch64-tbl.h (_SIMD_INSN): New.
559 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
560 fmulx scalar and vector by element isns.
562 2019-02-07 Nick Clifton <nickc@redhat.com>
564 * po/sv.po: Updated Swedish translation.
566 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
568 * s390-mkopc.c (main): Accept arch13 as cpu string.
569 * s390-opc.c: Add new instruction formats and instruction opcode
571 * s390-opc.txt: Add new arch13 instructions.
573 2019-01-25 Sudakshina Das <sudi.das@arm.com>
575 * aarch64-tbl.h (QL_LDST_AT): Update macro.
576 (aarch64_opcode): Change encoding for stg, stzg
578 * aarch64-asm-2.c: Regenerated.
579 * aarch64-dis-2.c: Regenerated.
580 * aarch64-opc-2.c: Regenerated.
582 2019-01-25 Sudakshina Das <sudi.das@arm.com>
584 * aarch64-asm-2.c: Regenerated.
585 * aarch64-dis-2.c: Likewise.
586 * aarch64-opc-2.c: Likewise.
587 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
589 2019-01-25 Sudakshina Das <sudi.das@arm.com>
590 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
592 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
593 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
594 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
595 * aarch64-dis.h (ext_addr_simple_2): Likewise.
596 * aarch64-opc.c (operand_general_constraint_met_p): Remove
597 case for ldstgv_indexed.
598 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
599 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
600 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
601 * aarch64-asm-2.c: Regenerated.
602 * aarch64-dis-2.c: Regenerated.
603 * aarch64-opc-2.c: Regenerated.
605 2019-01-23 Nick Clifton <nickc@redhat.com>
607 * po/pt_BR.po: Updated Brazilian Portuguese translation.
609 2019-01-21 Nick Clifton <nickc@redhat.com>
611 * po/de.po: Updated German translation.
612 * po/uk.po: Updated Ukranian translation.
614 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
615 * mips-dis.c (mips_arch_choices): Fix typo in
616 gs464, gs464e and gs264e descriptors.
618 2019-01-19 Nick Clifton <nickc@redhat.com>
620 * configure: Regenerate.
621 * po/opcodes.pot: Regenerate.
623 2018-06-24 Nick Clifton <nickc@redhat.com>
627 2019-01-09 John Darrington <john@darrington.wattle.id.au>
629 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
631 -dis.c (opr_emit_disassembly): Do not omit an index if it is
634 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
636 * configure: Regenerate.
638 2019-01-07 Alan Modra <amodra@gmail.com>
640 * configure: Regenerate.
641 * po/POTFILES.in: Regenerate.
643 2019-01-03 John Darrington <john@darrington.wattle.id.au>
645 * s12z-opc.c: New file.
646 * s12z-opc.h: New file.
647 * s12z-dis.c: Removed all code not directly related to display
648 of instructions. Used the interface provided by the new files
650 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
651 * Makefile.in: Regenerate.
652 * configure.ac (bfd_s12z_arch): Correct the dependencies.
653 * configure: Regenerate.
655 2019-01-01 Alan Modra <amodra@gmail.com>
657 Update year range in copyright notice of all files.
659 For older changes see ChangeLog-2018
661 Copyright (C) 2019 Free Software Foundation, Inc.
663 Copying and distribution of this file, with or without modification,
664 are permitted in any medium without royalty provided the copyright
665 notice and this notice are preserved.
671 version-control: never