1 2019-12-26 Alan Modra <amodra@gmail.com>
3 * crx-dis.c (get_number_of_operands): Don't access operands[]
6 2019-12-26 Alan Modra <amodra@gmail.com>
8 * v850-dis.c (disassemble): Avoid signed overflow. Don't use
9 long vars when unsigned int will do.
11 2019-12-24 Alan Modra <amodra@gmail.com>
13 * arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
15 2019-12-23 Jan Beulich <jbeulich@suse.com>
17 * ppc-dis.c (print_insn_powerpc): Rename local variable "spaces"
19 * ppc-opc.c (D34, SI34, NSI34): Use UINT64_C().
21 2019-12-23 Alan Modra <amodra@gmail.com>
23 * score-dis.c (print_insn_score32): Avoid signed overflow.
24 (print_insn_score48): Likewise. Don't cast to int when printing
27 2019-12-23 Alan Modra <amodra@gmail.com>
29 * iq2000-ibld.c: Regenerate.
31 2019-12-23 Alan Modra <amodra@gmail.com>
33 * d30v-dis.c (extract_value): Make num param a uint64_t, constify
34 oper. Use unsigned vars.
35 (print_insn): Make num var uint64_t. Constify oper and remove now
36 unnecessary casts on extract_value calls.
37 (print_insn_d30v): Use unsigned vars. Adjust printf formats.
39 2019-12-23 Alan Modra <amodra@gmail.com>
41 * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
42 Catch value overflow. Sign extend only on terminating byte.
44 2019-12-20 Alan Modra <amodra@gmail.com>
47 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
48 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word
49 printed. Print .word in more cases.
51 2019-12-20 Alan Modra <amodra@gmail.com>
53 * or1k-ibld.c: Regenerate.
55 2019-12-20 Alan Modra <amodra@gmail.com>
57 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
60 2019-12-20 Alan Modra <amodra@gmail.com>
62 * m68hc11-dis.c (read_memory): Delete forward decls.
63 (print_indexed_operand, print_insn): Likewise.
64 (print_indexed_operand): Formatting. Don't rely on short being
65 exactly 16 bits, make sign extension explicit.
66 (print_insn): Likewise. Avoid signed overflow.
68 2019-12-19 Alan Modra <amodra@gmail.com>
70 * vax-dis.c (print_insn_mode): Stop index mode recursion.
72 2019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
75 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
77 * microblaze-opc.h (opcodes): Adjust to suit.
79 2019-12-18 Alan Modra <amodra@gmail.com>
81 * alpha-opc.c (OP): Avoid signed overflow.
82 * arm-dis.c (print_insn): Likewise.
83 * mcore-dis.c (print_insn_mcore): Likewise.
84 * pj-dis.c (get_int): Likewise.
85 * ppc-opc.c (EBD15, EBD15BI): Likewise.
86 * score7-dis.c (s7_print_insn): Likewise.
87 * tic30-dis.c (print_insn_tic30): Likewise.
88 * v850-opc.c (insert_SELID): Likewise.
89 * vax-dis.c (print_insn_vax): Likewise.
90 * arc-ext.c (create_map): Likewise.
91 (struct ExtAuxRegister): Make "address" field unsigned int.
92 (arcExtMap_auxRegName): Pass unsigned address.
93 (dump_ARC_extmap): Adjust.
94 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
96 2019-12-17 Alan Modra <amodra@gmail.com>
98 * visium-dis.c (print_insn_visium): Avoid signed overflow.
100 2019-12-17 Alan Modra <amodra@gmail.com>
102 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
103 (value_fit_unsigned_field_p): Likewise.
104 (aarch64_wide_constant_p): Likewise.
105 (operand_general_constraint_met_p): Likewise.
106 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
108 2019-12-17 Alan Modra <amodra@gmail.com>
110 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
111 (print_insn_nds32): Use uint64_t for "given" and "given1".
113 2019-12-17 Alan Modra <amodra@gmail.com>
115 * tic80-dis.c: Delete file.
116 * tic80-opc.c: Delete file.
117 * disassemble.c: Remove tic80 support.
118 * disassemble.h: Likewise.
119 * Makefile.am: Likewise.
120 * configure.ac: Likewise.
121 * Makefile.in: Regenerate.
122 * configure: Regenerate.
123 * po/POTFILES.in: Regenerate.
125 2019-12-17 Alan Modra <amodra@gmail.com>
127 * bpf-ibld.c: Regenerate.
129 2019-12-16 Alan Modra <amodra@gmail.com>
131 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
133 (aarch64_ext_imm): Avoid signed overflow.
135 2019-12-16 Alan Modra <amodra@gmail.com>
137 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
139 2019-12-16 Alan Modra <amodra@gmail.com>
141 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
143 2019-12-16 Alan Modra <amodra@gmail.com>
145 * xstormy16-ibld.c: Regenerate.
147 2019-12-16 Alan Modra <amodra@gmail.com>
149 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
150 value adjustment so that it doesn't affect reg field too.
152 2019-12-16 Alan Modra <amodra@gmail.com>
154 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
155 (get_number_of_operands, getargtype, getbits, getregname),
156 (getcopregname, getprocregname, gettrapstring, getcinvstring),
157 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
158 (powerof2, match_opcode, make_instruction, print_arguments),
159 (print_arg): Delete forward declarations, moving static to..
160 (getregname, getcopregname, getregliststring): ..these definitions.
161 (build_mask): Return unsigned int mask.
162 (match_opcode): Use unsigned int vars.
164 2019-12-16 Alan Modra <amodra@gmail.com>
166 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
168 2019-12-16 Alan Modra <amodra@gmail.com>
170 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
171 (struct objdump_disasm_info): Delete.
172 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
173 N32_IMMS to unsigned before shifting left.
175 2019-12-16 Alan Modra <amodra@gmail.com>
177 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
178 (print_insn_moxie): Remove unnecessary cast.
180 2019-12-12 Alan Modra <amodra@gmail.com>
182 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
185 2019-12-11 Alan Modra <amodra@gmail.com>
187 * arc-dis.c (BITS): Don't truncate high bits with shifts.
188 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
189 * tic54x-dis.c (print_instruction): Likewise.
190 * tilegx-opc.c (parse_insn_tilegx): Likewise.
191 * tilepro-opc.c (parse_insn_tilepro): Likewise.
192 * visium-dis.c (disassem_class0): Likewise.
193 * pdp11-dis.c (sign_extend): Likewise.
195 * epiphany-ibld.c: Regenerate.
196 * lm32-ibld.c: Regenerate.
197 * m32c-ibld.c: Regenerate.
199 2019-12-11 Alan Modra <amodra@gmail.com>
201 * ns32k-dis.c (sign_extend): Correct last patch.
203 2019-12-11 Alan Modra <amodra@gmail.com>
205 * vax-dis.c (NEXTLONG): Avoid signed overflow.
207 2019-12-11 Alan Modra <amodra@gmail.com>
209 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
210 sign extend using shifts.
212 2019-12-11 Alan Modra <amodra@gmail.com>
214 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
216 2019-12-11 Alan Modra <amodra@gmail.com>
218 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
219 on NULL registertable entry.
220 (tic4x_hash_opcode): Use unsigned arithmetic.
222 2019-12-11 Alan Modra <amodra@gmail.com>
224 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
226 2019-12-11 Alan Modra <amodra@gmail.com>
228 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
229 (bit_extract_simple, sign_extend): Likewise.
231 2019-12-11 Alan Modra <amodra@gmail.com>
233 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
235 2019-12-11 Alan Modra <amodra@gmail.com>
237 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
239 2019-12-11 Alan Modra <amodra@gmail.com>
241 * m68k-dis.c (COERCE32): Cast value first.
242 (NEXTLONG, NEXTULONG): Avoid signed overflow.
244 2019-12-11 Alan Modra <amodra@gmail.com>
246 * h8300-dis.c (extract_immediate): Avoid signed overflow.
247 (bfd_h8_disassemble): Likewise.
249 2019-12-11 Alan Modra <amodra@gmail.com>
251 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
252 past end of operands array.
254 2019-12-11 Alan Modra <amodra@gmail.com>
256 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
257 overflow when collecting bytes of a number.
259 2019-12-11 Alan Modra <amodra@gmail.com>
261 * cris-dis.c (print_with_operands): Avoid signed integer
262 overflow when collecting bytes of a 32-bit integer.
264 2019-12-11 Alan Modra <amodra@gmail.com>
266 * cr16-dis.c (EXTRACT, SBM): Rewrite.
267 (cr16_match_opcode): Delete duplicate bcond test.
269 2019-12-11 Alan Modra <amodra@gmail.com>
271 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
273 (MASKBITS, SIGNEXTEND): Rewrite.
274 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
275 unsigned arithmetic, instead assign result of SIGNEXTEND back
277 (fmtconst_val): Use 1u in shift expression.
279 2019-12-11 Alan Modra <amodra@gmail.com>
281 * arc-dis.c (find_format_from_table): Use ull constant when
282 shifting by up to 32.
284 2019-12-11 Alan Modra <amodra@gmail.com>
287 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
288 false when field is zero for sve_size_tsz_bhs.
290 2019-12-11 Alan Modra <amodra@gmail.com>
292 * epiphany-ibld.c: Regenerate.
294 2019-12-10 Alan Modra <amodra@gmail.com>
297 * disassemble.c (disassemble_free_target): New function.
299 2019-12-10 Alan Modra <amodra@gmail.com>
301 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
302 * disassemble.c (disassemble_init_for_target): Likewise.
303 * bpf-dis.c: Regenerate.
304 * epiphany-dis.c: Regenerate.
305 * fr30-dis.c: Regenerate.
306 * frv-dis.c: Regenerate.
307 * ip2k-dis.c: Regenerate.
308 * iq2000-dis.c: Regenerate.
309 * lm32-dis.c: Regenerate.
310 * m32c-dis.c: Regenerate.
311 * m32r-dis.c: Regenerate.
312 * mep-dis.c: Regenerate.
313 * mt-dis.c: Regenerate.
314 * or1k-dis.c: Regenerate.
315 * xc16x-dis.c: Regenerate.
316 * xstormy16-dis.c: Regenerate.
318 2019-12-10 Alan Modra <amodra@gmail.com>
320 * ppc-dis.c (private): Delete variable.
321 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
322 (powerpc_init_dialect): Don't use global private.
324 2019-12-10 Alan Modra <amodra@gmail.com>
326 * s12z-opc.c: Formatting.
328 2019-12-08 Alan Modra <amodra@gmail.com>
330 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
333 2019-12-05 Jan Beulich <jbeulich@suse.com>
335 * aarch64-tbl.h (aarch64_feature_crypto,
336 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
337 CRYPTO_V8_2_INSN): Delete.
339 2019-12-05 Alan Modra <amodra@gmail.com>
342 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
343 (struct string_buf): New.
344 (strbuf): New function.
345 (get_field): Use strbuf rather than strdup of local temp.
346 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
347 (get_field_rfsl, get_field_imm15): Likewise.
348 (get_field_rd, get_field_r1, get_field_r2): Update macros.
349 (get_field_special): Likewise. Don't strcpy spr. Formatting.
350 (print_insn_microblaze): Formatting. Init and pass string_buf to
353 2019-12-04 Jan Beulich <jbeulich@suse.com>
355 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
356 * i386-tbl.h: Re-generate.
358 2019-12-04 Jan Beulich <jbeulich@suse.com>
360 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
362 2019-12-04 Jan Beulich <jbeulich@suse.com>
364 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
366 (xbegin): Drop DefaultSize.
367 * i386-tbl.h: Re-generate.
369 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
371 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
372 Change the coproc CRC conditions to use the extension
373 feature set, second word, base on ARM_EXT2_CRC.
375 2019-11-14 Jan Beulich <jbeulich@suse.com>
377 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
378 * i386-tbl.h: Re-generate.
380 2019-11-14 Jan Beulich <jbeulich@suse.com>
382 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
383 JumpInterSegment, and JumpAbsolute entries.
384 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
385 JUMP_ABSOLUTE): Define.
386 (struct i386_opcode_modifier): Extend jump field to 3 bits.
387 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
389 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
390 JumpInterSegment): Define.
391 * i386-tbl.h: Re-generate.
393 2019-11-14 Jan Beulich <jbeulich@suse.com>
395 * i386-gen.c (operand_type_init): Remove
396 OPERAND_TYPE_JUMPABSOLUTE entry.
397 (opcode_modifiers): Add JumpAbsolute entry.
398 (operand_types): Remove JumpAbsolute entry.
399 * i386-opc.h (JumpAbsolute): Move between enums.
400 (struct i386_opcode_modifier): Add jumpabsolute field.
401 (union i386_operand_type): Remove jumpabsolute field.
402 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
403 * i386-init.h, i386-tbl.h: Re-generate.
405 2019-11-14 Jan Beulich <jbeulich@suse.com>
407 * i386-gen.c (opcode_modifiers): Add AnySize entry.
408 (operand_types): Remove AnySize entry.
409 * i386-opc.h (AnySize): Move between enums.
410 (struct i386_opcode_modifier): Add anysize field.
411 (OTUnused): Un-comment.
412 (union i386_operand_type): Remove anysize field.
413 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
414 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
415 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
417 * i386-tbl.h: Re-generate.
419 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
421 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
422 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
423 use the floating point register (FPR).
425 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
427 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
429 (is_mve_encoding_conflict): Update cmode conflict checks for
432 2019-11-12 Jan Beulich <jbeulich@suse.com>
434 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
436 (operand_types): Remove EsSeg entry.
437 (main): Replace stale use of OTMax.
438 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
439 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
441 (OTUnused): Comment out.
442 (union i386_operand_type): Remove esseg field.
443 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
444 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
445 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
446 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
447 * i386-init.h, i386-tbl.h: Re-generate.
449 2019-11-12 Jan Beulich <jbeulich@suse.com>
451 * i386-gen.c (operand_instances): Add RegB entry.
452 * i386-opc.h (enum operand_instance): Add RegB.
453 * i386-opc.tbl (RegC, RegD, RegB): Define.
454 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
455 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
456 monitorx, mwaitx): Drop ImmExt and convert encodings
458 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
459 (edx, rdx): Add Instance=RegD.
460 (ebx, rbx): Add Instance=RegB.
461 * i386-tbl.h: Re-generate.
463 2019-11-12 Jan Beulich <jbeulich@suse.com>
465 * i386-gen.c (operand_type_init): Adjust
466 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
467 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
468 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
469 (operand_instances): New.
470 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
471 (output_operand_type): New parameter "instance". Process it.
472 (process_i386_operand_type): New local variable "instance".
473 (main): Adjust static assertions.
474 * i386-opc.h (INSTANCE_WIDTH): Define.
475 (enum operand_instance): New.
476 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
477 (union i386_operand_type): Replace acc, inoutportreg, and
478 shiftcount by instance.
479 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
480 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
482 * i386-init.h, i386-tbl.h: Re-generate.
484 2019-11-11 Jan Beulich <jbeulich@suse.com>
486 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
487 smaxp/sminp entries' "tied_operand" field to 2.
489 2019-11-11 Jan Beulich <jbeulich@suse.com>
491 * aarch64-opc.c (operand_general_constraint_met_p): Replace
492 "index" local variable by that of the already existing "num".
494 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
497 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
498 * i386-tbl.h: Regenerated.
500 2019-11-08 Jan Beulich <jbeulich@suse.com>
502 * i386-gen.c (operand_type_init): Add Class= to
503 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
504 OPERAND_TYPE_REGBND entry.
505 (operand_classes): Add RegMask and RegBND entries.
506 (operand_types): Drop RegMask and RegBND entry.
507 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
508 (RegMask, RegBND): Delete.
509 (union i386_operand_type): Remove regmask and regbnd fields.
510 * i386-opc.tbl (RegMask, RegBND): Define.
511 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
513 * i386-init.h, i386-tbl.h: Re-generate.
515 2019-11-08 Jan Beulich <jbeulich@suse.com>
517 * i386-gen.c (operand_type_init): Add Class= to
518 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
519 OPERAND_TYPE_REGZMM entries.
520 (operand_classes): Add RegMMX and RegSIMD entries.
521 (operand_types): Drop RegMMX and RegSIMD entries.
522 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
523 (RegMMX, RegSIMD): Delete.
524 (union i386_operand_type): Remove regmmx and regsimd fields.
525 * i386-opc.tbl (RegMMX): Define.
526 (RegXMM, RegYMM, RegZMM): Add Class=.
527 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
529 * i386-init.h, i386-tbl.h: Re-generate.
531 2019-11-08 Jan Beulich <jbeulich@suse.com>
533 * i386-gen.c (operand_type_init): Add Class= to
534 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
536 (operand_classes): Add RegCR, RegDR, and RegTR entries.
537 (operand_types): Drop Control, Debug, and Test entries.
538 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
539 (Control, Debug, Test): Delete.
540 (union i386_operand_type): Remove control, debug, and test
542 * i386-opc.tbl (Control, Debug, Test): Define.
543 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
544 Class=RegDR, and Test by Class=RegTR.
545 * i386-init.h, i386-tbl.h: Re-generate.
547 2019-11-08 Jan Beulich <jbeulich@suse.com>
549 * i386-gen.c (operand_type_init): Add Class= to
550 OPERAND_TYPE_SREG entry.
551 (operand_classes): Add SReg entry.
552 (operand_types): Drop SReg entry.
553 * i386-opc.h (enum operand_class): Add SReg.
555 (union i386_operand_type): Remove sreg field.
556 * i386-opc.tbl (SReg): Define.
557 * i386-reg.tbl: Replace SReg by Class=SReg.
558 * i386-init.h, i386-tbl.h: Re-generate.
560 2019-11-08 Jan Beulich <jbeulich@suse.com>
562 * i386-gen.c (operand_type_init): Add Class=. New
563 OPERAND_TYPE_ANYIMM entry.
564 (operand_classes): New.
565 (operand_types): Drop Reg entry.
566 (output_operand_type): New parameter "class". Process it.
567 (process_i386_operand_type): New local variable "class".
568 (main): Adjust static assertions.
569 * i386-opc.h (CLASS_WIDTH): Define.
570 (enum operand_class): New.
571 (Reg): Replace by Class. Adjust comment.
572 (union i386_operand_type): Replace reg by class.
573 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
575 * i386-reg.tbl: Replace Reg by Class=Reg.
576 * i386-init.h: Re-generate.
578 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
580 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
581 (aarch64_opcode_table): Add data gathering hint mnemonic.
582 * opcodes/aarch64-dis-2.c: Account for new instruction.
584 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
586 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
589 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
591 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
592 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
593 aarch64_feature_f64mm): New feature sets.
594 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
595 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
597 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
599 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
600 (OP_SVE_QQQ): New qualifier.
601 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
602 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
603 the movprfx constraint.
604 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
605 (aarch64_opcode_table): Define new instructions smmla,
606 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
608 * aarch64-opc.c (operand_general_constraint_met_p): Handle
609 AARCH64_OPND_SVE_ADDR_RI_S4x32.
610 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
611 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
612 Account for new instructions.
613 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
615 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
617 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
618 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
620 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
622 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
623 (neon_opcodes): Add bfloat SIMD instructions.
624 (print_insn_coprocessor): Add new control character %b to print
625 condition code without checking cp_num.
626 (print_insn_neon): Account for BFloat16 instructions that have no
627 special top-byte handling.
629 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
630 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
632 * arm-dis.c (print_insn_coprocessor,
633 print_insn_generic_coprocessor): Create wrapper functions around
634 the implementation of the print_insn_coprocessor control codes.
635 (print_insn_coprocessor_1): Original print_insn_coprocessor
636 function that now takes which array to look at as an argument.
637 (print_insn_arm): Use both print_insn_coprocessor and
638 print_insn_generic_coprocessor.
639 (print_insn_thumb32): As above.
641 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
642 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
644 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
645 in reglane special case.
646 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
647 aarch64_find_next_opcode): Account for new instructions.
648 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
649 in reglane special case.
650 * aarch64-opc.c (struct operand_qualifier_data): Add data for
651 new AARCH64_OPND_QLF_S_2H qualifier.
652 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
653 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
654 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
656 (BFLOAT_SVE, BFLOAT): New feature set macros.
657 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
659 (aarch64_opcode_table): Define new instructions bfdot,
660 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
663 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
664 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
666 * aarch64-tbl.h (ARMV8_6): New macro.
668 2019-11-07 Jan Beulich <jbeulich@suse.com>
670 * i386-dis.c (prefix_table): Add mcommit.
671 (rm_table): Add rdpru.
672 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
673 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
674 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
675 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
676 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
677 * i386-opc.tbl (mcommit, rdpru): New.
678 * i386-init.h, i386-tbl.h: Re-generate.
680 2019-11-07 Jan Beulich <jbeulich@suse.com>
682 * i386-dis.c (OP_Mwait): Drop local variable "names", use
684 (OP_Monitor): Drop local variable "op1_names", re-purpose
685 "names" for it instead, and replace former "names" uses by
688 2019-11-07 Jan Beulich <jbeulich@suse.com>
691 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
693 * opcodes/i386-tbl.h: Re-generate.
695 2019-11-05 Jan Beulich <jbeulich@suse.com>
697 * i386-dis.c (OP_Mwaitx): Delete.
698 (prefix_table): Use OP_Mwait for mwaitx entry.
699 (OP_Mwait): Also handle mwaitx.
701 2019-11-05 Jan Beulich <jbeulich@suse.com>
703 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
704 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
705 (prefix_table): Add respective entries.
706 (rm_table): Link to those entries.
708 2019-11-05 Jan Beulich <jbeulich@suse.com>
710 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
711 (REG_0F1C_P_0_MOD_0): ... this.
712 (REG_0F1E_MOD_3): Rename to ...
713 (REG_0F1E_P_1_MOD_3): ... this.
714 (RM_0F01_REG_5): Rename to ...
715 (RM_0F01_REG_5_MOD_3): ... this.
716 (RM_0F01_REG_7): Rename to ...
717 (RM_0F01_REG_7_MOD_3): ... this.
718 (RM_0F1E_MOD_3_REG_7): Rename to ...
719 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
720 (RM_0FAE_REG_6): Rename to ...
721 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
722 (RM_0FAE_REG_7): Rename to ...
723 (RM_0FAE_REG_7_MOD_3): ... this.
724 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
725 (PREFIX_0F01_REG_5_MOD_0): ... this.
726 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
727 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
728 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
729 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
730 (PREFIX_0FAE_REG_0): Rename to ...
731 (PREFIX_0FAE_REG_0_MOD_3): ... this.
732 (PREFIX_0FAE_REG_1): Rename to ...
733 (PREFIX_0FAE_REG_1_MOD_3): ... this.
734 (PREFIX_0FAE_REG_2): Rename to ...
735 (PREFIX_0FAE_REG_2_MOD_3): ... this.
736 (PREFIX_0FAE_REG_3): Rename to ...
737 (PREFIX_0FAE_REG_3_MOD_3): ... this.
738 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
739 (PREFIX_0FAE_REG_4_MOD_0): ... this.
740 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
741 (PREFIX_0FAE_REG_4_MOD_3): ... this.
742 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
743 (PREFIX_0FAE_REG_5_MOD_0): ... this.
744 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
745 (PREFIX_0FAE_REG_5_MOD_3): ... this.
746 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
747 (PREFIX_0FAE_REG_6_MOD_0): ... this.
748 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
749 (PREFIX_0FAE_REG_6_MOD_3): ... this.
750 (PREFIX_0FAE_REG_7): Rename to ...
751 (PREFIX_0FAE_REG_7_MOD_0): ... this.
752 (PREFIX_MOD_0_0FC3): Rename to ...
753 (PREFIX_0FC3_MOD_0): ... this.
754 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
755 (PREFIX_0FC7_REG_6_MOD_0): ... this.
756 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
757 (PREFIX_0FC7_REG_6_MOD_3): ... this.
758 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
759 (PREFIX_0FC7_REG_7_MOD_3): ... this.
760 (reg_table, prefix_table, mod_table, rm_table): Adjust
763 2019-11-04 Nick Clifton <nickc@redhat.com>
765 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
766 of a v850 system register. Move the v850_sreg_names array into
768 (get_v850_reg_name): Likewise for ordinary register names.
769 (get_v850_vreg_name): Likewise for vector register names.
770 (get_v850_cc_name): Likewise for condition codes.
771 * get_v850_float_cc_name): Likewise for floating point condition
773 (get_v850_cacheop_name): Likewise for cache-ops.
774 (get_v850_prefop_name): Likewise for pref-ops.
775 (disassemble): Use the new accessor functions.
777 2019-10-30 Delia Burduv <delia.burduv@arm.com>
779 * aarch64-opc.c (print_immediate_offset_address): Don't print the
780 immediate for the writeback form of ldraa/ldrab if it is 0.
781 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
782 * aarch64-opc-2.c: Regenerated.
784 2019-10-30 Jan Beulich <jbeulich@suse.com>
786 * i386-gen.c (operand_type_shorthands): Delete.
787 (operand_type_init): Expand previous shorthands.
788 (set_bitfield_from_shorthand): Rename back to ...
789 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
790 of operand_type_init[].
791 (set_bitfield): Adjust call to the above function.
792 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
793 RegXMM, RegYMM, RegZMM): Define.
794 * i386-reg.tbl: Expand prior shorthands.
796 2019-10-30 Jan Beulich <jbeulich@suse.com>
798 * i386-gen.c (output_i386_opcode): Change order of fields
800 * i386-opc.h (struct insn_template): Move operands field.
801 Convert extension_opcode field to unsigned short.
802 * i386-tbl.h: Re-generate.
804 2019-10-30 Jan Beulich <jbeulich@suse.com>
806 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
808 * i386-opc.h (W): Extend comment.
809 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
810 general purpose variants not allowing for byte operands.
811 * i386-tbl.h: Re-generate.
813 2019-10-29 Nick Clifton <nickc@redhat.com>
815 * tic30-dis.c (print_branch): Correct size of operand array.
817 2019-10-29 Nick Clifton <nickc@redhat.com>
819 * d30v-dis.c (print_insn): Check that operand index is valid
820 before attempting to access the operands array.
822 2019-10-29 Nick Clifton <nickc@redhat.com>
824 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
825 locating the bit to be tested.
827 2019-10-29 Nick Clifton <nickc@redhat.com>
829 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
831 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
832 (print_insn_s12z): Check for illegal size values.
834 2019-10-28 Nick Clifton <nickc@redhat.com>
836 * csky-dis.c (csky_chars_to_number): Check for a negative
837 count. Use an unsigned integer to construct the return value.
839 2019-10-28 Nick Clifton <nickc@redhat.com>
841 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
842 operand buffer. Set value to 15 not 13.
843 (get_register_operand): Use OPERAND_BUFFER_LEN.
844 (get_indirect_operand): Likewise.
845 (print_two_operand): Likewise.
846 (print_three_operand): Likewise.
847 (print_oar_insn): Likewise.
849 2019-10-28 Nick Clifton <nickc@redhat.com>
851 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
852 (bit_extract_simple): Likewise.
853 (bit_copy): Likewise.
854 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
855 index_offset array are not accessed.
857 2019-10-28 Nick Clifton <nickc@redhat.com>
859 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
862 2019-10-25 Nick Clifton <nickc@redhat.com>
864 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
865 access to opcodes.op array element.
867 2019-10-23 Nick Clifton <nickc@redhat.com>
869 * rx-dis.c (get_register_name): Fix spelling typo in error
871 (get_condition_name, get_flag_name, get_double_register_name)
872 (get_double_register_high_name, get_double_register_low_name)
873 (get_double_control_register_name, get_double_condition_name)
874 (get_opsize_name, get_size_name): Likewise.
876 2019-10-22 Nick Clifton <nickc@redhat.com>
878 * rx-dis.c (get_size_name): New function. Provides safe
879 access to name array.
880 (get_opsize_name): Likewise.
881 (print_insn_rx): Use the accessor functions.
883 2019-10-16 Nick Clifton <nickc@redhat.com>
885 * rx-dis.c (get_register_name): New function. Provides safe
886 access to name array.
887 (get_condition_name, get_flag_name, get_double_register_name)
888 (get_double_register_high_name, get_double_register_low_name)
889 (get_double_control_register_name, get_double_condition_name):
891 (print_insn_rx): Use the accessor functions.
893 2019-10-09 Nick Clifton <nickc@redhat.com>
896 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
899 2019-10-07 Jan Beulich <jbeulich@suse.com>
901 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
902 (cmpsd): Likewise. Move EsSeg to other operand.
903 * opcodes/i386-tbl.h: Re-generate.
905 2019-09-23 Alan Modra <amodra@gmail.com>
907 * m68k-dis.c: Include cpu-m68k.h
909 2019-09-23 Alan Modra <amodra@gmail.com>
911 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
912 "elf/mips.h" earlier.
914 2018-09-20 Jan Beulich <jbeulich@suse.com>
917 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
919 * i386-tbl.h: Re-generate.
921 2019-09-18 Alan Modra <amodra@gmail.com>
923 * arc-ext.c: Update throughout for bfd section macro changes.
925 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
927 * Makefile.in: Re-generate.
928 * configure: Re-generate.
930 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
932 * riscv-opc.c (riscv_opcodes): Change subset field
933 to insn_class field for all instructions.
934 (riscv_insn_types): Likewise.
936 2019-09-16 Phil Blundell <pb@pbcl.net>
938 * configure: Regenerated.
940 2019-09-10 Miod Vallat <miod@online.fr>
943 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
945 2019-09-09 Phil Blundell <pb@pbcl.net>
947 binutils 2.33 branch created.
949 2019-09-03 Nick Clifton <nickc@redhat.com>
952 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
953 greater than zero before indexing via (bufcnt -1).
955 2019-09-03 Nick Clifton <nickc@redhat.com>
958 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
959 (MAX_SPEC_REG_NAME_LEN): Define.
960 (struct mmix_dis_info): Use defined constants for array lengths.
961 (get_reg_name): New function.
962 (get_sprec_reg_name): New function.
963 (print_insn_mmix): Use new functions.
965 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
967 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
968 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
969 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
971 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
973 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
974 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
975 (aarch64_sys_reg_supported_p): Update checks for the above.
977 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
979 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
980 cases MVE_SQRSHRL and MVE_UQRSHLL.
981 (print_insn_mve): Add case for specifier 'k' to check
982 specific bit of the instruction.
984 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
987 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
988 encountering an unknown machine type.
989 (print_insn_arc): Handle arc_insn_length returning 0. In error
990 cases return -1 rather than calling abort.
992 2019-08-07 Jan Beulich <jbeulich@suse.com>
994 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
995 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
997 * i386-tbl.h: Re-generate.
999 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
1001 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
1004 2019-07-30 Mel Chen <mel.chen@sifive.com>
1006 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
1007 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
1009 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
1012 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1014 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
1015 and MPY class instructions.
1016 (parse_option): Add nps400 option.
1017 (print_arc_disassembler_options): Add nps400 info.
1019 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1021 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
1024 * arc-opc.c (RAD_CHK): Add.
1025 * arc-tbl.h: Regenerate.
1027 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1029 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1030 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1032 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
1034 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1035 instructions as UNPREDICTABLE.
1037 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1039 * bpf-desc.c: Regenerated.
1041 2019-07-17 Jan Beulich <jbeulich@suse.com>
1043 * i386-gen.c (static_assert): Define.
1045 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1046 (Opcode_Modifier_Num): ... this.
1049 2019-07-16 Jan Beulich <jbeulich@suse.com>
1051 * i386-gen.c (operand_types): Move RegMem ...
1052 (opcode_modifiers): ... here.
1053 * i386-opc.h (RegMem): Move to opcode modifer enum.
1054 (union i386_operand_type): Move regmem field ...
1055 (struct i386_opcode_modifier): ... here.
1056 * i386-opc.tbl (RegMem): Define.
1057 (mov, movq): Move RegMem on segment, control, debug, and test
1059 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1060 to non-SSE2AVX flavor.
1061 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1062 Move RegMem on register only flavors. Drop IgnoreSize from
1063 legacy encoding flavors.
1064 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1066 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1067 register only flavors.
1068 (vmovd): Move RegMem and drop IgnoreSize on register only
1069 flavor. Change opcode and operand order to store form.
1070 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1072 2019-07-16 Jan Beulich <jbeulich@suse.com>
1074 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1076 * i386-opc.h (SReg2, SReg3): Replace by ...
1078 (union i386_operand_type): Replace sreg fields.
1079 * i386-opc.tbl (mov, ): Use SReg.
1080 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1082 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1083 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1085 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1087 * bpf-desc.c: Regenerate.
1088 * bpf-opc.c: Likewise.
1089 * bpf-opc.h: Likewise.
1091 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1093 * bpf-desc.c: Regenerate.
1094 * bpf-opc.c: Likewise.
1096 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1098 * arm-dis.c (print_insn_coprocessor): Rename index to
1101 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
1103 * riscv-opc.c (riscv_insn_types): Add r4 type.
1105 * riscv-opc.c (riscv_insn_types): Add b and j type.
1107 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1108 format for sb type and correct s type.
1110 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1112 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1113 SVE FMOV alias of FCPY.
1115 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1117 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1118 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1120 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1122 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1123 registers in an instruction prefixed by MOVPRFX.
1125 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1127 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1128 sve_size_13 icode to account for variant behaviour of
1130 * aarch64-dis-2.c: Regenerate.
1131 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1132 sve_size_13 icode to account for variant behaviour of
1134 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1135 (OP_SVE_VVV_Q_D): Add new qualifier.
1136 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1137 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1140 2019-07-01 Jan Beulich <jbeulich@suse.com>
1142 * opcodes/i386-gen.c (operand_type_init): Remove
1143 OPERAND_TYPE_VEC_IMM4 entry.
1144 (operand_types): Remove Vec_Imm4.
1145 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1146 (union i386_operand_type): Remove vec_imm4.
1147 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1148 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1150 2019-07-01 Jan Beulich <jbeulich@suse.com>
1152 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1153 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1154 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1155 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1156 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1157 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1158 * i386-tbl.h: Re-generate.
1160 2019-07-01 Jan Beulich <jbeulich@suse.com>
1162 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1164 * i386-tbl.h: Re-generate.
1166 2019-07-01 Jan Beulich <jbeulich@suse.com>
1168 * i386-opc.tbl (C): New.
1169 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1170 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1171 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1172 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1173 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1174 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1175 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1176 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1177 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1178 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1179 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1180 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1181 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1182 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1183 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1184 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1185 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1186 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1187 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1188 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1189 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1190 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1191 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1192 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1193 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1194 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1196 * i386-tbl.h: Re-generate.
1198 2019-07-01 Jan Beulich <jbeulich@suse.com>
1200 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1202 * i386-tbl.h: Re-generate.
1204 2019-07-01 Jan Beulich <jbeulich@suse.com>
1206 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1207 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1208 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1209 * i386-tbl.h: Re-generate.
1211 2019-07-01 Jan Beulich <jbeulich@suse.com>
1213 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1214 Disp8MemShift from register only templates.
1215 * i386-tbl.h: Re-generate.
1217 2019-07-01 Jan Beulich <jbeulich@suse.com>
1219 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1220 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1221 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1222 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1223 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1224 EVEX_W_0F11_P_3_M_1): Delete.
1225 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1226 EVEX_W_0F11_P_3): New.
1227 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1228 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1229 MOD_EVEX_0F11_PREFIX_3 table entries.
1230 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1231 PREFIX_EVEX_0F11 table entries.
1232 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1233 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1234 EVEX_W_0F11_P_3_M_{0,1} table entries.
1236 2019-07-01 Jan Beulich <jbeulich@suse.com>
1238 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1241 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1244 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1245 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1246 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1247 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1248 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1249 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1250 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1251 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1252 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1253 PREFIX_EVEX_0F38C6_REG_6 entries.
1254 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1255 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1256 EVEX_W_0F38C7_R_6_P_2 entries.
1257 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1258 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1259 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1260 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1261 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1262 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1263 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1265 2019-06-27 Jan Beulich <jbeulich@suse.com>
1267 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1268 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1269 VEX_LEN_0F2D_P_3): Delete.
1270 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1271 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1272 (prefix_table): ... here.
1274 2019-06-27 Jan Beulich <jbeulich@suse.com>
1276 * i386-dis.c (Iq): Delete.
1278 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1280 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1281 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1282 (OP_E_memory): Also honor needindex when deciding whether an
1283 address size prefix needs printing.
1284 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1286 2019-06-26 Jim Wilson <jimw@sifive.com>
1289 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1290 Set info->display_endian to info->endian_code.
1292 2019-06-25 Jan Beulich <jbeulich@suse.com>
1294 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1295 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1296 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1297 OPERAND_TYPE_ACC64 entries.
1298 * i386-init.h: Re-generate.
1300 2019-06-25 Jan Beulich <jbeulich@suse.com>
1302 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1304 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1306 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1308 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1309 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1311 2019-06-25 Jan Beulich <jbeulich@suse.com>
1313 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1316 2019-06-25 Jan Beulich <jbeulich@suse.com>
1318 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1319 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1321 * i386-opc.tbl (movnti): Add IgnoreSize.
1322 * i386-tbl.h: Re-generate.
1324 2019-06-25 Jan Beulich <jbeulich@suse.com>
1326 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1327 * i386-tbl.h: Re-generate.
1329 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1331 * i386-dis-evex.h: Break into ...
1332 * i386-dis-evex-len.h: New file.
1333 * i386-dis-evex-mod.h: Likewise.
1334 * i386-dis-evex-prefix.h: Likewise.
1335 * i386-dis-evex-reg.h: Likewise.
1336 * i386-dis-evex-w.h: Likewise.
1337 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1338 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1339 i386-dis-evex-mod.h.
1341 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1344 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1345 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1347 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1348 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1349 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1350 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1351 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1352 EVEX_LEN_0F385B_P_2_W_1.
1353 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1354 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1355 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1356 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1357 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1358 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1359 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1360 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1361 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1362 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1364 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1367 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1368 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1369 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1370 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1371 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1372 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1373 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1374 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1375 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1376 EVEX_LEN_0F3A43_P_2_W_1.
1377 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1378 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1379 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1380 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1381 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1382 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1383 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1384 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1385 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1386 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1387 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1388 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1390 2019-06-14 Nick Clifton <nickc@redhat.com>
1392 * po/fr.po; Updated French translation.
1394 2019-06-13 Stafford Horne <shorne@gmail.com>
1396 * or1k-asm.c: Regenerated.
1397 * or1k-desc.c: Regenerated.
1398 * or1k-desc.h: Regenerated.
1399 * or1k-dis.c: Regenerated.
1400 * or1k-ibld.c: Regenerated.
1401 * or1k-opc.c: Regenerated.
1402 * or1k-opc.h: Regenerated.
1403 * or1k-opinst.c: Regenerated.
1405 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1407 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1409 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1412 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1413 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1414 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1415 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1416 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1417 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1418 EVEX_LEN_0F3A1B_P_2_W_1.
1419 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1420 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1421 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1422 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1423 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1424 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1425 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1426 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1428 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1431 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1432 EVEX.vvvv when disassembling VEX and EVEX instructions.
1433 (OP_VEX): Set vex.register_specifier to 0 after readding
1434 vex.register_specifier.
1435 (OP_Vex_2src_1): Likewise.
1436 (OP_Vex_2src_2): Likewise.
1437 (OP_LWP_E): Likewise.
1438 (OP_EX_Vex): Don't check vex.register_specifier.
1439 (OP_XMM_Vex): Likewise.
1441 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1442 Lili Cui <lili.cui@intel.com>
1444 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1445 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1447 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1448 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1449 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1450 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1451 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1452 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1453 * i386-init.h: Regenerated.
1454 * i386-tbl.h: Likewise.
1456 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1457 Lili Cui <lili.cui@intel.com>
1459 * doc/c-i386.texi: Document enqcmd.
1460 * testsuite/gas/i386/enqcmd-intel.d: New file.
1461 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1462 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1463 * testsuite/gas/i386/enqcmd.d: Likewise.
1464 * testsuite/gas/i386/enqcmd.s: Likewise.
1465 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1466 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1467 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1468 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1469 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1470 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1471 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1474 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1476 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1478 2019-06-03 Alan Modra <amodra@gmail.com>
1480 * ppc-dis.c (prefix_opcd_indices): Correct size.
1482 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1485 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1487 * i386-tbl.h: Regenerated.
1489 2019-05-24 Alan Modra <amodra@gmail.com>
1491 * po/POTFILES.in: Regenerate.
1493 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1494 Alan Modra <amodra@gmail.com>
1496 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1497 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1498 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1499 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1500 XTOP>): Define and add entries.
1501 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1502 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1503 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1504 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1506 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1507 Alan Modra <amodra@gmail.com>
1509 * ppc-dis.c (ppc_opts): Add "future" entry.
1510 (PREFIX_OPCD_SEGS): Define.
1511 (prefix_opcd_indices): New array.
1512 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1513 (lookup_prefix): New function.
1514 (print_insn_powerpc): Handle 64-bit prefix instructions.
1515 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1516 (PMRR, POWERXX): Define.
1517 (prefix_opcodes): New instruction table.
1518 (prefix_num_opcodes): New constant.
1520 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1522 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1523 * configure: Regenerated.
1524 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1526 (HFILES): Add bpf-desc.h and bpf-opc.h.
1527 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1528 bpf-ibld.c and bpf-opc.c.
1530 * Makefile.in: Regenerated.
1531 * disassemble.c (ARCH_bpf): Define.
1532 (disassembler): Add case for bfd_arch_bpf.
1533 (disassemble_init_for_target): Likewise.
1534 (enum epbf_isa_attr): Define.
1535 * disassemble.h: extern print_insn_bpf.
1536 * bpf-asm.c: Generated.
1537 * bpf-opc.h: Likewise.
1538 * bpf-opc.c: Likewise.
1539 * bpf-ibld.c: Likewise.
1540 * bpf-dis.c: Likewise.
1541 * bpf-desc.h: Likewise.
1542 * bpf-desc.c: Likewise.
1544 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1546 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1547 and VMSR with the new operands.
1549 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1551 * arm-dis.c (enum mve_instructions): New enum
1552 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1554 (mve_opcodes): New instructions as above.
1555 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1557 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1559 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1561 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1562 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1563 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1564 uqshl, urshrl and urshr.
1565 (is_mve_okay_in_it): Add new instructions to TRUE list.
1566 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1567 (print_insn_mve): Updated to accept new %j,
1568 %<bitfield>m and %<bitfield>n patterns.
1570 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1572 * mips-opc.c (mips_builtin_opcodes): Change source register
1573 constraint for DAUI.
1575 2019-05-20 Nick Clifton <nickc@redhat.com>
1577 * po/fr.po: Updated French translation.
1579 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1580 Michael Collison <michael.collison@arm.com>
1582 * arm-dis.c (thumb32_opcodes): Add new instructions.
1583 (enum mve_instructions): Likewise.
1584 (enum mve_undefined): Add new reasons.
1585 (is_mve_encoding_conflict): Handle new instructions.
1586 (is_mve_undefined): Likewise.
1587 (is_mve_unpredictable): Likewise.
1588 (print_mve_undefined): Likewise.
1589 (print_mve_size): Likewise.
1591 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1592 Michael Collison <michael.collison@arm.com>
1594 * arm-dis.c (thumb32_opcodes): Add new instructions.
1595 (enum mve_instructions): Likewise.
1596 (is_mve_encoding_conflict): Handle new instructions.
1597 (is_mve_undefined): Likewise.
1598 (is_mve_unpredictable): Likewise.
1599 (print_mve_size): Likewise.
1601 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1602 Michael Collison <michael.collison@arm.com>
1604 * arm-dis.c (thumb32_opcodes): Add new instructions.
1605 (enum mve_instructions): Likewise.
1606 (is_mve_encoding_conflict): Likewise.
1607 (is_mve_unpredictable): Likewise.
1608 (print_mve_size): Likewise.
1610 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1611 Michael Collison <michael.collison@arm.com>
1613 * arm-dis.c (thumb32_opcodes): Add new instructions.
1614 (enum mve_instructions): Likewise.
1615 (is_mve_encoding_conflict): Handle new instructions.
1616 (is_mve_undefined): Likewise.
1617 (is_mve_unpredictable): Likewise.
1618 (print_mve_size): Likewise.
1620 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1621 Michael Collison <michael.collison@arm.com>
1623 * arm-dis.c (thumb32_opcodes): Add new instructions.
1624 (enum mve_instructions): Likewise.
1625 (is_mve_encoding_conflict): Handle new instructions.
1626 (is_mve_undefined): Likewise.
1627 (is_mve_unpredictable): Likewise.
1628 (print_mve_size): Likewise.
1629 (print_insn_mve): Likewise.
1631 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1632 Michael Collison <michael.collison@arm.com>
1634 * arm-dis.c (thumb32_opcodes): Add new instructions.
1635 (print_insn_thumb32): Handle new instructions.
1637 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1638 Michael Collison <michael.collison@arm.com>
1640 * arm-dis.c (enum mve_instructions): Add new instructions.
1641 (enum mve_undefined): Add new reasons.
1642 (is_mve_encoding_conflict): Handle new instructions.
1643 (is_mve_undefined): Likewise.
1644 (is_mve_unpredictable): Likewise.
1645 (print_mve_undefined): Likewise.
1646 (print_mve_size): Likewise.
1647 (print_mve_shift_n): Likewise.
1648 (print_insn_mve): Likewise.
1650 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1651 Michael Collison <michael.collison@arm.com>
1653 * arm-dis.c (enum mve_instructions): Add new instructions.
1654 (is_mve_encoding_conflict): Handle new instructions.
1655 (is_mve_unpredictable): Likewise.
1656 (print_mve_rotate): Likewise.
1657 (print_mve_size): Likewise.
1658 (print_insn_mve): Likewise.
1660 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1661 Michael Collison <michael.collison@arm.com>
1663 * arm-dis.c (enum mve_instructions): Add new instructions.
1664 (is_mve_encoding_conflict): Handle new instructions.
1665 (is_mve_unpredictable): Likewise.
1666 (print_mve_size): Likewise.
1667 (print_insn_mve): Likewise.
1669 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1670 Michael Collison <michael.collison@arm.com>
1672 * arm-dis.c (enum mve_instructions): Add new instructions.
1673 (enum mve_undefined): Add new reasons.
1674 (is_mve_encoding_conflict): Handle new instructions.
1675 (is_mve_undefined): Likewise.
1676 (is_mve_unpredictable): Likewise.
1677 (print_mve_undefined): Likewise.
1678 (print_mve_size): Likewise.
1679 (print_insn_mve): Likewise.
1681 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1682 Michael Collison <michael.collison@arm.com>
1684 * arm-dis.c (enum mve_instructions): Add new instructions.
1685 (is_mve_encoding_conflict): Handle new instructions.
1686 (is_mve_undefined): Likewise.
1687 (is_mve_unpredictable): Likewise.
1688 (print_mve_size): Likewise.
1689 (print_insn_mve): Likewise.
1691 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1692 Michael Collison <michael.collison@arm.com>
1694 * arm-dis.c (enum mve_instructions): Add new instructions.
1695 (enum mve_unpredictable): Add new reasons.
1696 (enum mve_undefined): Likewise.
1697 (is_mve_okay_in_it): Handle new isntructions.
1698 (is_mve_encoding_conflict): Likewise.
1699 (is_mve_undefined): Likewise.
1700 (is_mve_unpredictable): Likewise.
1701 (print_mve_vmov_index): Likewise.
1702 (print_simd_imm8): Likewise.
1703 (print_mve_undefined): Likewise.
1704 (print_mve_unpredictable): Likewise.
1705 (print_mve_size): Likewise.
1706 (print_insn_mve): Likewise.
1708 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1709 Michael Collison <michael.collison@arm.com>
1711 * arm-dis.c (enum mve_instructions): Add new instructions.
1712 (enum mve_unpredictable): Add new reasons.
1713 (enum mve_undefined): Likewise.
1714 (is_mve_encoding_conflict): Handle new instructions.
1715 (is_mve_undefined): Likewise.
1716 (is_mve_unpredictable): Likewise.
1717 (print_mve_undefined): Likewise.
1718 (print_mve_unpredictable): Likewise.
1719 (print_mve_rounding_mode): Likewise.
1720 (print_mve_vcvt_size): Likewise.
1721 (print_mve_size): Likewise.
1722 (print_insn_mve): Likewise.
1724 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1725 Michael Collison <michael.collison@arm.com>
1727 * arm-dis.c (enum mve_instructions): Add new instructions.
1728 (enum mve_unpredictable): Add new reasons.
1729 (enum mve_undefined): Likewise.
1730 (is_mve_undefined): Handle new instructions.
1731 (is_mve_unpredictable): Likewise.
1732 (print_mve_undefined): Likewise.
1733 (print_mve_unpredictable): Likewise.
1734 (print_mve_size): Likewise.
1735 (print_insn_mve): Likewise.
1737 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1738 Michael Collison <michael.collison@arm.com>
1740 * arm-dis.c (enum mve_instructions): Add new instructions.
1741 (enum mve_undefined): Add new reasons.
1742 (insns): Add new instructions.
1743 (is_mve_encoding_conflict):
1744 (print_mve_vld_str_addr): New print function.
1745 (is_mve_undefined): Handle new instructions.
1746 (is_mve_unpredictable): Likewise.
1747 (print_mve_undefined): Likewise.
1748 (print_mve_size): Likewise.
1749 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1750 (print_insn_mve): Handle new operands.
1752 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1753 Michael Collison <michael.collison@arm.com>
1755 * arm-dis.c (enum mve_instructions): Add new instructions.
1756 (enum mve_unpredictable): Add new reasons.
1757 (is_mve_encoding_conflict): Handle new instructions.
1758 (is_mve_unpredictable): Likewise.
1759 (mve_opcodes): Add new instructions.
1760 (print_mve_unpredictable): Handle new reasons.
1761 (print_mve_register_blocks): New print function.
1762 (print_mve_size): Handle new instructions.
1763 (print_insn_mve): Likewise.
1765 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1766 Michael Collison <michael.collison@arm.com>
1768 * arm-dis.c (enum mve_instructions): Add new instructions.
1769 (enum mve_unpredictable): Add new reasons.
1770 (enum mve_undefined): Likewise.
1771 (is_mve_encoding_conflict): Handle new instructions.
1772 (is_mve_undefined): Likewise.
1773 (is_mve_unpredictable): Likewise.
1774 (coprocessor_opcodes): Move NEON VDUP from here...
1775 (neon_opcodes): ... to here.
1776 (mve_opcodes): Add new instructions.
1777 (print_mve_undefined): Handle new reasons.
1778 (print_mve_unpredictable): Likewise.
1779 (print_mve_size): Handle new instructions.
1780 (print_insn_neon): Handle vdup.
1781 (print_insn_mve): Handle new operands.
1783 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1784 Michael Collison <michael.collison@arm.com>
1786 * arm-dis.c (enum mve_instructions): Add new instructions.
1787 (enum mve_unpredictable): Add new values.
1788 (mve_opcodes): Add new instructions.
1789 (vec_condnames): New array with vector conditions.
1790 (mve_predicatenames): New array with predicate suffixes.
1791 (mve_vec_sizename): New array with vector sizes.
1792 (enum vpt_pred_state): New enum with vector predication states.
1793 (struct vpt_block): New struct type for vpt blocks.
1794 (vpt_block_state): Global struct to keep track of state.
1795 (mve_extract_pred_mask): New helper function.
1796 (num_instructions_vpt_block): Likewise.
1797 (mark_outside_vpt_block): Likewise.
1798 (mark_inside_vpt_block): Likewise.
1799 (invert_next_predicate_state): Likewise.
1800 (update_next_predicate_state): Likewise.
1801 (update_vpt_block_state): Likewise.
1802 (is_vpt_instruction): Likewise.
1803 (is_mve_encoding_conflict): Add entries for new instructions.
1804 (is_mve_unpredictable): Likewise.
1805 (print_mve_unpredictable): Handle new cases.
1806 (print_instruction_predicate): Likewise.
1807 (print_mve_size): New function.
1808 (print_vec_condition): New function.
1809 (print_insn_mve): Handle vpt blocks and new print operands.
1811 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1813 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1814 8, 14 and 15 for Armv8.1-M Mainline.
1816 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1817 Michael Collison <michael.collison@arm.com>
1819 * arm-dis.c (enum mve_instructions): New enum.
1820 (enum mve_unpredictable): Likewise.
1821 (enum mve_undefined): Likewise.
1822 (struct mopcode32): New struct.
1823 (is_mve_okay_in_it): New function.
1824 (is_mve_architecture): Likewise.
1825 (arm_decode_field): Likewise.
1826 (arm_decode_field_multiple): Likewise.
1827 (is_mve_encoding_conflict): Likewise.
1828 (is_mve_undefined): Likewise.
1829 (is_mve_unpredictable): Likewise.
1830 (print_mve_undefined): Likewise.
1831 (print_mve_unpredictable): Likewise.
1832 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1833 (print_insn_mve): New function.
1834 (print_insn_thumb32): Handle MVE architecture.
1835 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1837 2019-05-10 Nick Clifton <nickc@redhat.com>
1840 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1841 end of the table prematurely.
1843 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1845 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1848 2019-05-11 Alan Modra <amodra@gmail.com>
1850 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1851 when -Mraw is in effect.
1853 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1855 * aarch64-dis-2.c: Regenerate.
1856 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1857 (OP_SVE_BBB): New variant set.
1858 (OP_SVE_DDDD): New variant set.
1859 (OP_SVE_HHH): New variant set.
1860 (OP_SVE_HHHU): New variant set.
1861 (OP_SVE_SSS): New variant set.
1862 (OP_SVE_SSSU): New variant set.
1863 (OP_SVE_SHH): New variant set.
1864 (OP_SVE_SBBU): New variant set.
1865 (OP_SVE_DSS): New variant set.
1866 (OP_SVE_DHHU): New variant set.
1867 (OP_SVE_VMV_HSD_BHS): New variant set.
1868 (OP_SVE_VVU_HSD_BHS): New variant set.
1869 (OP_SVE_VVVU_SD_BH): New variant set.
1870 (OP_SVE_VVVU_BHSD): New variant set.
1871 (OP_SVE_VVV_QHD_DBS): New variant set.
1872 (OP_SVE_VVV_HSD_BHS): New variant set.
1873 (OP_SVE_VVV_HSD_BHS2): New variant set.
1874 (OP_SVE_VVV_BHS_HSD): New variant set.
1875 (OP_SVE_VV_BHS_HSD): New variant set.
1876 (OP_SVE_VVV_SD): New variant set.
1877 (OP_SVE_VVU_BHS_HSD): New variant set.
1878 (OP_SVE_VZVV_SD): New variant set.
1879 (OP_SVE_VZVV_BH): New variant set.
1880 (OP_SVE_VZV_SD): New variant set.
1881 (aarch64_opcode_table): Add sve2 instructions.
1883 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1885 * aarch64-asm-2.c: Regenerated.
1886 * aarch64-dis-2.c: Regenerated.
1887 * aarch64-opc-2.c: Regenerated.
1888 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1889 for SVE_SHLIMM_UNPRED_22.
1890 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1891 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1894 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1896 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1897 sve_size_tsz_bhs iclass encode.
1898 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1899 sve_size_tsz_bhs iclass decode.
1901 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1903 * aarch64-asm-2.c: Regenerated.
1904 * aarch64-dis-2.c: Regenerated.
1905 * aarch64-opc-2.c: Regenerated.
1906 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1907 for SVE_Zm4_11_INDEX.
1908 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1909 (fields): Handle SVE_i2h field.
1910 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1911 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1913 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1915 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1916 sve_shift_tsz_bhsd iclass encode.
1917 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1918 sve_shift_tsz_bhsd iclass decode.
1920 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1922 * aarch64-asm-2.c: Regenerated.
1923 * aarch64-dis-2.c: Regenerated.
1924 * aarch64-opc-2.c: Regenerated.
1925 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1926 (aarch64_encode_variant_using_iclass): Handle
1927 sve_shift_tsz_hsd iclass encode.
1928 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1929 sve_shift_tsz_hsd iclass decode.
1930 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1931 for SVE_SHRIMM_UNPRED_22.
1932 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1933 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1936 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1938 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1939 sve_size_013 iclass encode.
1940 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1941 sve_size_013 iclass decode.
1943 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1945 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1946 sve_size_bh iclass encode.
1947 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1948 sve_size_bh iclass decode.
1950 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1952 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1953 sve_size_sd2 iclass encode.
1954 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1955 sve_size_sd2 iclass decode.
1956 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1957 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1959 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1961 * aarch64-asm-2.c: Regenerated.
1962 * aarch64-dis-2.c: Regenerated.
1963 * aarch64-opc-2.c: Regenerated.
1964 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1966 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1967 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1969 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1971 * aarch64-asm-2.c: Regenerated.
1972 * aarch64-dis-2.c: Regenerated.
1973 * aarch64-opc-2.c: Regenerated.
1974 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1975 for SVE_Zm3_11_INDEX.
1976 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1977 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1978 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1980 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1982 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1984 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1985 sve_size_hsd2 iclass encode.
1986 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1987 sve_size_hsd2 iclass decode.
1988 * aarch64-opc.c (fields): Handle SVE_size field.
1989 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1991 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1993 * aarch64-asm-2.c: Regenerated.
1994 * aarch64-dis-2.c: Regenerated.
1995 * aarch64-opc-2.c: Regenerated.
1996 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1998 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1999 (fields): Handle SVE_rot3 field.
2000 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
2001 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2003 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2005 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
2008 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2011 (aarch64_feature_sve2, aarch64_feature_sve2aes,
2012 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
2013 aarch64_feature_sve2bitperm): New feature sets.
2014 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
2015 for feature set addresses.
2016 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
2017 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
2020 Faraz Shahbazker <fshahbazker@wavecomp.com>
2022 * mips-dis.c (mips_calculate_combination_ases): Add ISA
2023 argument and set ASE_EVA_R6 appropriately.
2024 (set_default_mips_dis_options): Pass ISA to above.
2025 (parse_mips_dis_option): Likewise.
2026 * mips-opc.c (EVAR6): New macro.
2027 (mips_builtin_opcodes): Add llwpe, scwpe.
2029 2019-05-01 Sudakshina Das <sudi.das@arm.com>
2031 * aarch64-asm-2.c: Regenerated.
2032 * aarch64-dis-2.c: Regenerated.
2033 * aarch64-opc-2.c: Regenerated.
2034 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2035 AARCH64_OPND_TME_UIMM16.
2036 (aarch64_print_operand): Likewise.
2037 * aarch64-tbl.h (QL_IMM_NIL): New.
2040 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2042 2019-04-29 John Darrington <john@darrington.wattle.id.au>
2044 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2046 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
2047 Faraz Shahbazker <fshahbazker@wavecomp.com>
2049 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2051 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2053 * s12z-opc.h: Add extern "C" bracketing to help
2054 users who wish to use this interface in c++ code.
2056 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2058 * s12z-opc.c (bm_decode): Handle bit map operations with the
2061 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2063 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2064 specifier. Add entries for VLDR and VSTR of system registers.
2065 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2066 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2067 of %J and %K format specifier.
2069 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2071 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2072 Add new entries for VSCCLRM instruction.
2073 (print_insn_coprocessor): Handle new %C format control code.
2075 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2077 * arm-dis.c (enum isa): New enum.
2078 (struct sopcode32): New structure.
2079 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2080 set isa field of all current entries to ANY.
2081 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2082 Only match an entry if its isa field allows the current mode.
2084 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2086 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2088 (print_insn_thumb32): Add logic to print %n CLRM register list.
2090 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2092 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2095 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2097 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2098 (print_insn_thumb32): Edit the switch case for %Z.
2100 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2102 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2104 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2106 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2108 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2110 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2112 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2114 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2115 Arm register with r13 and r15 unpredictable.
2116 (thumb32_opcodes): New instructions for bfx and bflx.
2118 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2120 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2122 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2124 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2126 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2128 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2130 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2132 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2134 2019-04-12 John Darrington <john@darrington.wattle.id.au>
2136 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2137 "optr". ("operator" is a reserved word in c++).
2139 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2141 * aarch64-opc.c (aarch64_print_operand): Add case for
2143 (verify_constraints): Likewise.
2144 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2145 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2146 to accept Rt|SP as first operand.
2147 (AARCH64_OPERANDS): Add new Rt_SP.
2148 * aarch64-asm-2.c: Regenerated.
2149 * aarch64-dis-2.c: Regenerated.
2150 * aarch64-opc-2.c: Regenerated.
2152 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2154 * aarch64-asm-2.c: Regenerated.
2155 * aarch64-dis-2.c: Likewise.
2156 * aarch64-opc-2.c: Likewise.
2157 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2159 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2161 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2163 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2165 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2166 * i386-init.h: Regenerated.
2168 2019-04-07 Alan Modra <amodra@gmail.com>
2170 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2171 op_separator to control printing of spaces, comma and parens
2172 rather than need_comma, need_paren and spaces vars.
2174 2019-04-07 Alan Modra <amodra@gmail.com>
2177 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2178 (print_insn_neon, print_insn_arm): Likewise.
2180 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2182 * i386-dis-evex.h (evex_table): Updated to support BF16
2184 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2185 and EVEX_W_0F3872_P_3.
2186 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2187 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2188 * i386-opc.h (enum): Add CpuAVX512_BF16.
2189 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2190 * i386-opc.tbl: Add AVX512 BF16 instructions.
2191 * i386-init.h: Regenerated.
2192 * i386-tbl.h: Likewise.
2194 2019-04-05 Alan Modra <amodra@gmail.com>
2196 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2197 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2198 to favour printing of "-" branch hint when using the "y" bit.
2199 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2201 2019-04-05 Alan Modra <amodra@gmail.com>
2203 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2204 opcode until first operand is output.
2206 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
2209 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2210 (valid_bo_post_v2): Add support for 'at' branch hints.
2211 (insert_bo): Only error on branch on ctr.
2212 (get_bo_hint_mask): New function.
2213 (insert_boe): Add new 'branch_taken' formal argument. Add support
2214 for inserting 'at' branch hints.
2215 (extract_boe): Add new 'branch_taken' formal argument. Add support
2216 for extracting 'at' branch hints.
2217 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2218 (BOE): Delete operand.
2219 (BOM, BOP): New operands.
2221 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2222 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2223 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2224 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2225 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2226 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2227 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2228 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2229 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2230 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2231 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2232 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2233 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2234 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2235 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2236 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2237 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2238 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2239 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2240 bttarl+>: New extended mnemonics.
2242 2019-03-28 Alan Modra <amodra@gmail.com>
2245 * ppc-opc.c (BTF): Define.
2246 (powerpc_opcodes): Use for mtfsb*.
2247 * ppc-dis.c (print_insn_powerpc): Print fields with both
2248 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2250 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2252 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2253 (mapping_symbol_for_insn): Implement new algorithm.
2254 (print_insn): Remove duplicate code.
2256 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2258 * aarch64-dis.c (print_insn_aarch64):
2261 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2263 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2266 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2268 * aarch64-dis.c (last_stop_offset): New.
2269 (print_insn_aarch64): Use stop_offset.
2271 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2274 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2276 * i386-init.h: Regenerated.
2278 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2281 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2282 vmovdqu16, vmovdqu32 and vmovdqu64.
2283 * i386-tbl.h: Regenerated.
2285 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2287 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2288 from vstrszb, vstrszh, and vstrszf.
2290 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2292 * s390-opc.txt: Add instruction descriptions.
2294 2019-02-08 Jim Wilson <jimw@sifive.com>
2296 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2299 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2301 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2303 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2306 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2307 * aarch64-opc.c (verify_elem_sd): New.
2308 (fields): Add FLD_sz entr.
2309 * aarch64-tbl.h (_SIMD_INSN): New.
2310 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2311 fmulx scalar and vector by element isns.
2313 2019-02-07 Nick Clifton <nickc@redhat.com>
2315 * po/sv.po: Updated Swedish translation.
2317 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2319 * s390-mkopc.c (main): Accept arch13 as cpu string.
2320 * s390-opc.c: Add new instruction formats and instruction opcode
2322 * s390-opc.txt: Add new arch13 instructions.
2324 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2326 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2327 (aarch64_opcode): Change encoding for stg, stzg
2329 * aarch64-asm-2.c: Regenerated.
2330 * aarch64-dis-2.c: Regenerated.
2331 * aarch64-opc-2.c: Regenerated.
2333 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2335 * aarch64-asm-2.c: Regenerated.
2336 * aarch64-dis-2.c: Likewise.
2337 * aarch64-opc-2.c: Likewise.
2338 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2340 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2341 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2343 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2344 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2345 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2346 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2347 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2348 case for ldstgv_indexed.
2349 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2350 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2351 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2352 * aarch64-asm-2.c: Regenerated.
2353 * aarch64-dis-2.c: Regenerated.
2354 * aarch64-opc-2.c: Regenerated.
2356 2019-01-23 Nick Clifton <nickc@redhat.com>
2358 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2360 2019-01-21 Nick Clifton <nickc@redhat.com>
2362 * po/de.po: Updated German translation.
2363 * po/uk.po: Updated Ukranian translation.
2365 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2366 * mips-dis.c (mips_arch_choices): Fix typo in
2367 gs464, gs464e and gs264e descriptors.
2369 2019-01-19 Nick Clifton <nickc@redhat.com>
2371 * configure: Regenerate.
2372 * po/opcodes.pot: Regenerate.
2374 2018-06-24 Nick Clifton <nickc@redhat.com>
2376 2.32 branch created.
2378 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2380 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2382 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2385 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2387 * configure: Regenerate.
2389 2019-01-07 Alan Modra <amodra@gmail.com>
2391 * configure: Regenerate.
2392 * po/POTFILES.in: Regenerate.
2394 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2396 * s12z-opc.c: New file.
2397 * s12z-opc.h: New file.
2398 * s12z-dis.c: Removed all code not directly related to display
2399 of instructions. Used the interface provided by the new files
2401 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2402 * Makefile.in: Regenerate.
2403 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2404 * configure: Regenerate.
2406 2019-01-01 Alan Modra <amodra@gmail.com>
2408 Update year range in copyright notice of all files.
2410 For older changes see ChangeLog-2018
2412 Copyright (C) 2019 Free Software Foundation, Inc.
2414 Copying and distribution of this file, with or without modification,
2415 are permitted in any medium without royalty provided the copyright
2416 notice and this notice are preserved.
2422 version-control: never