opcodes/ChangeLog

   1 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
   2             Joseph Myers  <joseph@codesourcery.com>
   3             Ian Lance Taylor  <ian@wasabisystems.com>
   4             Ben Elliston  <bje@wasabisystems.com>
   5
   6         * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
   7         only be used with the default multiply-add operation, so if N is
   8         set, don't bother printing X.  Add new iwmmxt instructions.
   9         (IWMMXT_INSN_COUNT): Update.
  10         (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
  11         with a 'c' suffix.
  12         (print_insn_coprocessor): Check for iWMMXt2.  Handle format
  13         specifiers 'r', 'i'.
  14
  15 2006-09-24  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  16
  17         PR binutils/3100
  18         * i386-dis.c (prefix_user_table): Fix the second operand of
  19         maskmovdqu instruction to allow only %xmm register instead of
  20         both %xmm register and memory.
  21
  22 2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
  23
  24         PR binutils/3235
  25         * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
  26         address size prefix.
  27
  28 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  29
  30         * score-dis.c: New file.
  31         * score-opc.h: New file.
  32         * Makefile.am: Add Score files.
  33         * Makefile.in: Regenerate.
  34         * configure.in: Add support for Score target.
  35         * configure: Regenerate.
  36         * disassemble.c: Add support for Score target.
  37
  38 2006-09-16  Nick Clifton  <nickc@redhat.com>
  39             Pedro Alves  <pedro_alves@portugalmail.pt>
  40
  41         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
  42         macros defined in bfd.h.
  43         * cris-dis.c: Likewise.
  44         * h8300-dis.c: Likewise.
  45         * i386-dis.c: Likewise.
  46         * ia64-gen.c: Likewise.
  47         * mips-dis: Likewise.
  48
  49 2006-09-04  Paul Brook  <paul@codesourcery.com>
  50
  51         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
  52
  53 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
  54
  55         * i386-dis.c (three_byte_table): Expand to 256 elements.
  56
  57 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  58
  59         PR binutils/3000
  60         * i386-dis.c (MXC,EMC): Define.
  61         (OP_MXC): New function to handle cvt* (convert instructions) between
  62         %xmm and %mm register correctly.
  63         (OP_EMC): ditto.
  64         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
  65         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
  66         with EMC/MXC.
  67
  68 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
  69
  70         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
  71         "fdaddl" entry.
  72
  73 2006-07-19  Paul Brook  <paul@codesourcery.com>
  74
  75         * armd-dis.c (arm_opcodes): Fix rbit opcode.
  76
  77 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  78
  79         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
  80         "sldt", "str" and "smsw".
  81
  82 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
  83
  84         PR binutils/2829
  85         * i386-dis.c (GRP11_C6): NEW.
  86         (GRP11_C7): Likewise.
  87         (GRP12): Updated.
  88         (GRP13): Likewise.
  89         (GRP14): Likewise.
  90         (GRP15): Likewise.
  91         (GRP16): Likewise.
  92         (GRPAMD): Likewise.
  93         (GRPPADLCK1): Likewise.
  94         (GRPPADLCK2): Likewise.
  95         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
  96         respectively.
  97         (grps): Add entries for GRP11_C6 and GRP11_C7.
  98
  99 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 100            Michael Meissner             <michael.meissner@amd.com>
 101
 102         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
 103         support for amdfam10 SSE4a/ABM instructions. Modify all
 104         initializer macros to have additional arguments. Disallow REP
 105         prefix for non-string instructions.
 106         (print_insn): Ditto.
 107
 108
 109 2006-07-05  Julian Brown  <julian@codesourcery.com>
 110
 111         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
 112
 113 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 114
 115         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
 116         (twobyte_has_modrm): Set 1 for 0x1f.
 117
 118 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         * i386-dis.c (NOP_Fixup): Removed.
 121         (NOP_Fixup1): New.
 122         (NOP_Fixup2): Likewise.
 123         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 124
 125 2006-06-12  Julian Brown  <julian@codesourcery.com>
 126
 127         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
 128         on 64-bit hosts.
 129
 130 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 131
 132         * i386.c (GRP10): Renamed to ...
 133         (GRP12): This.
 134         (GRP11): Renamed to ...
 135         (GRP13): This.
 136         (GRP12): Renamed to ...
 137         (GRP14): This.
 138         (GRP13): Renamed to ...
 139         (GRP15): This.
 140         (GRP14): Renamed to ...
 141         (GRP16): This.
 142         (dis386_twobyte): Updated.
 143         (grps): Likewise.
 144
 145 2006-06-09  Nick Clifton  <nickc@redhat.com>
 146
 147         * po/fi.po: Updated Finnish translation.
 148
 149 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 150
 151         * po/Make-in (pdf, ps): New dummy targets.
 152
 153 2006-06-06  Paul Brook  <paul@codesourcery.com>
 154
 155         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 156         instructions.
 157         (neon_opcodes): Add conditional execution specifiers.
 158         (thumb_opcodes): Ditto.
 159         (thumb32_opcodes): Ditto.
 160         (arm_conditional): Change 0xe to "al" and add "" to end.
 161         (ifthen_state, ifthen_next_state, ifthen_address): New.
 162         (IFTHEN_COND): Define.
 163         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 164         (print_insn_arm): Change %c to use new values of arm_conditional.
 165         (print_insn_thumb16): Print thumb conditions.  Add %I.
 166         (print_insn_thumb32): Print thumb conditions.
 167         (find_ifthen_state): New function.
 168         (print_insn): Track IT block state.
 169
 170 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 171             Anton Blanchard  <anton@samba.org>
 172             Peter Bergner  <bergner@vnet.ibm.com>
 173
 174         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 175         (print_ppc_disassembler_options): Mention power6.
 176
 177 2006-06-06  Thiemo Seufer  <ths@mips.com>
 178             Chao-ying Fu  <fu@mips.com>
 179
 180         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 181         * mips-opc.c: Add DSP64 instructions.
 182
 183 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 184
 185         * m68hc11-dis.c (print_insn): Warning fix.
 186
 187 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 188
 189         * po/Make-in (top_builddir): Define.
 190
 191 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 192
 193         * Makefile.am: Run "make dep-am".
 194         * Makefile.in: Regenerate.
 195         * config.in: Regenerate.
 196
 197 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 198
 199         * Makefile.am (INCLUDES): Use @INCINTL@.
 200         * acinclude.m4: Include new gettext macros.
 201         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 202         Remove local code for po/Makefile.
 203         * Makefile.in, aclocal.m4, configure: Regenerated.
 204
 205 2006-05-30  Nick Clifton  <nickc@redhat.com>
 206
 207         * po/es.po: Updated Spanish translation.
 208
 209 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 210
 211         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 212         and fmovem entries.  Put register list entries before immediate
 213         mask entries.  Use "l" rather than "L" in the fmovem entries.
 214         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 215         out from INFO.
 216         (m68k_scan_mask): New function, split out from...
 217         (print_insn_m68k): ...here.  If no architecture has been set,
 218         first try printing an m680x0 instruction, then try a Coldfire one.
 219
 220 2006-05-24  Nick Clifton  <nickc@redhat.com>
 221
 222         * po/ga.po: Updated Irish translation.
 223
 224 2006-05-22  Nick Clifton  <nickc@redhat.com>
 225
 226         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 227
 228 2006-05-22  Nick Clifton  <nickc@redhat.com>
 229
 230         * po/nl.po: Updated translation.
 231
 232 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 233
 234         * avr-dis.c: Formatting fix.
 235
 236 2006-05-14  Thiemo Seufer  <ths@mips.com>
 237
 238         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 239         (mips16_opcodes): Change membership of instructions to their
 240         lowest baseline ISA.
 241
 242 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 243
 244         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 245
 246 2006-05-05  Julian Brown  <julian@codesourcery.com>
 247
 248         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 249         vldm/vstm.
 250
 251 2006-05-05  Thiemo Seufer  <ths@mips.com>
 252             David Ung  <davidu@mips.com>
 253
 254         * mips-opc.c: Add macro for cache instruction.
 255
 256 2006-05-04  Thiemo Seufer  <ths@mips.com>
 257             Nigel Stephens  <nigel@mips.com>
 258             David Ung  <davidu@mips.com>
 259
 260         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 261         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 262         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 263         MIPS64R2.
 264         * mips-opc.c: fix random typos in comments.
 265         (INSN_SMARTMIPS): New defines.
 266         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 267         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 268         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 269         FP_S and FP_D flags to denote single and double register
 270         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 271         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 272         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 273         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 274         release 2 ISAs.
 275         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 276
 277 2006-05-03  Thiemo Seufer  <ths@mips.com>
 278
 279         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 280
 281 2006-05-02  Thiemo Seufer  <ths@mips.com>
 282             Nigel Stephens  <nigel@mips.com>
 283             David Ung  <davidu@mips.com>
 284
 285         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 286         (print_mips16_insn_arg): Force mips16 to odd addresses.
 287
 288 2006-04-30  Thiemo Seufer  <ths@mips.com>
 289             David Ung  <davidu@mips.com>
 290
 291         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 292         "udi0" to "udi15".
 293         * mips-dis.c (print_insn_args): Adds udi argument handling.
 294
 295 2006-04-28  James E Wilson  <wilson@specifix.com>
 296
 297         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 298         error message.
 299
 300 2006-04-28  Thiemo Seufer  <ths@mips.com>
 301             David Ung  <davidu@mips.com>
 302             Nigel Stephens  <nigel@mips.com>
 303
 304         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 305         names.
 306
 307 2006-04-28  Thiemo Seufer  <ths@mips.com>
 308             Nigel Stephens  <nigel@mips.com>
 309             David Ung  <davidu@mips.com>
 310
 311         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 312         (print_insn_mips):  Adjust print_insn_args call.
 313
 314 2006-04-28  Thiemo Seufer  <ths@mips.com>
 315             Nigel Stephens  <nigel@mips.com>
 316
 317         * mips-dis.c (print_insn_args): Print $fcc only for FP
 318         instructions, use $cc elsewise.
 319
 320 2006-04-28  Thiemo Seufer  <ths@mips.com>
 321             Nigel Stephens  <nigel@mips.com>
 322
 323         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 324         Map MIPS16 registers to O32 names.
 325         (print_mips16_insn_arg): Use mips16_reg_names.
 326
 327 2006-04-26  Julian Brown  <julian@codesourcery.com>
 328
 329         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 330         VMOV.
 331
 332 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 333             Julian Brown  <julian@codesourcery.com>
 334
 335         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 336         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 337         Add unified load/store instruction names.
 338         (neon_opcode_table): New.
 339         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 340         (arm_decode_bitfield): New.
 341         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 342         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 343         (print_insn_neon): New.
 344         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 345         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 346         (print_insn_thumb32): Likewise.
 347
 348 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 349
 350         * Makefile.am: Run "make dep-am".
 351         * Makefile.in: Regenerate.
 352
 353 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 354
 355         * avr-dis.c (avr_operand): Warning fix.
 356
 357         * configure: Regenerate.
 358
 359 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 360
 361         * po/POTFILES.in: Regenerated.
 362
 363 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 364
 365         PR binutils/2454
 366         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 367         the symolic form of an address, so that the output of objdump -d
 368         can be reassembled.
 369
 370 2006-04-10  DJ Delorie  <dj@redhat.com>
 371
 372         * m32c-asm.c: Regenerate.
 373
 374 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 375
 376         * Makefile.am: Add install-html target.
 377         * Makefile.in: Regenerate.
 378
 379 2006-04-06  Nick Clifton  <nickc@redhat.com>
 380
 381         * po/vi/po: Updated Vietnamese translation.
 382
 383 2006-03-31  Paul Koning  <ni1d@arrl.net>
 384
 385         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 386
 387 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 388
 389         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 390         logic to identify halfword shifts.
 391
 392 2006-03-16  Paul Brook  <paul@codesourcery.com>
 393
 394         * arm-dis.c (arm_opcodes): Rename swi to svc.
 395         (thumb_opcodes): Ditto.
 396
 397 2006-03-13  DJ Delorie  <dj@redhat.com>
 398
 399         * m32c-asm.c: Regenerate.
 400         * m32c-desc.c: Likewise.
 401         * m32c-desc.h: Likewise.
 402         * m32c-dis.c: Likewise.
 403         * m32c-ibld.c: Likewise.
 404         * m32c-opc.c: Likewise.
 405         * m32c-opc.h: Likewise.
 406
 407 2006-03-10  DJ Delorie  <dj@redhat.com>
 408
 409         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 410         * m32c-opc.c: Likewise.
 411         * m32c-opc.h: Likewise.
 412
 413
 414 2006-03-09  Nick Clifton  <nickc@redhat.com>
 415
 416         * po/sv.po: Updated Swedish translation.
 417
 418 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 419
 420         PR binutils/2428
 421         * i386-dis.c (REP_Fixup): New function.
 422         (AL): Remove duplicate.
 423         (Xbr): New.
 424         (Xvr): Likewise.
 425         (Ybr): Likewise.
 426         (Yvr): Likewise.
 427         (indirDXr): Likewise.
 428         (ALr): Likewise.
 429         (eAXr): Likewise.
 430         (dis386): Updated entries of ins, outs, movs, lods and stos.
 431
 432 2006-03-05  Nick Clifton  <nickc@redhat.com>
 433
 434         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 435         signed 32-bit value into an unsigned 32-bit field when the host is
 436         a 64-bit machine.
 437         * fr30-ibld.c: Regenerate.
 438         * frv-ibld.c: Regenerate.
 439         * ip2k-ibld.c: Regenerate.
 440         * iq2000-asm.c: Regenerate.
 441         * iq2000-ibld.c: Regenerate.
 442         * m32c-ibld.c: Regenerate.
 443         * m32r-ibld.c: Regenerate.
 444         * openrisc-ibld.c: Regenerate.
 445         * xc16x-ibld.c: Regenerate.
 446         * xstormy16-ibld.c: Regenerate.
 447
 448 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 449
 450         * xc16x-asm.c: Regenerate.
 451         * xc16x-dis.c: Regenerate.
 452
 453 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 454
 455         * po/Make-in: Add html target.
 456
 457 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 458
 459         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 460         Intel Merom New Instructions.
 461         (THREE_BYTE_0): Likewise.
 462         (THREE_BYTE_1): Likewise.
 463         (three_byte_table): Likewise.
 464         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 465         THREE_BYTE_1 for entry 0x3a.
 466         (twobyte_has_modrm): Updated.
 467         (twobyte_uses_SSE_prefix): Likewise.
 468         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 469         Instructions.
 470
 471 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 472
 473         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 474         (v9_hpriv_reg_names): New table.
 475         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 476         New cases '$' and '%' for read/write hyperprivileged register.
 477         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 478         window handling and rdhpr/wrhpr instructions.
 479
 480 2006-02-24  DJ Delorie  <dj@redhat.com>
 481
 482         * m32c-desc.c: Regenerate with linker relaxation attributes.
 483         * m32c-desc.h: Likewise.
 484         * m32c-dis.c: Likewise.
 485         * m32c-opc.c: Likewise.
 486
 487 2006-02-24  Paul Brook  <paul@codesourcery.com>
 488
 489         * arm-dis.c (arm_opcodes): Add V7 instructions.
 490         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 491         (print_arm_address): New function.
 492         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 493         (psr_name): New function.
 494         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 495
 496 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 497
 498         * ia64-opc-i.c (bXc): New.
 499         (mXc): Likewise.
 500         (OpX2TaTbYaXcC): Likewise.
 501         (TF). Likewise.
 502         (TFCM). Likewise.
 503         (ia64_opcodes_i): Add instructions for tf.
 504
 505         * ia64-opc.h (IMMU5b): New.
 506
 507         * ia64-asmtab.c: Regenerated.
 508
 509 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 510
 511         * ia64-gen.c: Update copyright years.
 512         * ia64-opc-b.c: Likewise.
 513
 514 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 515
 516         * ia64-gen.c (lookup_regindex): Handle ".vm".
 517         (print_dependency_table): Handle '\"'.
 518
 519         * ia64-ic.tbl: Updated from SDM 2.2.
 520         * ia64-raw.tbl: Likewise.
 521         * ia64-waw.tbl: Likewise.
 522         * ia64-asmtab.c: Regenerated.
 523
 524         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 525
 526 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 527             Anil Paranjape   <anilp1@kpitcummins.com>
 528             Shilin Shakti    <shilins@kpitcummins.com>
 529
 530         * xc16x-desc.h: New file
 531         * xc16x-desc.c: New file
 532         * xc16x-opc.h: New file
 533         * xc16x-opc.c: New file
 534         * xc16x-ibld.c: New file
 535         * xc16x-asm.c: New file
 536         * xc16x-dis.c: New file
 537         * Makefile.am: Entries for xc16x
 538         * Makefile.in: Regenerate
 539         * cofigure.in: Add xc16x target information.
 540         * configure: Regenerate.
 541         * disassemble.c: Add xc16x target information.
 542
 543 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 544
 545         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 546         moves.
 547
 548 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         * i386-dis.c ('Z'): Add a new macro.
 551         (dis386_twobyte): Use "movZ" for control register moves.
 552
 553 2006-02-10  Nick Clifton  <nickc@redhat.com>
 554
 555         * iq2000-asm.c: Regenerate.
 556
 557 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 558
 559         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 560
 561 2006-01-26  David Ung  <davidu@mips.com>
 562
 563         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 564         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 565         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 566         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 567         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 568
 569 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 570
 571         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 572         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 573         disassembled.
 574         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 575         buffer overflows when disassembling instructions like
 576         ld (ix+123),0x23
 577         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 578         operand, if the offset is negative.
 579
 580 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 581
 582         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 583         unsigned char to hold data to be disassembled.
 584
 585 2006-01-17  Andreas Schwab  <schwab@suse.de>
 586
 587         PR binutils/1486
 588         * disassemble.c (disassemble_init_for_target): Set
 589         disassembler_needs_relocs for bfd_arch_arm.
 590
 591 2006-01-16  Paul Brook  <paul@codesourcery.com>
 592
 593         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 594         f?add?, and f?sub? instructions.
 595
 596 2006-01-16  Nick Clifton  <nickc@redhat.com>
 597
 598         * po/zh_CN.po: New Chinese (simplified) translation.
 599         * configure.in (ALL_LINGUAS): Add "zh_CH".
 600         * configure: Regenerate.
 601
 602 2006-01-05  Paul Brook  <paul@codesourcery.com>
 603
 604         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 605
 606 2006-01-06  DJ Delorie  <dj@redhat.com>
 607
 608         * m32c-desc.c: Regenerate.
 609         * m32c-opc.c: Regenerate.
 610         * m32c-opc.h: Regenerate.
 611
 612 2006-01-03  DJ Delorie  <dj@redhat.com>
 613
 614         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 615         * m32c-ibld.c: Regenerated.
 616
 617 For older changes see ChangeLog-2005
 618 \f
 619 Local Variables:
 620 mode: change-log
 621 left-margin: 8
 622 fill-column: 74
 623 version-control: never
 624 End: