opcodes/ChangeLog

   1 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
   4         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
   5         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
   6         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
   7         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
   8         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
   9         (OP_SVE_V_HSD): New macros.
  10         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
  11         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
  12         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
  13         (aarch64_opcode_table): Add new SVE instructions.
  14         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
  15         for rotation operands.  Add new SVE operands.
  16         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
  17         (ins_sve_quad_index): Likewise.
  18         (ins_imm_rotate): Split into...
  19         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
  20         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
  21         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
  22         functions.
  23         (aarch64_ins_sve_addr_ri_s4): New function.
  24         (aarch64_ins_sve_quad_index): Likewise.
  25         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
  26         * aarch64-asm-2.c: Regenerate.
  27         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
  28         (ext_sve_quad_index): Likewise.
  29         (ext_imm_rotate): Split into...
  30         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
  31         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
  32         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
  33         functions.
  34         (aarch64_ext_sve_addr_ri_s4): New function.
  35         (aarch64_ext_sve_quad_index): Likewise.
  36         (aarch64_ext_sve_index): Allow quad indices.
  37         (do_misc_decoding): Likewise.
  38         * aarch64-dis-2.c: Regenerate.
  39         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
  40         aarch64_field_kinds.
  41         (OPD_F_OD_MASK): Widen by one bit.
  42         (OPD_F_NO_ZR): Bump accordingly.
  43         (get_operand_field_width): New function.
  44         * aarch64-opc.c (fields): Add new SVE fields.
  45         (operand_general_constraint_met_p): Handle new SVE operands.
  46         (aarch64_print_operand): Likewise.
  47         * aarch64-opc-2.c: Regenerate.
  48
  49 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
  50
  51         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
  52         (aarch64_feature_compnum): ...this.
  53         (SIMD_V8_3): Replace with...
  54         (COMPNUM): ...this.
  55         (CNUM_INSN): New macro.
  56         (aarch64_opcode_table): Use it for the complex number instructions.
  57
  58 2017-02-24  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
  61
  62 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
  63
  64         Add support for associating SPARC ASIs with an architecture level.
  65         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
  66         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
  67         decoding of SPARC ASIs.
  68
  69 2017-02-23  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
  72         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
  73
  74 2017-02-21  Jan Beulich  <jbeulich@suse.com>
  75
  76         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
  77         1 (instead of to itself). Correct typo.
  78
  79 2017-02-14  Andrew Waterman  <andrew@sifive.com>
  80
  81         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
  82         pseudoinstructions.
  83
  84 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
  85
  86         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
  87         (aarch64_sys_reg_supported_p): Handle them.
  88
  89 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
  90
  91         * arc-opc.c (UIMM6_20R): Define.
  92         (SIMM12_20): Use above.
  93         (SIMM12_20R): Define.
  94         (SIMM3_5_S): Use above.
  95         (UIMM7_A32_11R_S): Define.
  96         (UIMM7_9_S): Use above.
  97         (UIMM3_13R_S): Define.
  98         (SIMM11_A32_7_S): Use above.
  99         (SIMM9_8R): Define.
 100         (UIMM10_A32_8_S): Use above.
 101         (UIMM8_8R_S): Define.
 102         (W6): Use above.
 103         (arc_relax_opcodes): Use all above defines.
 104
 105 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 106
 107         * arc-regs.h: Distinguish some of the registers different on
 108         ARC700 and HS38 cpus.
 109
 110 2017-02-14  Alan Modra  <amodra@gmail.com>
 111
 112         PR 21118
 113         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 114         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 115
 116 2017-02-11  Stafford Horne  <shorne@gmail.com>
 117             Alan Modra  <amodra@gmail.com>
 118
 119         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 120         Use insn_bytes_value and insn_int_value directly instead.  Don't
 121         free allocated memory until function exit.
 122
 123 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 124
 125         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 126
 127 2017-02-03  Nick Clifton  <nickc@redhat.com>
 128
 129         PR 21096
 130         * aarch64-opc.c (print_register_list): Ensure that the register
 131         list index will fir into the tb buffer.
 132         (print_register_offset_address): Likewise.
 133         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 134
 135 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 136
 137         PR 21056
 138         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 139         instructions when the previous fetch packet ends with a 32-bit
 140         instruction.
 141
 142 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 143
 144         * pru-opc.c: Remove vague reference to a future GDB port.
 145
 146 2017-01-20  Nick Clifton  <nickc@redhat.com>
 147
 148         * po/ga.po: Updated Irish translation.
 149
 150 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 151
 152         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 153
 154 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 155
 156         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 157         if FETCH_DATA returns 0.
 158         (m68k_scan_mask): Likewise.
 159         (print_insn_m68k): Update code to handle -1 return value.
 160
 161 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 162
 163         * m68k-dis.c (enum print_insn_arg_error): New.
 164         (NEXTBYTE): Replace -3 with
 165         PRINT_INSN_ARG_MEMORY_ERROR.
 166         (NEXTULONG): Likewise.
 167         (NEXTSINGLE): Likewise.
 168         (NEXTDOUBLE): Likewise.
 169         (NEXTDOUBLE): Likewise.
 170         (NEXTPACKED): Likewise.
 171         (FETCH_ARG): Likewise.
 172         (FETCH_DATA): Update comments.
 173         (print_insn_arg): Update comments. Replace magic numbers with
 174         enum.
 175         (match_insn_m68k): Likewise.
 176
 177 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 178
 179         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 180         * i386-dis-evex.h (evex_table): Updated.
 181         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 182         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 183         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 184         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 185         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 186         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 187         * i386-init.h: Regenerate.
 188         * i386-tbl.h: Ditto.
 189
 190 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 191
 192         * msp430-dis.c (msp430_singleoperand): Return -1 if
 193         msp430dis_opcode_signed returns false.
 194         (msp430_doubleoperand): Likewise.
 195         (msp430_branchinstr): Return -1 if
 196         msp430dis_opcode_unsigned returns false.
 197         (msp430x_calla_instr): Likewise.
 198         (print_insn_msp430): Likewise.
 199
 200 2017-01-05  Nick Clifton  <nickc@redhat.com>
 201
 202         PR 20946
 203         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 204         could not be matched.
 205         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 206         NULL.
 207
 208 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 209
 210         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 211         (aarch64_opcode_table): Use RCPC_INSN.
 212
 213 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 214
 215         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 216         extension.
 217         * riscv-opcodes/all-opcodes: Likewise.
 218
 219 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 220
 221         * riscv-dis.c (print_insn_args): Add fall through comment.
 222
 223 2017-01-03  Nick Clifton  <nickc@redhat.com>
 224
 225         * po/sr.po: New Serbian translation.
 226         * configure.ac (ALL_LINGUAS): Add sr.
 227         * configure: Regenerate.
 228
 229 2017-01-02  Alan Modra  <amodra@gmail.com>
 230
 231         * epiphany-desc.h: Regenerate.
 232         * epiphany-opc.h: Regenerate.
 233         * fr30-desc.h: Regenerate.
 234         * fr30-opc.h: Regenerate.
 235         * frv-desc.h: Regenerate.
 236         * frv-opc.h: Regenerate.
 237         * ip2k-desc.h: Regenerate.
 238         * ip2k-opc.h: Regenerate.
 239         * iq2000-desc.h: Regenerate.
 240         * iq2000-opc.h: Regenerate.
 241         * lm32-desc.h: Regenerate.
 242         * lm32-opc.h: Regenerate.
 243         * m32c-desc.h: Regenerate.
 244         * m32c-opc.h: Regenerate.
 245         * m32r-desc.h: Regenerate.
 246         * m32r-opc.h: Regenerate.
 247         * mep-desc.h: Regenerate.
 248         * mep-opc.h: Regenerate.
 249         * mt-desc.h: Regenerate.
 250         * mt-opc.h: Regenerate.
 251         * or1k-desc.h: Regenerate.
 252         * or1k-opc.h: Regenerate.
 253         * xc16x-desc.h: Regenerate.
 254         * xc16x-opc.h: Regenerate.
 255         * xstormy16-desc.h: Regenerate.
 256         * xstormy16-opc.h: Regenerate.
 257
 258 2017-01-02  Alan Modra  <amodra@gmail.com>
 259
 260         Update year range in copyright notice of all files.
 261
 262 For older changes see ChangeLog-2016
 263 \f
 264 Copyright (C) 2017 Free Software Foundation, Inc.
 265
 266 Copying and distribution of this file, with or without modification,
 267 are permitted in any medium without royalty provided the copyright
 268 notice and this notice are preserved.
 269
 270 Local Variables:
 271 mode: change-log
 272 left-margin: 8
 273 fill-column: 74
 274 version-control: never
 275 End: