opcodes/ChangeLog

   1 2011-12-08  Andrew Pinski  <apinski@cavium.com>
   2
   3         * mips-opc.c (mips_builtin_opcodes): Add "pause".
   4
   5 2011-12-08  Andrew Pinski  <apinski@cavium.com>
   6             Adam Nemet  <anemet@caviumnetworks.com>
   7
   8         * mips-dis.c (mips_arch_choices): Add Octeon2.
   9         For "octeon+", just include OcteonP for the insn.
  10         * mips-opc.c (IOCT): Include Octeon2.
  11         (IOCTP): Include Octeon2.
  12         (IOCT2): New macro.
  13         (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
  14         "ladd", "lai", "laid", "las", "lasd", "law", "lawd".
  15         Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
  16         loads are, and add IOCT2 to them.
  17         Add "lbx" and "lhux".
  18         Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
  19         "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
  20         Add "zcb" and "zcbt".
  21
  22 2011-11-29  Andrew Pinski  <apinski@cavium.com>
  23
  24         * mips-dis.c (mips_arch_choices): Add Octeon+.
  25         * mips-opc.c (IOCT): Include Octeon+.
  26         (IOCTP): New macro.
  27         (mips_builtin_opcodes): Add "saa" and "saad".
  28
  29 2011-11-25  Pierre Muller  <muller@ics.u-strasbg.fr>
  30
  31         * mips-dis.c (print_insn_micromips): Rename local variable iprintf
  32         to infprintf to avoid shadow warning.
  33
  34 2011-11-25  Nick Clifton  <nickc@redhat.com>
  35
  36         * po/it.po: Updated Italian translation.
  37
  38 2011-11-16  Maciej W. Rozycki  <macro@codesourcery.com>
  39
  40         * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
  41         for "alnv.ps".
  42
  43 2011-11-02  Nick Clifton  <nickc@redhat.com>
  44
  45         * po/it.po: New Italian translation.
  46         * configure.in (ALL_LINGUAS): Add it.
  47         * configure: Regenerate.
  48         * po/opcodes.pot: Regenerate.
  49
  50 2011-11-01  DJ Delorie  <dj@redhat.com>
  51
  52         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
  53         rl78-dis.c.
  54         (MAINTAINERCLEANFILES): Add rl78-decode.c.
  55         (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
  56         * Makefile.in: Regenerate.
  57         * configure.in: Add bfd_rl78_arch case.
  58         * configure: Regenerate.
  59         * disassemble.c: Define ARCH_rl78.
  60         (disassembler): Add ARCH_rl78 case.
  61         * rl78-decode.c: New file.
  62         * rl78-decode.opc: New file.
  63         * rl78-dis.c: New file.
  64
  65 2011-10-27  Peter Bergner  <bergner@vnet.ibm.com>
  66
  67         * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
  68         dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
  69         diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
  70         instructions.
  71
  72 2011-10-26  Nick Clifton  <nickc@redhat.com>
  73
  74         PR binutils/13348
  75         * i386-dis.c (print_insn): Fix testing of array subscript.
  76
  77 2011-10-26  Joern Rennecke  <joern.rennecke@embecosm.com>
  78
  79         * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
  80         * epiphany-asm.c, epiphany-opc.h: Regenerate.
  81
  82 2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
  83
  84         * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
  85         (TARGET_LIBOPCODES_CFILES): Add  epiphany-asm.c, epiphany-desc.c,
  86         epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
  87         (CLEANFILES): Add stamp-epiphany.
  88         (EPIPHANY_DEPS): Set.  Make CGEN-generated Epiphany files depend on it.
  89         (stamp-epiphany): New rule.
  90         * configure.in: Handle bfd_epiphany_arch.
  91         * disassemble.c (ARCH_epiphany): Define.
  92         (disassembler): Handle bfd_arch_epiphany.
  93         * epiphany-asm.c: New file.
  94         * epiphany-desc.c: New file.
  95         * epiphany-desc.h: New file.
  96         * epiphany-dis.c: New file.
  97         * epiphany-ibld.c: New file.
  98         * epiphany-opc.c: New file.
  99         * epiphany-opc.h: New file.
 100         * Makefile.in: Regenerate.
 101         * configure: Regenerate.
 102         * po/POTFILES.in: Regenerate.
 103         * po/opcodes.pot: Regenerate.
 104
 105 2011-10-24  Julian Brown  <julian@codesourcery.com>
 106
 107         * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
 108
 109 2011-10-21  Jan Glauber  <jang@linux.vnet.ibm.com>
 110
 111         * s390-opc.txt: Add CPUMF instructions.
 112
 113 2011-10-18  Jie Zhang  <jie@codesourcery.com>
 114             Julian Brown  <julian@codesourcery.com>
 115
 116         * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
 117
 118 2011-10-10  Nick Clifton  <nickc@redhat.com>
 119
 120         * po/es.po: Updated Spanish translation.
 121         * po/fi.po: Updated Finnish translation.
 122
 123 2011-09-28  Jan Beulich  <jbeulich@suse.com>
 124
 125         * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
 126         RBX): New.
 127         (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
 128         (powerpc_opcodes): Use RAX for second and RBXC for third operand of
 129         lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
 130         lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
 131         mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
 132         on DFP quad instructions.
 133
 134 2011-09-27  David S. Miller  <davem@davemloft.net>
 135
 136         * sparc-opc.c (sparc_opcodes): Fix random instruction to write
 137         to a float instead of an integer register.
 138
 139 2011-09-26  David S. Miller  <davem@davemloft.net>
 140
 141         * sparc-opc.c (sparc_opcodes): Add integer multiply-add
 142         instructions.
 143
 144 2011-09-21  David S. Miller  <davem@davemloft.net>
 145
 146         * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
 147         bits.  Fix "fchksm16" mnemonic.
 148
 149 2011-09-08  Mark Fortescue <mark@mtfhpc.demon.co.uk>
 150
 151         The changes below bring 'mov' and 'ticc' instructions into line
 152         with the V8 SPARC Architecture Manual.
 153         * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
 154         * sparc-opc.c (sparc_opcodes): Add alias entries for
 155         'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
 156         'mov regrs2,%wim' and 'mov regrs2,%tbr'.
 157         * sparc-opc.c (sparc_opcodes): Move/Change entries for
 158         'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
 159         and 'mov imm,%tbr'.
 160         * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
 161         mov aliases.
 162
 163         * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
 164         This has been reported as being accepted by the Sun assmebler.
 165
 166 2011-09-08  David S. Miller  <davem@davemloft.net>
 167
 168         * sparc-opc.c (pdistn): Destination is integer not float register.
 169
 170 2011-09-07  Andreas Schwab  <schwab@linux-m68k.org>
 171
 172         PR gas/13145
 173         * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
 174
 175 2011-08-26  Nick Clifton  <nickc@redhat.com>
 176
 177         * po/es.po: Updated Spanish translation.
 178
 179 2011-08-22  Nick Clifton  <nickc@redhat.com>
 180
 181         * Makefile.am (CPUDIR): Redfine to point to top level cpu
 182         directory.
 183         (stamp-frv): Use CPUDIR.
 184         (stamp-iq2000): Likewise.
 185         (stamp-lm32): Likewise.
 186         (stamp-m32c): Likewise.
 187         (stamp-mt): Likewise.
 188         (stamp-xc16x): Likewise.
 189         * Makefile.in: Regenerate.
 190
 191 2011-08-09  Chao-ying Fu  <fu@mips.com>
 192             Maciej W. Rozycki  <macro@codesourcery.com>
 193
 194         * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
 195         and "mips64r2".
 196         (print_insn_args, print_insn_micromips): Handle MCU.
 197         * micromips-opc.c (MC): New macro.
 198         (micromips_opcodes): Add "aclr", "aset" and "iret".
 199         * mips-opc.c (MC): New macro.
 200         (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
 201
 202 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 203
 204         * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
 205         (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
 206         (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
 207         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
 208         (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
 209         (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
 210         (WR_s): Update macro.
 211         (micromips_opcodes): Update register use flags of: "addiu",
 212         "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
 213         "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
 214         "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
 215         "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
 216         "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
 217         "swm" and "xor" instructions.
 218
 219 2011-08-05  David S. Miller  <davem@davemloft.net>
 220
 221         * sparc-dis.c (v9a_ast_reg_names): Add "cps".
 222         (X_RS3): New macro.
 223         (print_insn_sparc): Handle '4', '5', and '(' format codes.
 224         Accept %asr numbers below 28.
 225         * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
 226         instructions.
 227
 228 2011-08-02  Quentin Neill  <quentin.neill@amd.com>
 229
 230         * i386-dis.c (xop_table): Remove spurious bextr insn.
 231
 232 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 233
 234         PR ld/13048
 235         * i386-dis.c (print_insn): Optimize info->mach check.
 236
 237 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 238
 239         PR gas/13046
 240         * i386-opc.tbl: Add Disp32S to 64bit call.
 241         * i386-tbl.h: Regenerated.
 242
 243 2011-07-24  Chao-ying Fu  <fu@mips.com>
 244             Maciej W. Rozycki  <macro@codesourcery.com>
 245
 246         * micromips-opc.c: New file.
 247         * mips-dis.c (micromips_to_32_reg_b_map): New array.
 248         (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
 249         (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
 250         (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
 251         (micromips_to_32_reg_q_map): Likewise.
 252         (micromips_imm_b_map, micromips_imm_c_map): Likewise.
 253         (micromips_ase): New variable.
 254         (is_micromips): New function.
 255         (set_default_mips_dis_options): Handle microMIPS ASE.
 256         (print_insn_micromips): New function.
 257         (is_compressed_mode_p): Likewise.
 258         (_print_insn_mips): Handle microMIPS instructions.
 259         * Makefile.am (CFILES): Add micromips-opc.c.
 260         * configure.in (bfd_mips_arch): Add micromips-opc.lo.
 261         * Makefile.in: Regenerate.
 262         * configure: Regenerate.
 263
 264         * mips-dis.c (micromips_to_32_reg_h_map): New variable.
 265         (micromips_to_32_reg_i_map): Likewise.
 266         (micromips_to_32_reg_m_map): Likewise.
 267         (micromips_to_32_reg_n_map): New macro.
 268
 269 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 270
 271         * mips-opc.c (NODS): New macro.
 272         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 273         (DSP_VOLA): Likewise.
 274         (mips_builtin_opcodes): Add NODS annotation to "deret" and
 275         "eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
 276         place of TRAP for "wait", "waiti" and "yield".
 277         * mips16-opc.c (NODS): New macro.
 278         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 279         (mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
 280         "restore" and "save".
 281
 282 2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 283
 284         * configure.in: Handle bfd_k1om_arch.
 285         * configure: Regenerated.
 286
 287         * disassemble.c (disassembler): Handle bfd_k1om_arch.
 288
 289         * i386-dis.c (print_insn): Handle bfd_mach_k1om and
 290         bfd_mach_k1om_intel_syntax.
 291
 292         * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
 293         ~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
 294         (cpu_flags): Add CpuK1OM.
 295
 296         * i386-opc.h (CpuK1OM): New.
 297         (i386_cpu_flags): Add cpuk1om.
 298
 299         * i386-init.h: Regenerated.
 300         * i386-tbl.h: Likewise.
 301
 302 2011-07-12  Nick Clifton  <nickc@redhat.com>
 303
 304         * arm-dis.c (print_insn_arm): Revert previous, undocumented,
 305         accidental change.
 306
 307 2011-07-01  Nick Clifton  <nickc@redhat.com>
 308
 309         PR binutils/12329
 310         * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
 311         insns using post-increment addressing.
 312
 313 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         * i386-dis.c (vex_len_table): Update rorxS.
 316
 317 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         AVX Programming Reference (June, 2011)
 320         * i386-dis.c (vex_len_table): Correct rorxS.
 321
 322         * i386-opc.tbl: Correct rorx.
 323         * i386-tbl.h: Regenerated.
 324
 325 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
 326
 327         * tilegx-opc.c (find_opcode): Replace "index" with "i".
 328         * tilepro-opc.c (find_opcode): Likewise.
 329
 330 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
 331
 332         * mips16-opc.c (jalrc, jrc): Move earlier in file.
 333
 334 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 335
 336         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
 337         PREFIX_VEX_0F388E.
 338
 339 2011-06-17  Andreas Schwab  <schwab@redhat.com>
 340
 341         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
 342         (MOSTLYCLEANFILES): ... here.
 343         * Makefile.in: Regenerate.
 344
 345 2011-06-14  Alan Modra  <amodra@gmail.com>
 346
 347         * Makefile.in: Regenerate.
 348
 349 2011-06-13  Walter Lee  <walt@tilera.com>
 350
 351         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
 352         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
 353         * Makefile.in: Regenerate.
 354         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
 355         * configure: Regenerate.
 356         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
 357         * po/POTFILES.in: Regenerate.
 358         * tilegx-dis.c: New file.
 359         * tilegx-opc.c: New file.
 360         * tilepro-dis.c: New file.
 361         * tilepro-opc.c: New file.
 362
 363 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 364
 365         AVX Programming Reference (June, 2011)
 366         * i386-dis.c (XMGatherQ): New.
 367         * i386-dis.c (EXxmm_mb): New.
 368         (EXxmm_mb): Likewise.
 369         (EXxmm_mw): Likewise.
 370         (EXxmm_md): Likewise.
 371         (EXxmm_mq): Likewise.
 372         (EXxmmdw): Likewise.
 373         (EXxmmqd): Likewise.
 374         (VexGatherQ): Likewise.
 375         (MVexVSIBDWpX): Likewise.
 376         (MVexVSIBQWpX): Likewise.
 377         (xmm_mb_mode): Likewise.
 378         (xmm_mw_mode): Likewise.
 379         (xmm_md_mode): Likewise.
 380         (xmm_mq_mode): Likewise.
 381         (xmmdw_mode): Likewise.
 382         (xmmqd_mode): Likewise.
 383         (ymmxmm_mode): Likewise.
 384         (vex_vsib_d_w_dq_mode): Likewise.
 385         (vex_vsib_q_w_dq_mode): Likewise.
 386         (MOD_VEX_0F385A_PREFIX_2): Likewise.
 387         (MOD_VEX_0F388C_PREFIX_2): Likewise.
 388         (MOD_VEX_0F388E_PREFIX_2): Likewise.
 389         (PREFIX_0F3882): Likewise.
 390         (PREFIX_VEX_0F3816): Likewise.
 391         (PREFIX_VEX_0F3836): Likewise.
 392         (PREFIX_VEX_0F3845): Likewise.
 393         (PREFIX_VEX_0F3846): Likewise.
 394         (PREFIX_VEX_0F3847): Likewise.
 395         (PREFIX_VEX_0F3858): Likewise.
 396         (PREFIX_VEX_0F3859): Likewise.
 397         (PREFIX_VEX_0F385A): Likewise.
 398         (PREFIX_VEX_0F3878): Likewise.
 399         (PREFIX_VEX_0F3879): Likewise.
 400         (PREFIX_VEX_0F388C): Likewise.
 401         (PREFIX_VEX_0F388E): Likewise.
 402         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
 403         (PREFIX_VEX_0F38F5): Likewise.
 404         (PREFIX_VEX_0F38F6): Likewise.
 405         (PREFIX_VEX_0F3A00): Likewise.
 406         (PREFIX_VEX_0F3A01): Likewise.
 407         (PREFIX_VEX_0F3A02): Likewise.
 408         (PREFIX_VEX_0F3A38): Likewise.
 409         (PREFIX_VEX_0F3A39): Likewise.
 410         (PREFIX_VEX_0F3A46): Likewise.
 411         (PREFIX_VEX_0F3AF0): Likewise.
 412         (VEX_LEN_0F3816_P_2): Likewise.
 413         (VEX_LEN_0F3819_P_2): Likewise.
 414         (VEX_LEN_0F3836_P_2): Likewise.
 415         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 416         (VEX_LEN_0F38F5_P_0): Likewise.
 417         (VEX_LEN_0F38F5_P_1): Likewise.
 418         (VEX_LEN_0F38F5_P_3): Likewise.
 419         (VEX_LEN_0F38F6_P_3): Likewise.
 420         (VEX_LEN_0F38F7_P_1): Likewise.
 421         (VEX_LEN_0F38F7_P_2): Likewise.
 422         (VEX_LEN_0F38F7_P_3): Likewise.
 423         (VEX_LEN_0F3A00_P_2): Likewise.
 424         (VEX_LEN_0F3A01_P_2): Likewise.
 425         (VEX_LEN_0F3A38_P_2): Likewise.
 426         (VEX_LEN_0F3A39_P_2): Likewise.
 427         (VEX_LEN_0F3A46_P_2): Likewise.
 428         (VEX_LEN_0F3AF0_P_3): Likewise.
 429         (VEX_W_0F3816_P_2): Likewise.
 430         (VEX_W_0F3818_P_2): Likewise.
 431         (VEX_W_0F3819_P_2): Likewise.
 432         (VEX_W_0F3836_P_2): Likewise.
 433         (VEX_W_0F3846_P_2): Likewise.
 434         (VEX_W_0F3858_P_2): Likewise.
 435         (VEX_W_0F3859_P_2): Likewise.
 436         (VEX_W_0F385A_P_2_M_0): Likewise.
 437         (VEX_W_0F3878_P_2): Likewise.
 438         (VEX_W_0F3879_P_2): Likewise.
 439         (VEX_W_0F3A00_P_2): Likewise.
 440         (VEX_W_0F3A01_P_2): Likewise.
 441         (VEX_W_0F3A02_P_2): Likewise.
 442         (VEX_W_0F3A38_P_2): Likewise.
 443         (VEX_W_0F3A39_P_2): Likewise.
 444         (VEX_W_0F3A46_P_2): Likewise.
 445         (MOD_VEX_0F3818_PREFIX_2): Removed.
 446         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 447         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 448         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 449         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 450         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 451         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 452         (VEX_LEN_0F3A0E_P_2): Likewise.
 453         (VEX_LEN_0F3A0F_P_2): Likewise.
 454         (VEX_LEN_0F3A42_P_2): Likewise.
 455         (VEX_LEN_0F3A4C_P_2): Likewise.
 456         (VEX_W_0F3818_P_2_M_0): Likewise.
 457         (VEX_W_0F3819_P_2_M_0): Likewise.
 458         (prefix_table): Updated.
 459         (three_byte_table): Likewise.
 460         (vex_table): Likewise.
 461         (vex_len_table): Likewise.
 462         (vex_w_table): Likewise.
 463         (mod_table): Likewise.
 464         (putop): Handle "LW".
 465         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 466         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 467         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 468         (OP_EX): Likewise.
 469         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 470         vex_vsib_q_w_dq_mode.
 471         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 472         (OP_VEX): Likewise.
 473
 474         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 475         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 476         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 477         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 478         (opcode_modifiers): Add VecSIB.
 479
 480         * i386-opc.h (CpuAVX2): New.
 481         (CpuBMI2): Likewise.
 482         (CpuLZCNT): Likewise.
 483         (CpuINVPCID): Likewise.
 484         (VecSIB128): Likewise.
 485         (VecSIB256): Likewise.
 486         (VecSIB): Likewise.
 487         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 488         (i386_opcode_modifier): Add vecsib.
 489
 490         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 491         * i386-init.h: Regenerated.
 492         * i386-tbl.h: Likewise.
 493
 494 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 495
 496         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 497         * i386-init.h: Regenerated.
 498
 499 2011-06-03  Nick Clifton  <nickc@redhat.com>
 500
 501         PR binutils/12752
 502         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 503         computing address offsets.
 504         (print_arm_address): Likewise.
 505         (print_insn_arm): Likewise.
 506         (print_insn_thumb16): Likewise.
 507         (print_insn_thumb32): Likewise.
 508
 509 2011-06-02  Jie Zhang <jie@codesourcery.com>
 510             Nathan Sidwell <nathan@codesourcery.com>
 511             Maciej Rozycki <macro@codesourcery.com>
 512
 513         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 514         as address offset.
 515         (print_arm_address): Likewise. Elide positive #0 appropriately.
 516         (print_insn_arm): Likewise.
 517
 518 2011-06-02  Nick Clifton  <nickc@redhat.com>
 519
 520         PR gas/12752
 521         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 522         passed to print_address_func.
 523
 524 2011-06-02  Nick Clifton  <nickc@redhat.com>
 525
 526         * arm-dis.c: Fix spelling mistakes.
 527         * op/opcodes.pot: Regenerate.
 528
 529 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 530
 531         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 532         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 533         * s390-opc.txt: Fix cxr instruction type.
 534
 535 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 536
 537         * s390-opc.c: Add new instruction types marking register pair
 538         operands.
 539         * s390-opc.txt: Match instructions having register pair operands
 540         to the new instruction types.
 541
 542 2011-05-19  Nick Clifton  <nickc@redhat.com>
 543
 544         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 545         operands.
 546
 547 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 548
 549         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 550         * i386-init.h: Regenerated.
 551
 552 2011-04-27  Nick Clifton  <nickc@redhat.com>
 553
 554         * po/da.po: Updated Danish translation.
 555
 556 2011-04-26  Anton Blanchard  <anton@samba.org>
 557
 558         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 559
 560 2011-04-21  DJ Delorie  <dj@redhat.com>
 561
 562         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 563         * rx-decode.c: Regenerate.
 564
 565 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 566
 567         * i386-init.h: Regenerated.
 568
 569 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 570
 571         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 572         from bdver1 flags.
 573
 574 2011-04-13  Nick Clifton  <nickc@redhat.com>
 575
 576         * v850-dis.c (disassemble): Always print a closing square brace if
 577         an opening square brace was printed.
 578
 579 2011-04-12  Nick Clifton  <nickc@redhat.com>
 580
 581         PR binutils/12534
 582         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 583         patterns.
 584         (print_insn_thumb32): Handle %L.
 585
 586 2011-04-11  Julian Brown  <julian@codesourcery.com>
 587
 588         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 589         (print_insn_thumb32): Add APSR bitmask support.
 590
 591 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 592
 593         * arm-dis.c (print_insn): init vars moved into private_data structure.
 594
 595 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 596
 597         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 598
 599 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 600
 601         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 602         post-increment to support LPM Z+ instruction. Add support for 'E'
 603         constraint for DES instruction.
 604         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 605
 606 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 607
 608         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 609
 610 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 611
 612         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 613         Use branch types instead.
 614         (print_insn): Likewise.
 615
 616 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 617
 618         * mips-opc.c (mips_builtin_opcodes): Correct register use
 619         annotation of "alnv.ps".
 620
 621 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 622
 623         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 624
 625 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 626
 627         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 628
 629 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 630
 631         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 632
 633 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 634
 635         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 636         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 637         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 638         exception, end_of_registers, msize, memory, bfd_mach.
 639         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 640         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 641         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 642         (get_allreg): Change to new defines.  Fallback to abort().
 643
 644 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 645
 646         * bfin-dis.c: Add whitespace/parenthesis where needed.
 647
 648 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 649
 650         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 651         than 7.
 652
 653 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 654
 655         * configure: Regenerate.
 656
 657 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 658
 659         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 660
 661 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 662
 663         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 664         dregs only when P is set, and dregs_lo otherwise.
 665
 666 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 667
 668         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 669
 670 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 671
 672         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 673
 674 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 675
 676         * bfin-dis.c (machine_registers): Delete REG_GP.
 677         (reg_names): Delete "GP".
 678         (decode_allregs): Change REG_GP to REG_LASTREG.
 679
 680 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 681
 682         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 683         M_IH, M_IU): Delete.
 684
 685 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 686
 687         * bfin-dis.c (reg_names): Add const.
 688         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 689         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 690         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 691         decode_counters, decode_allregs): Likewise.
 692
 693 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 694
 695         * i386-dis.c (OP_J): Parenthesize expression to prevent
 696         truncated addresses.
 697         (print_insn): Fix indentation off-by-one.
 698
 699 2011-02-01  Nick Clifton  <nickc@redhat.com>
 700
 701         * po/da.po: Updated Danish translation.
 702
 703 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 704
 705         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 706
 707 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 708
 709         * i386-dis.c (sIbT): New.
 710         (b_T_mode): Likewise.
 711         (dis386): Replace sIb with sIbT on "pushT".
 712         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 713         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 714
 715 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 716
 717         * i386-init.h: Regenerated.
 718         * i386-tbl.h: Regenerated
 719
 720 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 721
 722         * i386-dis.c (REG_XOP_TBM_01): New.
 723         (REG_XOP_TBM_02): New.
 724         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 725         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 726         entries, and add bextr instruction.
 727
 728         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 729         (cpu_flags): Add CpuTBM.
 730
 731         * i386-opc.h (CpuTBM) New.
 732         (i386_cpu_flags): Add bit cputbm.
 733
 734         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 735         blcs, blsfill, blsic, t1mskc, and tzmsk.
 736
 737 2011-01-12  DJ Delorie  <dj@redhat.com>
 738
 739         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 740
 741 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 742
 743         * mips-dis.c (print_insn_args): Adjust the value to print the real
 744         offset for "+c" argument.
 745
 746 2011-01-10  Nick Clifton  <nickc@redhat.com>
 747
 748         * po/da.po: Updated Danish translation.
 749
 750 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 751
 752         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 753
 754 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 755
 756         * i386-dis.c (REG_VEX_38F3): New.
 757         (PREFIX_0FBC): Likewise.
 758         (PREFIX_VEX_38F2): Likewise.
 759         (PREFIX_VEX_38F3_REG_1): Likewise.
 760         (PREFIX_VEX_38F3_REG_2): Likewise.
 761         (PREFIX_VEX_38F3_REG_3): Likewise.
 762         (PREFIX_VEX_38F7): Likewise.
 763         (VEX_LEN_38F2_P_0): Likewise.
 764         (VEX_LEN_38F3_R_1_P_0): Likewise.
 765         (VEX_LEN_38F3_R_2_P_0): Likewise.
 766         (VEX_LEN_38F3_R_3_P_0): Likewise.
 767         (VEX_LEN_38F7_P_0): Likewise.
 768         (dis386_twobyte): Use PREFIX_0FBC.
 769         (reg_table): Add REG_VEX_38F3.
 770         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 771         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 772         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 773         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 774         PREFIX_VEX_38F7.
 775         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 776         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 777         VEX_LEN_38F7_P_0.
 778
 779         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 780         (cpu_flags): Add CpuBMI.
 781
 782         * i386-opc.h (CpuBMI): New.
 783         (i386_cpu_flags): Add cpubmi.
 784
 785         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 786         * i386-init.h: Regenerated.
 787         * i386-tbl.h: Likewise.
 788
 789 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 790
 791         * i386-dis.c (VexGdq): New.
 792         (OP_VEX): Handle dq_mode.
 793
 794 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 795
 796         * i386-gen.c (process_copyright): Update copyright to 2011.
 797
 798 For older changes see ChangeLog-2010
 799 \f
 800 Local Variables:
 801 mode: change-log
 802 left-margin: 8
 803 fill-column: 74
 804 version-control: never
 805 End: