opcodes/ChangeLog

   1 2006-11-01  Mei Ligang  <ligang@sunnorth.com.cn>
   2
   3         * score-opc.h (score_opcodes): Delete modifier '0x'.
   4
   5 2006-10-30  Paul Brook  <paul@codesourcery.com>
   6
   7         * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
   8         (get_sym_code_type): New function.
   9         (print_insn): Search for mapping symbols.
  10
  11 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  12
  13         * score-dis.c (print_insn): Correct the error code to print
  14         correct PCE instruction disassembly.
  15
  16 2006-10-26  Ben Elliston  <bje@au.ibm.com>
  17             Anton Blanchard  <anton@samba.org>
  18             Peter Bergner  <bergner@vnet.ibm.com>
  19
  20         * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
  21         AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
  22         (POWER6): Define.
  23         (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
  24         "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
  25         Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
  26         "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
  27         "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
  28         "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
  29         "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
  30         "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
  31         "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
  32         "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
  33         "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
  34         "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
  35         "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
  36         "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
  37         "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
  38         "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
  39         "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
  40         "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
  41         "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
  42         "diexq" and "diexq." opcodes.
  43
  44 2006-10-26  Daniel Jacobowitz  <dan@codesourcery.com>
  45
  46         * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
  47
  48 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  49             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  50             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  51             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  52             Alan Modra  <amodra@bigpond.net.au>
  53
  54         * spu-dis.c: New file.
  55         * spu-opc.c: New file.
  56         * configure.in: Add SPU support.
  57         * disassemble.c: Likewise.
  58         * Makefile.am: Likewise.  Run "make dep-am".
  59         * Makefile.in: Regenerate.
  60         * configure: Regenerate.
  61         * po/POTFILES.in: Regenerate.
  62
  63 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  64
  65         * ppc-opc.c (CELL): New define.
  66         (powerpc_opcodes): Enable hrfid for Cell.  Add ldbrx and stdbrx,
  67         cell specific instructions.  Add {st,l}x{r,l}{,l} cell specific
  68         VMX instructions.
  69         * ppc-dis.c (powerpc_dialect): Handle cell.
  70
  71 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  72
  73         * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
  74         amdfam10 architecture.
  75         (PREGRP37): NEW.
  76         (print_insn): Disallow REP prefix for POPCNT.
  77
  78 2006-10-20  Andrew Stubbs  <andrew.stubbs@st.com>
  79
  80         * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
  81         duplicating it.
  82
  83 2006-10-18  Dave Brolley  <brolley@redhat.com>
  84
  85         * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
  86         * configure: Regenerated.
  87
  88 2006-09-29  Alan Modra  <amodra@bigpond.net.au>
  89
  90         * po/POTFILES.in: Regenerate.
  91
  92 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  93             Joseph Myers  <joseph@codesourcery.com>
  94             Ian Lance Taylor  <ian@wasabisystems.com>
  95             Ben Elliston  <bje@wasabisystems.com>
  96
  97         * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
  98         only be used with the default multiply-add operation, so if N is
  99         set, don't bother printing X.  Add new iwmmxt instructions.
 100         (IWMMXT_INSN_COUNT): Update.
 101         (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
 102         with a 'c' suffix.
 103         (print_insn_coprocessor): Check for iWMMXt2.  Handle format
 104         specifiers 'r', 'i'.
 105
 106 2006-09-24  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 107
 108         PR binutils/3100
 109         * i386-dis.c (prefix_user_table): Fix the second operand of
 110         maskmovdqu instruction to allow only %xmm register instead of
 111         both %xmm register and memory.
 112
 113 2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
 114
 115         PR binutils/3235
 116         * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
 117         address size prefix.
 118
 119 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 120
 121         * score-dis.c: New file.
 122         * score-opc.h: New file.
 123         * Makefile.am: Add Score files.
 124         * Makefile.in: Regenerate.
 125         * configure.in: Add support for Score target.
 126         * configure: Regenerate.
 127         * disassemble.c: Add support for Score target.
 128
 129 2006-09-16  Nick Clifton  <nickc@redhat.com>
 130             Pedro Alves  <pedro_alves@portugalmail.pt>
 131
 132         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
 133         macros defined in bfd.h.
 134         * cris-dis.c: Likewise.
 135         * h8300-dis.c: Likewise.
 136         * i386-dis.c: Likewise.
 137         * ia64-gen.c: Likewise.
 138         * mips-dis: Likewise.
 139
 140 2006-09-04  Paul Brook  <paul@codesourcery.com>
 141
 142         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
 143
 144 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
 145
 146         * i386-dis.c (three_byte_table): Expand to 256 elements.
 147
 148 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 149
 150         PR binutils/3000
 151         * i386-dis.c (MXC,EMC): Define.
 152         (OP_MXC): New function to handle cvt* (convert instructions) between
 153         %xmm and %mm register correctly.
 154         (OP_EMC): ditto.
 155         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
 156         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
 157         with EMC/MXC.
 158
 159 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
 160
 161         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
 162         "fdaddl" entry.
 163
 164 2006-07-19  Paul Brook  <paul@codesourcery.com>
 165
 166         * armd-dis.c (arm_opcodes): Fix rbit opcode.
 167
 168 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 169
 170         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
 171         "sldt", "str" and "smsw".
 172
 173 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 174
 175         PR binutils/2829
 176         * i386-dis.c (GRP11_C6): NEW.
 177         (GRP11_C7): Likewise.
 178         (GRP12): Updated.
 179         (GRP13): Likewise.
 180         (GRP14): Likewise.
 181         (GRP15): Likewise.
 182         (GRP16): Likewise.
 183         (GRPAMD): Likewise.
 184         (GRPPADLCK1): Likewise.
 185         (GRPPADLCK2): Likewise.
 186         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
 187         respectively.
 188         (grps): Add entries for GRP11_C6 and GRP11_C7.
 189
 190 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 191            Michael Meissner             <michael.meissner@amd.com>
 192
 193         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
 194         support for amdfam10 SSE4a/ABM instructions. Modify all
 195         initializer macros to have additional arguments. Disallow REP
 196         prefix for non-string instructions.
 197         (print_insn): Ditto.
 198
 199 2006-07-05  Julian Brown  <julian@codesourcery.com>
 200
 201         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
 202
 203 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 204
 205         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
 206         (twobyte_has_modrm): Set 1 for 0x1f.
 207
 208 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 209
 210         * i386-dis.c (NOP_Fixup): Removed.
 211         (NOP_Fixup1): New.
 212         (NOP_Fixup2): Likewise.
 213         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 214
 215 2006-06-12  Julian Brown  <julian@codesourcery.com>
 216
 217         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
 218         on 64-bit hosts.
 219
 220 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 221
 222         * i386.c (GRP10): Renamed to ...
 223         (GRP12): This.
 224         (GRP11): Renamed to ...
 225         (GRP13): This.
 226         (GRP12): Renamed to ...
 227         (GRP14): This.
 228         (GRP13): Renamed to ...
 229         (GRP15): This.
 230         (GRP14): Renamed to ...
 231         (GRP16): This.
 232         (dis386_twobyte): Updated.
 233         (grps): Likewise.
 234
 235 2006-06-09  Nick Clifton  <nickc@redhat.com>
 236
 237         * po/fi.po: Updated Finnish translation.
 238
 239 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 240
 241         * po/Make-in (pdf, ps): New dummy targets.
 242
 243 2006-06-06  Paul Brook  <paul@codesourcery.com>
 244
 245         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 246         instructions.
 247         (neon_opcodes): Add conditional execution specifiers.
 248         (thumb_opcodes): Ditto.
 249         (thumb32_opcodes): Ditto.
 250         (arm_conditional): Change 0xe to "al" and add "" to end.
 251         (ifthen_state, ifthen_next_state, ifthen_address): New.
 252         (IFTHEN_COND): Define.
 253         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 254         (print_insn_arm): Change %c to use new values of arm_conditional.
 255         (print_insn_thumb16): Print thumb conditions.  Add %I.
 256         (print_insn_thumb32): Print thumb conditions.
 257         (find_ifthen_state): New function.
 258         (print_insn): Track IT block state.
 259
 260 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 261             Anton Blanchard  <anton@samba.org>
 262             Peter Bergner  <bergner@vnet.ibm.com>
 263
 264         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 265         (print_ppc_disassembler_options): Mention power6.
 266
 267 2006-06-06  Thiemo Seufer  <ths@mips.com>
 268             Chao-ying Fu  <fu@mips.com>
 269
 270         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 271         * mips-opc.c: Add DSP64 instructions.
 272
 273 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 274
 275         * m68hc11-dis.c (print_insn): Warning fix.
 276
 277 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 278
 279         * po/Make-in (top_builddir): Define.
 280
 281 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 282
 283         * Makefile.am: Run "make dep-am".
 284         * Makefile.in: Regenerate.
 285         * config.in: Regenerate.
 286
 287 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 288
 289         * Makefile.am (INCLUDES): Use @INCINTL@.
 290         * acinclude.m4: Include new gettext macros.
 291         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 292         Remove local code for po/Makefile.
 293         * Makefile.in, aclocal.m4, configure: Regenerated.
 294
 295 2006-05-30  Nick Clifton  <nickc@redhat.com>
 296
 297         * po/es.po: Updated Spanish translation.
 298
 299 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 300
 301         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 302         and fmovem entries.  Put register list entries before immediate
 303         mask entries.  Use "l" rather than "L" in the fmovem entries.
 304         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 305         out from INFO.
 306         (m68k_scan_mask): New function, split out from...
 307         (print_insn_m68k): ...here.  If no architecture has been set,
 308         first try printing an m680x0 instruction, then try a Coldfire one.
 309
 310 2006-05-24  Nick Clifton  <nickc@redhat.com>
 311
 312         * po/ga.po: Updated Irish translation.
 313
 314 2006-05-22  Nick Clifton  <nickc@redhat.com>
 315
 316         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 317
 318 2006-05-22  Nick Clifton  <nickc@redhat.com>
 319
 320         * po/nl.po: Updated translation.
 321
 322 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 323
 324         * avr-dis.c: Formatting fix.
 325
 326 2006-05-14  Thiemo Seufer  <ths@mips.com>
 327
 328         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 329         (mips16_opcodes): Change membership of instructions to their
 330         lowest baseline ISA.
 331
 332 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 333
 334         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 335
 336 2006-05-05  Julian Brown  <julian@codesourcery.com>
 337
 338         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 339         vldm/vstm.
 340
 341 2006-05-05  Thiemo Seufer  <ths@mips.com>
 342             David Ung  <davidu@mips.com>
 343
 344         * mips-opc.c: Add macro for cache instruction.
 345
 346 2006-05-04  Thiemo Seufer  <ths@mips.com>
 347             Nigel Stephens  <nigel@mips.com>
 348             David Ung  <davidu@mips.com>
 349
 350         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 351         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 352         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 353         MIPS64R2.
 354         * mips-opc.c: fix random typos in comments.
 355         (INSN_SMARTMIPS): New defines.
 356         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 357         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 358         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 359         FP_S and FP_D flags to denote single and double register
 360         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 361         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 362         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 363         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 364         release 2 ISAs.
 365         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 366
 367 2006-05-03  Thiemo Seufer  <ths@mips.com>
 368
 369         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 370
 371 2006-05-02  Thiemo Seufer  <ths@mips.com>
 372             Nigel Stephens  <nigel@mips.com>
 373             David Ung  <davidu@mips.com>
 374
 375         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 376         (print_mips16_insn_arg): Force mips16 to odd addresses.
 377
 378 2006-04-30  Thiemo Seufer  <ths@mips.com>
 379             David Ung  <davidu@mips.com>
 380
 381         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 382         "udi0" to "udi15".
 383         * mips-dis.c (print_insn_args): Adds udi argument handling.
 384
 385 2006-04-28  James E Wilson  <wilson@specifix.com>
 386
 387         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 388         error message.
 389
 390 2006-04-28  Thiemo Seufer  <ths@mips.com>
 391             David Ung  <davidu@mips.com>
 392             Nigel Stephens  <nigel@mips.com>
 393
 394         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 395         names.
 396
 397 2006-04-28  Thiemo Seufer  <ths@mips.com>
 398             Nigel Stephens  <nigel@mips.com>
 399             David Ung  <davidu@mips.com>
 400
 401         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 402         (print_insn_mips):  Adjust print_insn_args call.
 403
 404 2006-04-28  Thiemo Seufer  <ths@mips.com>
 405             Nigel Stephens  <nigel@mips.com>
 406
 407         * mips-dis.c (print_insn_args): Print $fcc only for FP
 408         instructions, use $cc elsewise.
 409
 410 2006-04-28  Thiemo Seufer  <ths@mips.com>
 411             Nigel Stephens  <nigel@mips.com>
 412
 413         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 414         Map MIPS16 registers to O32 names.
 415         (print_mips16_insn_arg): Use mips16_reg_names.
 416
 417 2006-04-26  Julian Brown  <julian@codesourcery.com>
 418
 419         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 420         VMOV.
 421
 422 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 423             Julian Brown  <julian@codesourcery.com>
 424
 425         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 426         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 427         Add unified load/store instruction names.
 428         (neon_opcode_table): New.
 429         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 430         (arm_decode_bitfield): New.
 431         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 432         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 433         (print_insn_neon): New.
 434         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 435         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 436         (print_insn_thumb32): Likewise.
 437
 438 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 439
 440         * Makefile.am: Run "make dep-am".
 441         * Makefile.in: Regenerate.
 442
 443 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 444
 445         * avr-dis.c (avr_operand): Warning fix.
 446
 447         * configure: Regenerate.
 448
 449 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 450
 451         * po/POTFILES.in: Regenerated.
 452
 453 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 454
 455         PR binutils/2454
 456         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 457         the symolic form of an address, so that the output of objdump -d
 458         can be reassembled.
 459
 460 2006-04-10  DJ Delorie  <dj@redhat.com>
 461
 462         * m32c-asm.c: Regenerate.
 463
 464 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 465
 466         * Makefile.am: Add install-html target.
 467         * Makefile.in: Regenerate.
 468
 469 2006-04-06  Nick Clifton  <nickc@redhat.com>
 470
 471         * po/vi/po: Updated Vietnamese translation.
 472
 473 2006-03-31  Paul Koning  <ni1d@arrl.net>
 474
 475         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 476
 477 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 478
 479         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 480         logic to identify halfword shifts.
 481
 482 2006-03-16  Paul Brook  <paul@codesourcery.com>
 483
 484         * arm-dis.c (arm_opcodes): Rename swi to svc.
 485         (thumb_opcodes): Ditto.
 486
 487 2006-03-13  DJ Delorie  <dj@redhat.com>
 488
 489         * m32c-asm.c: Regenerate.
 490         * m32c-desc.c: Likewise.
 491         * m32c-desc.h: Likewise.
 492         * m32c-dis.c: Likewise.
 493         * m32c-ibld.c: Likewise.
 494         * m32c-opc.c: Likewise.
 495         * m32c-opc.h: Likewise.
 496
 497 2006-03-10  DJ Delorie  <dj@redhat.com>
 498
 499         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 500         * m32c-opc.c: Likewise.
 501         * m32c-opc.h: Likewise.
 502
 503
 504 2006-03-09  Nick Clifton  <nickc@redhat.com>
 505
 506         * po/sv.po: Updated Swedish translation.
 507
 508 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 509
 510         PR binutils/2428
 511         * i386-dis.c (REP_Fixup): New function.
 512         (AL): Remove duplicate.
 513         (Xbr): New.
 514         (Xvr): Likewise.
 515         (Ybr): Likewise.
 516         (Yvr): Likewise.
 517         (indirDXr): Likewise.
 518         (ALr): Likewise.
 519         (eAXr): Likewise.
 520         (dis386): Updated entries of ins, outs, movs, lods and stos.
 521
 522 2006-03-05  Nick Clifton  <nickc@redhat.com>
 523
 524         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 525         signed 32-bit value into an unsigned 32-bit field when the host is
 526         a 64-bit machine.
 527         * fr30-ibld.c: Regenerate.
 528         * frv-ibld.c: Regenerate.
 529         * ip2k-ibld.c: Regenerate.
 530         * iq2000-asm.c: Regenerate.
 531         * iq2000-ibld.c: Regenerate.
 532         * m32c-ibld.c: Regenerate.
 533         * m32r-ibld.c: Regenerate.
 534         * openrisc-ibld.c: Regenerate.
 535         * xc16x-ibld.c: Regenerate.
 536         * xstormy16-ibld.c: Regenerate.
 537
 538 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 539
 540         * xc16x-asm.c: Regenerate.
 541         * xc16x-dis.c: Regenerate.
 542
 543 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 544
 545         * po/Make-in: Add html target.
 546
 547 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 548
 549         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 550         Intel Merom New Instructions.
 551         (THREE_BYTE_0): Likewise.
 552         (THREE_BYTE_1): Likewise.
 553         (three_byte_table): Likewise.
 554         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 555         THREE_BYTE_1 for entry 0x3a.
 556         (twobyte_has_modrm): Updated.
 557         (twobyte_uses_SSE_prefix): Likewise.
 558         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 559         Instructions.
 560
 561 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 562
 563         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 564         (v9_hpriv_reg_names): New table.
 565         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 566         New cases '$' and '%' for read/write hyperprivileged register.
 567         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 568         window handling and rdhpr/wrhpr instructions.
 569
 570 2006-02-24  DJ Delorie  <dj@redhat.com>
 571
 572         * m32c-desc.c: Regenerate with linker relaxation attributes.
 573         * m32c-desc.h: Likewise.
 574         * m32c-dis.c: Likewise.
 575         * m32c-opc.c: Likewise.
 576
 577 2006-02-24  Paul Brook  <paul@codesourcery.com>
 578
 579         * arm-dis.c (arm_opcodes): Add V7 instructions.
 580         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 581         (print_arm_address): New function.
 582         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 583         (psr_name): New function.
 584         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 585
 586 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 587
 588         * ia64-opc-i.c (bXc): New.
 589         (mXc): Likewise.
 590         (OpX2TaTbYaXcC): Likewise.
 591         (TF). Likewise.
 592         (TFCM). Likewise.
 593         (ia64_opcodes_i): Add instructions for tf.
 594
 595         * ia64-opc.h (IMMU5b): New.
 596
 597         * ia64-asmtab.c: Regenerated.
 598
 599 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 600
 601         * ia64-gen.c: Update copyright years.
 602         * ia64-opc-b.c: Likewise.
 603
 604 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 605
 606         * ia64-gen.c (lookup_regindex): Handle ".vm".
 607         (print_dependency_table): Handle '\"'.
 608
 609         * ia64-ic.tbl: Updated from SDM 2.2.
 610         * ia64-raw.tbl: Likewise.
 611         * ia64-waw.tbl: Likewise.
 612         * ia64-asmtab.c: Regenerated.
 613
 614         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 615
 616 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 617             Anil Paranjape   <anilp1@kpitcummins.com>
 618             Shilin Shakti    <shilins@kpitcummins.com>
 619
 620         * xc16x-desc.h: New file
 621         * xc16x-desc.c: New file
 622         * xc16x-opc.h: New file
 623         * xc16x-opc.c: New file
 624         * xc16x-ibld.c: New file
 625         * xc16x-asm.c: New file
 626         * xc16x-dis.c: New file
 627         * Makefile.am: Entries for xc16x
 628         * Makefile.in: Regenerate
 629         * cofigure.in: Add xc16x target information.
 630         * configure: Regenerate.
 631         * disassemble.c: Add xc16x target information.
 632
 633 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 634
 635         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 636         moves.
 637
 638 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 639
 640         * i386-dis.c ('Z'): Add a new macro.
 641         (dis386_twobyte): Use "movZ" for control register moves.
 642
 643 2006-02-10  Nick Clifton  <nickc@redhat.com>
 644
 645         * iq2000-asm.c: Regenerate.
 646
 647 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 648
 649         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 650
 651 2006-01-26  David Ung  <davidu@mips.com>
 652
 653         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 654         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 655         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 656         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 657         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 658
 659 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 660
 661         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 662         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 663         disassembled.
 664         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 665         buffer overflows when disassembling instructions like
 666         ld (ix+123),0x23
 667         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 668         operand, if the offset is negative.
 669
 670 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 671
 672         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 673         unsigned char to hold data to be disassembled.
 674
 675 2006-01-17  Andreas Schwab  <schwab@suse.de>
 676
 677         PR binutils/1486
 678         * disassemble.c (disassemble_init_for_target): Set
 679         disassembler_needs_relocs for bfd_arch_arm.
 680
 681 2006-01-16  Paul Brook  <paul@codesourcery.com>
 682
 683         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 684         f?add?, and f?sub? instructions.
 685
 686 2006-01-16  Nick Clifton  <nickc@redhat.com>
 687
 688         * po/zh_CN.po: New Chinese (simplified) translation.
 689         * configure.in (ALL_LINGUAS): Add "zh_CH".
 690         * configure: Regenerate.
 691
 692 2006-01-05  Paul Brook  <paul@codesourcery.com>
 693
 694         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 695
 696 2006-01-06  DJ Delorie  <dj@redhat.com>
 697
 698         * m32c-desc.c: Regenerate.
 699         * m32c-opc.c: Regenerate.
 700         * m32c-opc.h: Regenerate.
 701
 702 2006-01-03  DJ Delorie  <dj@redhat.com>
 703
 704         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 705         * m32c-ibld.c: Regenerated.
 706
 707 For older changes see ChangeLog-2005
 708 \f
 709 Local Variables:
 710 mode: change-log
 711 left-margin: 8
 712 fill-column: 74
 713 version-control: never
 714 End: