1 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
3 * arc-nps400-tbl.h: Fix some instruction masks.
5 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
7 * i386-dis.c (REG_82): Removed.
8 (X86_64_82_REG_0): Likewise.
9 (X86_64_82_REG_1): Likewise.
10 (X86_64_82_REG_2): Likewise.
11 (X86_64_82_REG_3): Likewise.
12 (X86_64_82_REG_4): Likewise.
13 (X86_64_82_REG_5): Likewise.
14 (X86_64_82_REG_6): Likewise.
15 (X86_64_82_REG_7): Likewise.
17 (dis386): Use X86_64_82 instead of REG_82.
18 (reg_table): Remove REG_82.
19 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
20 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
21 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
24 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
27 * i386-dis.c (REG_82): New.
28 (X86_64_82_REG_0): Likewise.
29 (X86_64_82_REG_1): Likewise.
30 (X86_64_82_REG_2): Likewise.
31 (X86_64_82_REG_3): Likewise.
32 (X86_64_82_REG_4): Likewise.
33 (X86_64_82_REG_5): Likewise.
34 (X86_64_82_REG_6): Likewise.
35 (X86_64_82_REG_7): Likewise.
37 (reg_table): Add REG_82.
38 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
39 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
40 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
42 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
44 * i386-dis.c (REG_82): Renamed to ...
47 (reg_table): Likewise.
49 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
51 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
52 * i386-dis-evex.h (evex_table): Updated.
53 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
54 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
55 (cpu_flags): Add CpuAVX512_4VNNIW.
56 * i386-opc.h (enum): (AVX512_4VNNIW): New.
57 (i386_cpu_flags): Add cpuavx512_4vnniw.
58 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
59 * i386-init.h: Regenerate.
62 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
64 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
65 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
66 * i386-dis-evex.h (evex_table): Updated.
67 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
68 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
69 (cpu_flags): Add CpuAVX512_4FMAPS.
70 (opcode_modifiers): Add ImplicitQuadGroup modifier.
71 * i386-opc.h (AVX512_4FMAP): New.
72 (i386_cpu_flags): Add cpuavx512_4fmaps.
73 (ImplicitQuadGroup): New.
74 (i386_opcode_modifier): Add implicitquadgroup.
75 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
76 * i386-init.h: Regenerate.
79 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
80 Andrew Waterman <andrew@sifive.com>
82 Add support for RISC-V architecture.
83 * configure.ac: Add entry for bfd_riscv_arch.
84 * configure: Regenerate.
85 * disassemble.c (disassembler): Add support for riscv.
86 (disassembler_usage): Likewise.
87 * riscv-dis.c: New file.
88 * riscv-opc.c: New file.
90 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
93 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
94 (rm_table): Update the RM_0FAE_REG_7 entry.
95 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
96 (cpu_flags): Remove CpuPCOMMIT.
97 * i386-opc.h (CpuPCOMMIT): Removed.
98 (i386_cpu_flags): Remove cpupcommit.
99 * i386-opc.tbl: Remove pcommit.
100 * i386-init.h: Regenerated.
101 * i386-tbl.h: Likewise.
103 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
106 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
107 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
108 32-bit mode. Don't check vex.register_specifier in 32-bit
110 (OP_VEX): Check for invalid mask registers.
112 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
115 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
118 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
121 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
123 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
125 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
126 local variable to `index_regno'.
128 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
130 * arc-tbl.h: Removed any "inv.+" instructions from the table.
132 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
134 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
137 2016-10-11 Jiong Wang <jiong.wang@arm.com>
140 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
142 2016-10-07 Jiong Wang <jiong.wang@arm.com>
145 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
148 2016-10-07 Alan Modra <amodra@gmail.com>
150 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
152 2016-10-06 Alan Modra <amodra@gmail.com>
154 * aarch64-opc.c: Spell fall through comments consistently.
155 * i386-dis.c: Likewise.
156 * aarch64-dis.c: Add missing fall through comments.
157 * aarch64-opc.c: Likewise.
158 * arc-dis.c: Likewise.
159 * arm-dis.c: Likewise.
160 * i386-dis.c: Likewise.
161 * m68k-dis.c: Likewise.
162 * mep-asm.c: Likewise.
163 * ns32k-dis.c: Likewise.
164 * sh-dis.c: Likewise.
165 * tic4x-dis.c: Likewise.
166 * tic6x-dis.c: Likewise.
167 * vax-dis.c: Likewise.
169 2016-10-06 Alan Modra <amodra@gmail.com>
171 * arc-ext.c (create_map): Add missing break.
172 * msp430-decode.opc (encode_as): Likewise.
173 * msp430-decode.c: Regenerate.
175 2016-10-06 Alan Modra <amodra@gmail.com>
177 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
178 * crx-dis.c (print_insn_crx): Likewise.
180 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
183 * i386-dis.c (putop): Don't assign alt twice.
185 2016-09-29 Jiong Wang <jiong.wang@arm.com>
188 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
190 2016-09-29 Alan Modra <amodra@gmail.com>
192 * ppc-opc.c (L): Make compulsory.
193 (LOPT): New, optional form of L.
194 (HTM_R): Define as LOPT.
196 (L32OPT): New, optional for 32-bit L.
197 (L2OPT): New, 2-bit L for dcbf.
200 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
201 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
203 <tlbiel, tlbie>: Use LOPT.
204 <wclr, wclrall>: Use L2.
206 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
208 * Makefile.in: Regenerate.
209 * configure: Likewise.
211 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
213 * arc-ext-tbl.h (EXTINSN2OPF): Define.
214 (EXTINSN2OP): Use EXTINSN2OPF.
215 (bspeekm, bspop, modapp): New extension instructions.
216 * arc-opc.c (F_DNZ_ND): Define.
221 * arc-tbl.h (dbnz): New instruction.
222 (prealloc): Allow it for ARC EM.
225 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
227 * aarch64-opc.c (print_immediate_offset_address): Print spaces
228 after commas in addresses.
229 (aarch64_print_operand): Likewise.
231 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
233 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
234 rather than "should be" or "expected to be" in error messages.
236 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
238 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
239 (print_mnemonic_name): ...here.
240 (print_comment): New function.
241 (print_aarch64_insn): Call it.
242 * aarch64-opc.c (aarch64_conds): Add SVE names.
243 (aarch64_print_operand): Print alternative condition names in
246 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
248 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
249 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
250 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
251 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
252 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
253 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
254 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
255 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
256 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
257 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
258 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
259 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
260 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
261 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
262 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
263 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
264 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
265 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
266 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
267 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
268 (OP_SVE_XWU, OP_SVE_XXU): New macros.
269 (aarch64_feature_sve): New variable.
271 (_SVE_INSN): Likewise.
272 (aarch64_opcode_table): Add SVE instructions.
273 * aarch64-opc.h (extract_fields): Declare.
274 * aarch64-opc-2.c: Regenerate.
275 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
276 * aarch64-asm-2.c: Regenerate.
277 * aarch64-dis.c (extract_fields): Make global.
278 (do_misc_decoding): Handle the new SVE aarch64_ops.
279 * aarch64-dis-2.c: Regenerate.
281 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
283 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
284 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
286 * aarch64-opc.c (fields): Add corresponding entries.
287 * aarch64-asm.c (aarch64_get_variant): New function.
288 (aarch64_encode_variant_using_iclass): Likewise.
289 (aarch64_opcode_encode): Call it.
290 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
291 (aarch64_opcode_decode): Call it.
293 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
295 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
296 and FP register operands.
297 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
298 (FLD_SVE_Vn): New aarch64_field_kinds.
299 * aarch64-opc.c (fields): Add corresponding entries.
300 (aarch64_print_operand): Handle the new SVE core and FP register
302 * aarch64-opc-2.c: Regenerate.
303 * aarch64-asm-2.c: Likewise.
304 * aarch64-dis-2.c: Likewise.
306 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
308 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
310 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
311 * aarch64-opc.c (fields): Add corresponding entry.
312 (operand_general_constraint_met_p): Handle the new SVE FP immediate
314 (aarch64_print_operand): Likewise.
315 * aarch64-opc-2.c: Regenerate.
316 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
317 (ins_sve_float_zero_one): New inserters.
318 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
319 (aarch64_ins_sve_float_half_two): Likewise.
320 (aarch64_ins_sve_float_zero_one): Likewise.
321 * aarch64-asm-2.c: Regenerate.
322 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
323 (ext_sve_float_zero_one): New extractors.
324 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
325 (aarch64_ext_sve_float_half_two): Likewise.
326 (aarch64_ext_sve_float_zero_one): Likewise.
327 * aarch64-dis-2.c: Regenerate.
329 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
331 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
332 integer immediate operands.
333 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
334 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
335 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
336 * aarch64-opc.c (fields): Add corresponding entries.
337 (operand_general_constraint_met_p): Handle the new SVE integer
339 (aarch64_print_operand): Likewise.
340 (aarch64_sve_dupm_mov_immediate_p): New function.
341 * aarch64-opc-2.c: Regenerate.
342 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
343 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
344 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
345 (aarch64_ins_limm): ...here.
346 (aarch64_ins_inv_limm): New function.
347 (aarch64_ins_sve_aimm): Likewise.
348 (aarch64_ins_sve_asimm): Likewise.
349 (aarch64_ins_sve_limm_mov): Likewise.
350 (aarch64_ins_sve_shlimm): Likewise.
351 (aarch64_ins_sve_shrimm): Likewise.
352 * aarch64-asm-2.c: Regenerate.
353 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
354 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
355 * aarch64-dis.c (decode_limm): New function, split out from...
356 (aarch64_ext_limm): ...here.
357 (aarch64_ext_inv_limm): New function.
358 (decode_sve_aimm): Likewise.
359 (aarch64_ext_sve_aimm): Likewise.
360 (aarch64_ext_sve_asimm): Likewise.
361 (aarch64_ext_sve_limm_mov): Likewise.
362 (aarch64_top_bit): Likewise.
363 (aarch64_ext_sve_shlimm): Likewise.
364 (aarch64_ext_sve_shrimm): Likewise.
365 * aarch64-dis-2.c: Regenerate.
367 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
369 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
371 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
372 the AARCH64_MOD_MUL_VL entry.
373 (value_aligned_p): Cope with non-power-of-two alignments.
374 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
375 (print_immediate_offset_address): Likewise.
376 (aarch64_print_operand): Likewise.
377 * aarch64-opc-2.c: Regenerate.
378 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
379 (ins_sve_addr_ri_s9xvl): New inserters.
380 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
381 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
382 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
383 * aarch64-asm-2.c: Regenerate.
384 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
385 (ext_sve_addr_ri_s9xvl): New extractors.
386 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
387 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
388 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
389 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
390 * aarch64-dis-2.c: Regenerate.
392 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
394 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
396 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
397 (FLD_SVE_xs_22): New aarch64_field_kinds.
398 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
399 (get_operand_specific_data): New function.
400 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
401 FLD_SVE_xs_14 and FLD_SVE_xs_22.
402 (operand_general_constraint_met_p): Handle the new SVE address
404 (sve_reg): New array.
405 (get_addr_sve_reg_name): New function.
406 (aarch64_print_operand): Handle the new SVE address operands.
407 * aarch64-opc-2.c: Regenerate.
408 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
409 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
410 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
411 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
412 (aarch64_ins_sve_addr_rr_lsl): Likewise.
413 (aarch64_ins_sve_addr_rz_xtw): Likewise.
414 (aarch64_ins_sve_addr_zi_u5): Likewise.
415 (aarch64_ins_sve_addr_zz): Likewise.
416 (aarch64_ins_sve_addr_zz_lsl): Likewise.
417 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
418 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
419 * aarch64-asm-2.c: Regenerate.
420 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
421 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
422 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
423 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
424 (aarch64_ext_sve_addr_ri_u6): Likewise.
425 (aarch64_ext_sve_addr_rr_lsl): Likewise.
426 (aarch64_ext_sve_addr_rz_xtw): Likewise.
427 (aarch64_ext_sve_addr_zi_u5): Likewise.
428 (aarch64_ext_sve_addr_zz): Likewise.
429 (aarch64_ext_sve_addr_zz_lsl): Likewise.
430 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
431 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
432 * aarch64-dis-2.c: Regenerate.
434 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
436 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
437 AARCH64_OPND_SVE_PATTERN_SCALED.
438 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
439 * aarch64-opc.c (fields): Add a corresponding entry.
440 (set_multiplier_out_of_range_error): New function.
441 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
442 (operand_general_constraint_met_p): Handle
443 AARCH64_OPND_SVE_PATTERN_SCALED.
444 (print_register_offset_address): Use PRIi64 to print the
446 (aarch64_print_operand): Likewise. Handle
447 AARCH64_OPND_SVE_PATTERN_SCALED.
448 * aarch64-opc-2.c: Regenerate.
449 * aarch64-asm.h (ins_sve_scale): New inserter.
450 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
451 * aarch64-asm-2.c: Regenerate.
452 * aarch64-dis.h (ext_sve_scale): New inserter.
453 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
454 * aarch64-dis-2.c: Regenerate.
456 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
458 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
459 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
460 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
461 (FLD_SVE_prfop): Likewise.
462 * aarch64-opc.c: Include libiberty.h.
463 (aarch64_sve_pattern_array): New variable.
464 (aarch64_sve_prfop_array): Likewise.
465 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
466 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
467 AARCH64_OPND_SVE_PRFOP.
468 * aarch64-asm-2.c: Regenerate.
469 * aarch64-dis-2.c: Likewise.
470 * aarch64-opc-2.c: Likewise.
472 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
474 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
475 AARCH64_OPND_QLF_P_[ZM].
476 (aarch64_print_operand): Print /z and /m where appropriate.
478 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
480 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
481 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
482 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
483 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
484 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
485 * aarch64-opc.c (fields): Add corresponding entries here.
486 (operand_general_constraint_met_p): Check that SVE register lists
487 have the correct length. Check the ranges of SVE index registers.
488 Check for cases where p8-p15 are used in 3-bit predicate fields.
489 (aarch64_print_operand): Handle the new SVE operands.
490 * aarch64-opc-2.c: Regenerate.
491 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
492 * aarch64-asm.c (aarch64_ins_sve_index): New function.
493 (aarch64_ins_sve_reglist): Likewise.
494 * aarch64-asm-2.c: Regenerate.
495 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
496 * aarch64-dis.c (aarch64_ext_sve_index): New function.
497 (aarch64_ext_sve_reglist): Likewise.
498 * aarch64-dis-2.c: Regenerate.
500 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
502 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
503 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
504 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
505 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
508 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
510 * aarch64-opc.c (get_offset_int_reg_name): New function.
511 (print_immediate_offset_address): Likewise.
512 (print_register_offset_address): Take the base and offset
513 registers as parameters.
514 (aarch64_print_operand): Update caller accordingly. Use
515 print_immediate_offset_address.
517 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
519 * aarch64-opc.c (BANK): New macro.
520 (R32, R64): Take a register number as argument
523 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
525 * aarch64-opc.c (print_register_list): Add a prefix parameter.
526 (aarch64_print_operand): Update accordingly.
528 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
530 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
532 * aarch64-asm.h (ins_fpimm): New inserter.
533 * aarch64-asm.c (aarch64_ins_fpimm): New function.
534 * aarch64-asm-2.c: Regenerate.
535 * aarch64-dis.h (ext_fpimm): New extractor.
536 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
537 (aarch64_ext_fpimm): New function.
538 * aarch64-dis-2.c: Regenerate.
540 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
542 * aarch64-asm.c: Include libiberty.h.
543 (insert_fields): New function.
544 (aarch64_ins_imm): Use it.
545 * aarch64-dis.c (extract_fields): New function.
546 (aarch64_ext_imm): Use it.
548 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
550 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
551 with an esize parameter.
552 (operand_general_constraint_met_p): Update accordingly.
553 Fix misindented code.
554 * aarch64-asm.c (aarch64_ins_limm): Update call to
555 aarch64_logical_immediate_p.
557 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
559 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
561 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
563 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
565 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
567 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
569 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
571 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
572 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
573 xor3>: Delete mnemonics.
574 <cp_abort>: Rename mnemonic from ...
575 <cpabort>: ...to this.
576 <setb>: Change to a X form instruction.
577 <sync>: Change to 1 operand form.
578 <copy>: Delete mnemonic.
579 <copy_first>: Rename mnemonic from ...
581 <paste, paste.>: Delete mnemonics.
582 <paste_last>: Rename mnemonic from ...
583 <paste.>: ...to this.
585 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
587 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
589 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
591 * s390-mkopc.c (main): Support alternate arch strings.
593 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
595 * s390-opc.txt: Fix kmctr instruction type.
597 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
599 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
600 * i386-init.h: Regenerated.
602 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
604 * opcodes/arc-dis.c (print_insn_arc): Changed.
606 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
608 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
611 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
613 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
614 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
615 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
617 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
619 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
620 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
621 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
622 PREFIX_MOD_3_0FAE_REG_4.
623 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
624 PREFIX_MOD_3_0FAE_REG_4.
625 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
626 (cpu_flags): Add CpuPTWRITE.
627 * i386-opc.h (CpuPTWRITE): New.
628 (i386_cpu_flags): Add cpuptwrite.
629 * i386-opc.tbl: Add ptwrite instruction.
630 * i386-init.h: Regenerated.
631 * i386-tbl.h: Likewise.
633 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
635 * arc-dis.h: Wrap around in extern "C".
637 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
639 * aarch64-tbl.h (V8_2_INSN): New macro.
640 (aarch64_opcode_table): Use it.
642 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
644 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
645 CORE_INSN, __FP_INSN and SIMD_INSN.
647 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
649 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
650 (aarch64_opcode_table): Update uses accordingly.
652 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
653 Kwok Cheung Yeung <kcy@codesourcery.com>
656 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
657 'e_cmplwi' to 'e_cmpli' instead.
658 (OPVUPRT, OPVUPRT_MASK): Define.
659 (powerpc_opcodes): Add E200Z4 insns.
660 (vle_opcodes): Add context save/restore insns.
662 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
664 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
665 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
668 2016-07-27 Graham Markall <graham.markall@embecosm.com>
670 * arc-nps400-tbl.h: Change block comments to GNU format.
671 * arc-dis.c: Add new globals addrtypenames,
672 addrtypenames_max, and addtypeunknown.
673 (get_addrtype): New function.
674 (print_insn_arc): Print colons and address types when
676 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
677 define insert and extract functions for all address types.
678 (arc_operands): Add operands for colon and all address
680 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
681 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
682 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
683 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
684 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
685 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
687 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
689 * configure: Regenerated.
691 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
693 * arc-dis.c (skipclass): New structure.
694 (decodelist): New variable.
695 (is_compatible_p): New function.
696 (new_element): Likewise.
697 (skip_class_p): Likewise.
698 (find_format_from_table): Use skip_class_p function.
699 (find_format): Decode first the extension instructions.
700 (print_insn_arc): Select either ARCEM or ARCHS based on elf
702 (parse_option): New function.
703 (parse_disassembler_options): Likewise.
704 (print_arc_disassembler_options): Likewise.
705 (print_insn_arc): Use parse_disassembler_options function. Proper
706 select ARCv2 cpu variant.
707 * disassemble.c (disassembler_usage): Add ARC disassembler
710 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
712 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
713 annotation from the "nal" entry and reorder it beyond "bltzal".
715 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
717 * sparc-opc.c (ldtxa): New macro.
718 (sparc_opcodes): Use the macro defined above to add entries for
719 the LDTXA instructions.
720 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
723 2016-07-07 James Bowman <james.bowman@ftdichip.com>
725 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
728 2016-07-01 Jan Beulich <jbeulich@suse.com>
730 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
731 (movzb): Adjust to cover all permitted suffixes.
733 * i386-tbl.h: Re-generate.
735 2016-07-01 Jan Beulich <jbeulich@suse.com>
737 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
738 (lgdt): Remove Tbyte from non-64-bit variant.
739 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
740 xsaves64, xsavec64): Remove Disp16.
741 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
742 Remove Disp32S from non-64-bit variants. Remove Disp16 from
744 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
745 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
746 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
748 * i386-tbl.h: Re-generate.
750 2016-07-01 Jan Beulich <jbeulich@suse.com>
752 * i386-opc.tbl (xlat): Remove RepPrefixOk.
753 * i386-tbl.h: Re-generate.
755 2016-06-30 Yao Qi <yao.qi@linaro.org>
757 * arm-dis.c (print_insn): Fix typo in comment.
759 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
761 * aarch64-opc.c (operand_general_constraint_met_p): Check the
762 range of ldst_elemlist operands.
763 (print_register_list): Use PRIi64 to print the index.
764 (aarch64_print_operand): Likewise.
766 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
768 * mcore-opc.h: Remove sentinal.
769 * mcore-dis.c (print_insn_mcore): Adjust.
771 2016-06-23 Graham Markall <graham.markall@embecosm.com>
773 * arc-opc.c: Correct description of availability of NPS400
776 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
778 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
779 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
780 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
781 xor3>: New mnemonics.
782 <setb>: Change to a VX form instruction.
783 (insert_sh6): Add support for rldixor.
784 (extract_sh6): Likewise.
786 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
788 * arc-ext.h: Wrap in extern C.
790 2016-06-21 Graham Markall <graham.markall@embecosm.com>
792 * arc-dis.c (arc_insn_length): Add comment on instruction length.
793 Use same method for determining instruction length on ARC700 and
795 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
796 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
797 with the NPS400 subclass.
798 * arc-opc.c: Likewise.
800 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
802 * sparc-opc.c (rdasr): New macro.
808 (sparc_opcodes): Use the macros above to fix and expand the
809 definition of read/write instructions from/to
810 asr/privileged/hyperprivileged instructions.
811 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
812 %hva_mask_nz. Prefer softint_set and softint_clear over
813 set_softint and clear_softint.
814 (print_insn_sparc): Support %ver in Rd.
816 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
818 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
819 architecture according to the hardware capabilities they require.
821 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
823 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
824 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
825 bfd_mach_sparc_v9{c,d,e,v,m}.
826 * sparc-opc.c (MASK_V9C): Define.
827 (MASK_V9D): Likewise.
828 (MASK_V9E): Likewise.
829 (MASK_V9V): Likewise.
830 (MASK_V9M): Likewise.
831 (v6): Add MASK_V9{C,D,E,V,M}.
832 (v6notlet): Likewise.
836 (v9andleon): Likewise.
844 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
846 2016-06-15 Nick Clifton <nickc@redhat.com>
848 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
849 constants to match expected behaviour.
850 (nds32_parse_opcode): Likewise. Also for whitespace.
852 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
854 * arc-opc.c (extract_rhv1): Extract value from insn.
856 2016-06-14 Graham Markall <graham.markall@embecosm.com>
858 * arc-nps400-tbl.h: Add ldbit instruction.
859 * arc-opc.c: Add flag classes required for ldbit.
861 2016-06-14 Graham Markall <graham.markall@embecosm.com>
863 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
864 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
865 support the above instructions.
867 2016-06-14 Graham Markall <graham.markall@embecosm.com>
869 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
870 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
871 csma, cbba, zncv, and hofs.
872 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
873 support the above instructions.
875 2016-06-06 Graham Markall <graham.markall@embecosm.com>
877 * arc-nps400-tbl.h: Add andab and orab instructions.
879 2016-06-06 Graham Markall <graham.markall@embecosm.com>
881 * arc-nps400-tbl.h: Add addl-like instructions.
883 2016-06-06 Graham Markall <graham.markall@embecosm.com>
885 * arc-nps400-tbl.h: Add mxb and imxb instructions.
887 2016-06-06 Graham Markall <graham.markall@embecosm.com>
889 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
892 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
894 * s390-dis.c (option_use_insn_len_bits_p): New file scope
896 (init_disasm): Handle new command line option "insnlength".
897 (print_s390_disassembler_options): Mention new option in help
899 (print_insn_s390): Use the encoded insn length when dumping
900 unknown instructions.
902 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
904 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
905 to the address and set as symbol address for LDS/ STS immediate operands.
907 2016-06-07 Alan Modra <amodra@gmail.com>
909 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
910 cpu for "vle" to e500.
911 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
912 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
913 (PPCNONE): Delete, substitute throughout.
914 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
915 except for major opcode 4 and 31.
916 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
918 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
920 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
921 ARM_EXT_RAS in relevant entries.
923 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
926 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
929 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
932 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
934 Add comments for '&'.
935 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
937 (intel_operand_size): Handle indir_v_mode.
938 (OP_E_register): Likewise.
939 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
940 64-bit indirect call/jmp for AMD64.
941 * i386-tbl.h: Regenerated
943 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
945 * arc-dis.c (struct arc_operand_iterator): New structure.
946 (find_format_from_table): All the old content from find_format,
947 with some minor adjustments, and parameter renaming.
948 (find_format_long_instructions): New function.
949 (find_format): Rewritten.
950 (arc_insn_length): Add LSB parameter.
951 (extract_operand_value): New function.
952 (operand_iterator_next): New function.
953 (print_insn_arc): Use new functions to find opcode, and iterator
955 * arc-opc.c (insert_nps_3bit_dst_short): New function.
956 (extract_nps_3bit_dst_short): New function.
957 (insert_nps_3bit_src2_short): New function.
958 (extract_nps_3bit_src2_short): New function.
959 (insert_nps_bitop1_size): New function.
960 (extract_nps_bitop1_size): New function.
961 (insert_nps_bitop2_size): New function.
962 (extract_nps_bitop2_size): New function.
963 (insert_nps_bitop_mod4_msb): New function.
964 (extract_nps_bitop_mod4_msb): New function.
965 (insert_nps_bitop_mod4_lsb): New function.
966 (extract_nps_bitop_mod4_lsb): New function.
967 (insert_nps_bitop_dst_pos3_pos4): New function.
968 (extract_nps_bitop_dst_pos3_pos4): New function.
969 (insert_nps_bitop_ins_ext): New function.
970 (extract_nps_bitop_ins_ext): New function.
971 (arc_operands): Add new operands.
972 (arc_long_opcodes): New global array.
973 (arc_num_long_opcodes): New global.
974 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
976 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
978 * nds32-asm.h: Add extern "C".
979 * sh-opc.h: Likewise.
981 2016-06-01 Graham Markall <graham.markall@embecosm.com>
983 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
984 0,b,limm to the rflt instruction.
986 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
988 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
991 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
994 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
995 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
996 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
997 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
998 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
999 * i386-init.h: Regenerated.
1001 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1004 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1005 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1006 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1007 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1008 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1009 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1010 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1011 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1012 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1013 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1014 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1015 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1016 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1017 CpuRegMask for AVX512.
1018 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1020 (set_bitfield_from_cpu_flag_init): New function.
1021 (set_bitfield): Remove const on f. Call
1022 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1023 * i386-opc.h (CpuRegMMX): New.
1024 (CpuRegXMM): Likewise.
1025 (CpuRegYMM): Likewise.
1026 (CpuRegZMM): Likewise.
1027 (CpuRegMask): Likewise.
1028 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1030 * i386-init.h: Regenerated.
1031 * i386-tbl.h: Likewise.
1033 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1036 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1037 (opcode_modifiers): Add AMD64 and Intel64.
1038 (main): Properly verify CpuMax.
1039 * i386-opc.h (CpuAMD64): Removed.
1040 (CpuIntel64): Likewise.
1041 (CpuMax): Set to CpuNo64.
1042 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1044 (Intel64): Likewise.
1045 (i386_opcode_modifier): Add amd64 and intel64.
1046 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1048 * i386-init.h: Regenerated.
1049 * i386-tbl.h: Likewise.
1051 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1054 * i386-gen.c (main): Fail if CpuMax is incorrect.
1055 * i386-opc.h (CpuMax): Set to CpuIntel64.
1056 * i386-tbl.h: Regenerated.
1058 2016-05-27 Nick Clifton <nickc@redhat.com>
1061 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1062 (msp430dis_opcode_unsigned): New function.
1063 (msp430dis_opcode_signed): New function.
1064 (msp430_singleoperand): Use the new opcode reading functions.
1065 Only disassenmble bytes if they were successfully read.
1066 (msp430_doubleoperand): Likewise.
1067 (msp430_branchinstr): Likewise.
1068 (msp430x_callx_instr): Likewise.
1069 (print_insn_msp430): Check that it is safe to read bytes before
1070 attempting disassembly. Use the new opcode reading functions.
1072 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1074 * ppc-opc.c (CY): New define. Document it.
1075 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1077 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1079 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1080 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1081 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1082 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1084 * i386-init.h: Regenerated.
1086 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1089 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1090 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1091 * i386-init.h: Regenerated.
1093 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1095 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1096 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1097 * i386-init.h: Regenerated.
1099 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1101 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1103 (print_insn_arc): Set insn_type information.
1104 * arc-opc.c (C_CC): Add F_CLASS_COND.
1105 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1106 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1107 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1108 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1109 (brne, brne_s, jeq_s, jne_s): Likewise.
1111 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1113 * arc-tbl.h (neg): New instruction variant.
1115 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1117 * arc-dis.c (find_format, find_format, get_auxreg)
1118 (print_insn_arc): Changed.
1119 * arc-ext.h (INSERT_XOP): Likewise.
1121 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1123 * tic54x-dis.c (sprint_mmr): Adjust.
1124 * tic54x-opc.c: Likewise.
1126 2016-05-19 Alan Modra <amodra@gmail.com>
1128 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1130 2016-05-19 Alan Modra <amodra@gmail.com>
1132 * ppc-opc.c: Formatting.
1133 (NSISIGNOPT): Define.
1134 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1136 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1138 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1139 replacing references to `micromips_ase' throughout.
1140 (_print_insn_mips): Don't use file-level microMIPS annotation to
1141 determine the disassembly mode with the symbol table.
1143 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1145 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1147 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1149 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1151 * mips-opc.c (D34): New macro.
1152 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1154 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1156 * i386-dis.c (prefix_table): Add RDPID instruction.
1157 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1158 (cpu_flags): Add RDPID bitfield.
1159 * i386-opc.h (enum): Add RDPID element.
1160 (i386_cpu_flags): Add RDPID field.
1161 * i386-opc.tbl: Add RDPID instruction.
1162 * i386-init.h: Regenerate.
1163 * i386-tbl.h: Regenerate.
1165 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1167 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1168 branch type of a symbol.
1169 (print_insn): Likewise.
1171 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1173 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1174 Mainline Security Extensions instructions.
1175 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1176 Extensions instructions.
1177 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1179 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1182 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1184 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1186 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1188 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1189 (arcExtMap_genOpcode): Likewise.
1190 * arc-opc.c (arg_32bit_rc): Define new variable.
1191 (arg_32bit_u6): Likewise.
1192 (arg_32bit_limm): Likewise.
1194 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1196 * aarch64-gen.c (VERIFIER): Define.
1197 * aarch64-opc.c (VERIFIER): Define.
1198 (verify_ldpsw): Use static linkage.
1199 * aarch64-opc.h (verify_ldpsw): Remove.
1200 * aarch64-tbl.h: Use VERIFIER for verifiers.
1202 2016-04-28 Nick Clifton <nickc@redhat.com>
1205 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1206 * aarch64-opc.c (verify_ldpsw): New function.
1207 * aarch64-opc.h (verify_ldpsw): New prototype.
1208 * aarch64-tbl.h: Add initialiser for verifier field.
1209 (LDPSW): Set verifier to verify_ldpsw.
1211 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1215 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1216 smaller than address size.
1218 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1220 * alpha-dis.c: Regenerate.
1221 * crx-dis.c: Likewise.
1222 * disassemble.c: Likewise.
1223 * epiphany-opc.c: Likewise.
1224 * fr30-opc.c: Likewise.
1225 * frv-opc.c: Likewise.
1226 * ip2k-opc.c: Likewise.
1227 * iq2000-opc.c: Likewise.
1228 * lm32-opc.c: Likewise.
1229 * lm32-opinst.c: Likewise.
1230 * m32c-opc.c: Likewise.
1231 * m32r-opc.c: Likewise.
1232 * m32r-opinst.c: Likewise.
1233 * mep-opc.c: Likewise.
1234 * mt-opc.c: Likewise.
1235 * or1k-opc.c: Likewise.
1236 * or1k-opinst.c: Likewise.
1237 * tic80-opc.c: Likewise.
1238 * xc16x-opc.c: Likewise.
1239 * xstormy16-opc.c: Likewise.
1241 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1243 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1244 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1245 calcsd, and calcxd instructions.
1246 * arc-opc.c (insert_nps_bitop_size): Delete.
1247 (extract_nps_bitop_size): Delete.
1248 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1249 (extract_nps_qcmp_m3): Define.
1250 (extract_nps_qcmp_m2): Define.
1251 (extract_nps_qcmp_m1): Define.
1252 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1253 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1254 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1255 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1256 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1259 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1261 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1263 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1265 * Makefile.in: Regenerated with automake 1.11.6.
1266 * aclocal.m4: Likewise.
1268 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1270 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1272 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1273 (extract_nps_cmem_uimm16): New function.
1274 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1276 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1278 * arc-dis.c (arc_insn_length): New function.
1279 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1280 (find_format): Change insnLen parameter to unsigned.
1282 2016-04-13 Nick Clifton <nickc@redhat.com>
1285 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1286 the LD.B and LD.BU instructions.
1288 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1290 * arc-dis.c (find_format): Check for extension flags.
1291 (print_flags): New function.
1292 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1294 * arc-ext.c (arcExtMap_coreRegName): Use
1295 LAST_EXTENSION_CORE_REGISTER.
1296 (arcExtMap_coreReadWrite): Likewise.
1297 (dump_ARC_extmap): Update printing.
1298 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1299 (arc_aux_regs): Add cpu field.
1300 * arc-regs.h: Add cpu field, lower case name aux registers.
1302 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1304 * arc-tbl.h: Add rtsc, sleep with no arguments.
1306 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1308 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1310 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1311 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1312 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1313 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1314 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1315 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1316 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1317 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1318 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1319 (arc_opcode arc_opcodes): Null terminate the array.
1320 (arc_num_opcodes): Remove.
1321 * arc-ext.h (INSERT_XOP): Define.
1322 (extInstruction_t): Likewise.
1323 (arcExtMap_instName): Delete.
1324 (arcExtMap_insn): New function.
1325 (arcExtMap_genOpcode): Likewise.
1326 * arc-ext.c (ExtInstruction): Remove.
1327 (create_map): Zero initialize instruction fields.
1328 (arcExtMap_instName): Remove.
1329 (arcExtMap_insn): New function.
1330 (dump_ARC_extmap): More info while debuging.
1331 (arcExtMap_genOpcode): New function.
1332 * arc-dis.c (find_format): New function.
1333 (print_insn_arc): Use find_format.
1334 (arc_get_disassembler): Enable dump_ARC_extmap only when
1337 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1339 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1340 instruction bits out.
1342 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1344 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1345 * arc-opc.c (arc_flag_operands): Add new flags.
1346 (arc_flag_classes): Add new classes.
1348 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1350 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1352 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1354 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1355 encode1, rflt, crc16, and crc32 instructions.
1356 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1357 (arc_flag_classes): Add C_NPS_R.
1358 (insert_nps_bitop_size_2b): New function.
1359 (extract_nps_bitop_size_2b): Likewise.
1360 (insert_nps_bitop_uimm8): Likewise.
1361 (extract_nps_bitop_uimm8): Likewise.
1362 (arc_operands): Add new operand entries.
1364 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1366 * arc-regs.h: Add a new subclass field. Add double assist
1367 accumulator register values.
1368 * arc-tbl.h: Use DPA subclass to mark the double assist
1369 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1370 * arc-opc.c (RSP): Define instead of SP.
1371 (arc_aux_regs): Add the subclass field.
1373 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1375 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1377 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1379 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1382 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1384 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1385 issues. No functional changes.
1387 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1389 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1390 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1391 (RTT): Remove duplicate.
1392 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1393 (PCT_CONFIG*): Remove.
1394 (D1L, D1H, D2H, D2L): Define.
1396 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1398 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1400 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1402 * arc-tbl.h (invld07): Remove.
1403 * arc-ext-tbl.h: New file.
1404 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1405 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1407 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1409 Fix -Wstack-usage warnings.
1410 * aarch64-dis.c (print_operands): Substitute size.
1411 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1413 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1415 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1416 to get a proper diagnostic when an invalid ASR register is used.
1418 2016-03-22 Nick Clifton <nickc@redhat.com>
1420 * configure: Regenerate.
1422 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1424 * arc-nps400-tbl.h: New file.
1425 * arc-opc.c: Add top level comment.
1426 (insert_nps_3bit_dst): New function.
1427 (extract_nps_3bit_dst): New function.
1428 (insert_nps_3bit_src2): New function.
1429 (extract_nps_3bit_src2): New function.
1430 (insert_nps_bitop_size): New function.
1431 (extract_nps_bitop_size): New function.
1432 (arc_flag_operands): Add nps400 entries.
1433 (arc_flag_classes): Add nps400 entries.
1434 (arc_operands): Add nps400 entries.
1435 (arc_opcodes): Add nps400 include.
1437 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1439 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1440 the new class enum values.
1442 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1444 * arc-dis.c (print_insn_arc): Handle nps400.
1446 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1448 * arc-opc.c (BASE): Delete.
1450 2016-03-18 Nick Clifton <nickc@redhat.com>
1453 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1454 of MOV insn that aliases an ORR insn.
1456 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1458 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1460 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1462 * mcore-opc.h: Add const qualifiers.
1463 * microblaze-opc.h (struct op_code_struct): Likewise.
1464 * sh-opc.h: Likewise.
1465 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1466 (tic4x_print_op): Likewise.
1468 2016-03-02 Alan Modra <amodra@gmail.com>
1470 * or1k-desc.h: Regenerate.
1471 * fr30-ibld.c: Regenerate.
1472 * rl78-decode.c: Regenerate.
1474 2016-03-01 Nick Clifton <nickc@redhat.com>
1477 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1479 2016-02-24 Renlin Li <renlin.li@arm.com>
1481 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1482 (print_insn_coprocessor): Support fp16 instructions.
1484 2016-02-24 Renlin Li <renlin.li@arm.com>
1486 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1487 vminnm, vrint(mpna).
1489 2016-02-24 Renlin Li <renlin.li@arm.com>
1491 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1492 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1494 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1496 * i386-dis.c (print_insn): Parenthesize expression to prevent
1497 truncated addresses.
1500 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1501 Janek van Oirschot <jvanoirs@synopsys.com>
1503 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1506 2016-02-04 Nick Clifton <nickc@redhat.com>
1509 * msp430-dis.c (print_insn_msp430): Add a special case for
1510 decoding an RRC instruction with the ZC bit set in the extension
1513 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1515 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1516 * epiphany-ibld.c: Regenerate.
1517 * fr30-ibld.c: Regenerate.
1518 * frv-ibld.c: Regenerate.
1519 * ip2k-ibld.c: Regenerate.
1520 * iq2000-ibld.c: Regenerate.
1521 * lm32-ibld.c: Regenerate.
1522 * m32c-ibld.c: Regenerate.
1523 * m32r-ibld.c: Regenerate.
1524 * mep-ibld.c: Regenerate.
1525 * mt-ibld.c: Regenerate.
1526 * or1k-ibld.c: Regenerate.
1527 * xc16x-ibld.c: Regenerate.
1528 * xstormy16-ibld.c: Regenerate.
1530 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1532 * epiphany-dis.c: Regenerated from latest cpu files.
1534 2016-02-01 Michael McConville <mmcco@mykolab.com>
1536 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1539 2016-01-25 Renlin Li <renlin.li@arm.com>
1541 * arm-dis.c (mapping_symbol_for_insn): New function.
1542 (find_ifthen_state): Call mapping_symbol_for_insn().
1544 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1546 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1547 of MSR UAO immediate operand.
1549 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1551 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1552 instruction support.
1554 2016-01-17 Alan Modra <amodra@gmail.com>
1556 * configure: Regenerate.
1558 2016-01-14 Nick Clifton <nickc@redhat.com>
1560 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1561 instructions that can support stack pointer operations.
1562 * rl78-decode.c: Regenerate.
1563 * rl78-dis.c: Fix display of stack pointer in MOVW based
1566 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1568 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1569 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1570 erxtatus_el1 and erxaddr_el1.
1572 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1574 * arm-dis.c (arm_opcodes): Add "esb".
1575 (thumb_opcodes): Likewise.
1577 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1579 * ppc-opc.c <xscmpnedp>: Delete.
1580 <xvcmpnedp>: Likewise.
1581 <xvcmpnedp.>: Likewise.
1582 <xvcmpnesp>: Likewise.
1583 <xvcmpnesp.>: Likewise.
1585 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1588 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1591 2016-01-01 Alan Modra <amodra@gmail.com>
1593 Update year range in copyright notice of all files.
1595 For older changes see ChangeLog-2015
1597 Copyright (C) 2016 Free Software Foundation, Inc.
1599 Copying and distribution of this file, with or without modification,
1600 are permitted in any medium without royalty provided the copyright
1601 notice and this notice are preserved.
1607 version-control: never