RISC-V: Make disassebler work for --enable-targets=all config.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2018-02-22 Shea Levy <shea@shealevy.com>
2
3 * disassemble.c (ARCH_riscv): Define if ARCH_all.
4
5 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
6
7 * i386-opc.tbl: Add {rex},
8 * i386-tbl.h: Regenerated.
9
10 2018-02-20 Maciej W. Rozycki <macro@mips.com>
11
12 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
13 (mips16_opcodes): Replace `M' with `m' for "restore".
14
15 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
16
17 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
18
19 2018-02-13 Maciej W. Rozycki <macro@mips.com>
20
21 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
22 variable to `function_index'.
23
24 2018-02-13 Nick Clifton <nickc@redhat.com>
25
26 PR 22823
27 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
28 about truncation of printing.
29
30 2018-02-12 Henry Wong <henry@stuffedcow.net>
31
32 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
33
34 2018-02-05 Nick Clifton <nickc@redhat.com>
35
36 * po/pt_BR.po: Updated Brazilian Portuguese translation.
37
38 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
39
40 * i386-dis.c (enum): Add pconfig.
41 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
42 (cpu_flags): Add CpuPCONFIG.
43 * i386-opc.h (enum): Add CpuPCONFIG.
44 (i386_cpu_flags): Add cpupconfig.
45 * i386-opc.tbl: Add PCONFIG instruction.
46 * i386-init.h: Regenerate.
47 * i386-tbl.h: Likewise.
48
49 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
50
51 * i386-dis.c (enum): Add PREFIX_0F09.
52 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
53 (cpu_flags): Add CpuWBNOINVD.
54 * i386-opc.h (enum): Add CpuWBNOINVD.
55 (i386_cpu_flags): Add cpuwbnoinvd.
56 * i386-opc.tbl: Add WBNOINVD instruction.
57 * i386-init.h: Regenerate.
58 * i386-tbl.h: Likewise.
59
60 2018-01-17 Jim Wilson <jimw@sifive.com>
61
62 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
63
64 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
65
66 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
67 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
68 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
69 (cpu_flags): Add CpuIBT, CpuSHSTK.
70 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
71 (i386_cpu_flags): Add cpuibt, cpushstk.
72 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
73 * i386-init.h: Regenerate.
74 * i386-tbl.h: Likewise.
75
76 2018-01-16 Nick Clifton <nickc@redhat.com>
77
78 * po/pt_BR.po: Updated Brazilian Portugese translation.
79 * po/de.po: Updated German translation.
80
81 2018-01-15 Jim Wilson <jimw@sifive.com>
82
83 * riscv-opc.c (match_c_nop): New.
84 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
85
86 2018-01-15 Nick Clifton <nickc@redhat.com>
87
88 * po/uk.po: Updated Ukranian translation.
89
90 2018-01-13 Nick Clifton <nickc@redhat.com>
91
92 * po/opcodes.pot: Regenerated.
93
94 2018-01-13 Nick Clifton <nickc@redhat.com>
95
96 * configure: Regenerate.
97
98 2018-01-13 Nick Clifton <nickc@redhat.com>
99
100 2.30 branch created.
101
102 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
103
104 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
105 * i386-tbl.h: Regenerate.
106
107 2018-01-10 Jan Beulich <jbeulich@suse.com>
108
109 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
110 * i386-tbl.h: Re-generate.
111
112 2018-01-10 Jan Beulich <jbeulich@suse.com>
113
114 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
115 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
116 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
117 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
118 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
119 Disp8MemShift of AVX512VL forms.
120 * i386-tbl.h: Re-generate.
121
122 2018-01-09 Jim Wilson <jimw@sifive.com>
123
124 * riscv-dis.c (maybe_print_address): If base_reg is zero,
125 then the hi_addr value is zero.
126
127 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
128
129 * arm-dis.c (arm_opcodes): Add csdb.
130 (thumb32_opcodes): Add csdb.
131
132 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
133
134 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
135 * aarch64-asm-2.c: Regenerate.
136 * aarch64-dis-2.c: Regenerate.
137 * aarch64-opc-2.c: Regenerate.
138
139 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
140
141 PR gas/22681
142 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
143 Remove AVX512 vmovd with 64-bit operands.
144 * i386-tbl.h: Regenerated.
145
146 2018-01-05 Jim Wilson <jimw@sifive.com>
147
148 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
149 jalr.
150
151 2018-01-03 Alan Modra <amodra@gmail.com>
152
153 Update year range in copyright notice of all files.
154
155 2018-01-02 Jan Beulich <jbeulich@suse.com>
156
157 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
158 and OPERAND_TYPE_REGZMM entries.
159
160 For older changes see ChangeLog-2017
161 \f
162 Copyright (C) 2018 Free Software Foundation, Inc.
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