opcodes/ChangeLog

   1 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
   2
   3         * arc-dis.c (parse_disassembler_options): Use
   4         FOR_EACH_DISASSEMBLER_OPTION.
   5
   6 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
   7
   8         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
   9         disassembler option strings.
  10         (parse_cpu_option): Likewise.
  11
  12 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
  13
  14         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
  15         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
  16         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
  17         (aarch64_feature_dotprod, DOT_INSN): New.
  18         (udot, sdot): New.
  19         * aarch64-dis-2.c: Regenerated.
  20
  21 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
  22
  23         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
  24
  25 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
  26             Matthew Fortune  <matthew.fortune@imgtec.com>
  27             Andrew Bennett <andrew.bennett@imgtec.com>
  28
  29         * mips-formats.h (INT_BIAS): New macro.
  30         (INT_ADJ): Redefine in INT_BIAS terms.
  31         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
  32         (mips_print_save_restore): New function.
  33         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
  34         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
  35         call.
  36         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
  37         (print_mips16_insn_arg): Call `mips_print_save_restore' for
  38         OP_SAVE_RESTORE_LIST handling, factored out from here.
  39         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
  40         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
  41         (mips_builtin_opcodes): Add "restore" and "save" entries.
  42         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
  43         (IAMR2): New macro.
  44         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
  45
  46 2017-06-23  Andrew Waterman  <andrew@sifive.com>
  47
  48         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
  49         alias; do not mark SLTI instruction as an alias.
  50
  51 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  52
  53         * i386-dis.c (RM_0FAE_REG_5): Removed.
  54         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  55         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
  56         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
  57         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
  58         PREFIX_MOD_3_0F01_REG_5_RM_0.
  59         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
  60         PREFIX_MOD_3_0FAE_REG_5.
  61         (mod_table): Update MOD_0FAE_REG_5.
  62         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
  63         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
  64         * i386-tbl.h: Regenerated.
  65
  66 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  67
  68         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
  69         * i386-opc.tbl: Likewise.
  70         * i386-tbl.h: Regenerated.
  71
  72 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  73
  74         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
  75         and "jmp{&|}".
  76         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
  77         prefix.
  78
  79 2017-06-19  Nick Clifton  <nickc@redhat.com>
  80
  81         PR binutils/21614
  82         * score-dis.c (score_opcodes): Add sentinel.
  83
  84 2017-06-16  Alan Modra  <amodra@gmail.com>
  85
  86         * rx-decode.c: Regenerate.
  87
  88 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
  89
  90         PR binutils/21594
  91         * i386-dis.c (OP_E_register): Check valid bnd register.
  92         (OP_G): Likewise.
  93
  94 2017-06-15  Nick Clifton  <nickc@redhat.com>
  95
  96         PR binutils/21595
  97         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
  98         range value.
  99
 100 2017-06-15  Nick Clifton  <nickc@redhat.com>
 101
 102         PR binutils/21588
 103         * rl78-decode.opc (OP_BUF_LEN): Define.
 104         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 105         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 106         array.
 107         * rl78-decode.c: Regenerate.
 108
 109 2017-06-15  Nick Clifton  <nickc@redhat.com>
 110
 111         PR binutils/21586
 112         * bfin-dis.c (gregs): Clip index to prevent overflow.
 113         (regs): Likewise.
 114         (regs_lo): Likewise.
 115         (regs_hi): Likewise.
 116
 117 2017-06-14  Nick Clifton  <nickc@redhat.com>
 118
 119         PR binutils/21576
 120         * score7-dis.c (score_opcodes): Add sentinel.
 121
 122 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 123
 124         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 125         * arm-dis.c: Likewise.
 126         * ia64-dis.c: Likewise.
 127         * mips-dis.c: Likewise.
 128         * spu-dis.c: Likewise.
 129         * disassemble.h (print_insn_aarch64): New declaration, moved from
 130         include/dis-asm.h.
 131         (print_insn_big_arm, print_insn_big_mips): Likewise.
 132         (print_insn_i386, print_insn_ia64): Likewise.
 133         (print_insn_little_arm, print_insn_little_mips): Likewise.
 134
 135 2017-06-14  Nick Clifton  <nickc@redhat.com>
 136
 137         PR binutils/21587
 138         * rx-decode.opc: Include libiberty.h
 139         (GET_SCALE): New macro - validates access to SCALE array.
 140         (GET_PSCALE): New macro - validates access to PSCALE array.
 141         (DIs, SIs, S2Is, rx_disp): Use new macros.
 142         * rx-decode.c: Regenerate.
 143
 144 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 145
 146         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 147
 148 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 149
 150         * arc-dis.c (enforced_isa_mask): Declare.
 151         (cpu_types): Likewise.
 152         (parse_cpu_option): New function.
 153         (parse_disassembler_options): Use it.
 154         (print_insn_arc): Use enforced_isa_mask.
 155         (print_arc_disassembler_options): Document new options.
 156
 157 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 158
 159         * alpha-dis.c: Include disassemble.h, don't include
 160         dis-asm.h.
 161         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 162         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 163         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 164         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 165         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 166         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 167         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 168         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 169         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 170         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 171         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 172         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 173         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 174         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 175         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 176         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 177         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 178         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 179         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 180         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 181         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 182         * z80-dis.c, z8k-dis.c: Likewise.
 183         * disassemble.h: New file.
 184
 185 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 186
 187         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 188         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 189
 190 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 191
 192         * disassemble.c (disassembler): Add arguments a, big and mach.
 193         Use them.
 194
 195 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 196
 197         * i386-dis.c (NOTRACK_Fixup): New.
 198         (NOTRACK): Likewise.
 199         (NOTRACK_PREFIX): Likewise.
 200         (last_active_prefix): Likewise.
 201         (reg_table): Use NOTRACK on indirect call and jmp.
 202         (ckprefix): Set last_active_prefix.
 203         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 204         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 205         * i386-opc.h (NoTrackPrefixOk): New.
 206         (i386_opcode_modifier): Add notrackprefixok.
 207         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 208         Add notrack.
 209         * i386-tbl.h: Regenerated.
 210
 211 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 212
 213         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 214         (X_IMM2): Define.
 215         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 216         bfd_mach_sparc_v9m8.
 217         (print_insn_sparc): Handle new operand types.
 218         * sparc-opc.c (MASK_M8): Define.
 219         (v6): Add MASK_M8.
 220         (v6notlet): Likewise.
 221         (v7): Likewise.
 222         (v8): Likewise.
 223         (v9): Likewise.
 224         (v9a): Likewise.
 225         (v9b): Likewise.
 226         (v9c): Likewise.
 227         (v9d): Likewise.
 228         (v9e): Likewise.
 229         (v9v): Likewise.
 230         (v9m): Likewise.
 231         (v9andleon): Likewise.
 232         (m8): Define.
 233         (HWS_VM8): Define.
 234         (HWS2_VM8): Likewise.
 235         (sparc_opcode_archs): Add entry for "m8".
 236         (sparc_opcodes): Add OSA2017 and M8 instructions
 237         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 238         fpx{ll,ra,rl}64x,
 239         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 240         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 241         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 242         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 243         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 244         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 245         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 246         ASI_CORE_SELECT_COMMIT_NHT.
 247
 248 2017-05-18  Alan Modra  <amodra@gmail.com>
 249
 250         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 251         * aarch64-dis.c: Likewise.
 252         * aarch64-gen.c: Likewise.
 253         * aarch64-opc.c: Likewise.
 254
 255 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 256             Matthew Fortune  <matthew.fortune@imgtec.com>
 257
 258         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 259         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 260         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 261         (print_insn_arg) <OP_REG28>: Add handler.
 262         (validate_insn_args) <OP_REG28>: Handle.
 263         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 264         32-bit encoding and 9-bit immediates.
 265         (print_insn_mips16): Handle MIPS16 instructions that require
 266         32-bit encoding and MFC0/MTC0 operand decoding.
 267         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 268         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 269         (RD_C0, WR_C0, E2, E2MT): New macros.
 270         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 271         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 272         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 273         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 274         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 275         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 276         instructions, "swl", "swr", "sync" and its "sync_acquire",
 277         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 278         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 279         regular/extended entries for original MIPS16 ISA revision
 280         instructions whose extended forms are subdecoded in the MIPS16e2
 281         ISA revision: "li", "sll" and "srl".
 282
 283 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 284
 285         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 286         reference in CP0 move operand decoding.
 287
 288 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 289
 290         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 291         type to hexadecimal.
 292         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 293
 294 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 295
 296         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 297         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 298         "sync_rmb" and "sync_wmb" as aliases.
 299         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 300         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 301
 302 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 303
 304         * arc-dis.c (parse_option): Update quarkse_em option..
 305         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 306         QUARKSE1.
 307         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 308
 309 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 310
 311         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 312
 313 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 314
 315         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 316         register.
 317
 318 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 319
 320         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 321         and branches and not synthetic data instructions.
 322
 323 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 324
 325         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 326
 327 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 328
 329         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 330         * arc-opc.c (insert_r13el): New function.
 331         (R13_EL): Define.
 332         * arc-tbl.h: Add new enter/leave variants.
 333
 334 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 335
 336         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 337
 338 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 339
 340         * mips-dis.c (print_mips_disassembler_options): Add
 341         `no-aliases'.
 342
 343 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 344
 345         * mips16-opc.c (AL): New macro.
 346         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 347         of "ld" and "lw" as aliases.
 348
 349 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 350
 351         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 352         arguments.
 353
 354 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 355             Alan Modra  <amodra@gmail.com>
 356
 357         * ppc-opc.c (ELEV): Define.
 358         (vle_opcodes): Add se_rfgi and e_sc.
 359         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 360         for E200Z4.
 361
 362 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 363
 364         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 365
 366 2017-04-21  Nick Clifton  <nickc@redhat.com>
 367
 368         PR binutils/21380
 369         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 370         LD3R and LD4R.
 371
 372 2017-04-13  Alan Modra  <amodra@gmail.com>
 373
 374         * epiphany-desc.c: Regenerate.
 375         * fr30-desc.c: Regenerate.
 376         * frv-desc.c: Regenerate.
 377         * ip2k-desc.c: Regenerate.
 378         * iq2000-desc.c: Regenerate.
 379         * lm32-desc.c: Regenerate.
 380         * m32c-desc.c: Regenerate.
 381         * m32r-desc.c: Regenerate.
 382         * mep-desc.c: Regenerate.
 383         * mt-desc.c: Regenerate.
 384         * or1k-desc.c: Regenerate.
 385         * xc16x-desc.c: Regenerate.
 386         * xstormy16-desc.c: Regenerate.
 387
 388 2017-04-11  Alan Modra  <amodra@gmail.com>
 389
 390         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 391         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 392         PPC_OPCODE_TMR for e6500.
 393         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 394         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 395         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 396         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 397         (PPCHTM): Define as PPC_OPCODE_POWER8.
 398         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 399
 400 2017-04-10  Alan Modra  <amodra@gmail.com>
 401
 402         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 403         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 404         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 405         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 406
 407 2017-04-09  Pip Cet  <pipcet@gmail.com>
 408
 409         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 410         appropriate floating-point precision directly.
 411
 412 2017-04-07  Alan Modra  <amodra@gmail.com>
 413
 414         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 415         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 416         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 417         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 418         vector instructions with E6500 not PPCVEC2.
 419
 420 2017-04-06  Pip Cet  <pipcet@gmail.com>
 421
 422         * Makefile.am: Add wasm32-dis.c.
 423         * configure.ac: Add wasm32-dis.c to wasm32 target.
 424         * disassemble.c: Add wasm32 disassembler code.
 425         * wasm32-dis.c: New file.
 426         * Makefile.in: Regenerate.
 427         * configure: Regenerate.
 428         * po/POTFILES.in: Regenerate.
 429         * po/opcodes.pot: Regenerate.
 430
 431 2017-04-05  Pedro Alves  <palves@redhat.com>
 432
 433         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 434         * arm-dis.c (parse_arm_disassembler_options): Constify.
 435         * ppc-dis.c (powerpc_init_dialect): Constify local.
 436         * vax-dis.c (parse_disassembler_options): Constify.
 437
 438 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 439
 440         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 441         RISCV_GP_SYMBOL.
 442
 443 2017-03-30  Pip Cet  <pipcet@gmail.com>
 444
 445         * configure.ac: Add (empty) bfd_wasm32_arch target.
 446         * configure: Regenerate
 447         * po/opcodes.pot: Regenerate.
 448
 449 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 450
 451         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 452         OSA2015.
 453         * opcodes/sparc-opc.c (asi_table): New ASIs.
 454
 455 2017-03-29  Alan Modra  <amodra@gmail.com>
 456
 457         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 458         "raw" option.
 459         (lookup_powerpc): Don't special case -1 dialect.  Handle
 460         PPC_OPCODE_RAW.
 461         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 462         lookup_powerpc call, pass it on second.
 463
 464 2017-03-27  Alan Modra  <amodra@gmail.com>
 465
 466         PR 21303
 467         * ppc-dis.c (struct ppc_mopt): Comment.
 468         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 469
 470 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 471
 472         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 473         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 474         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 475         (insert_nps_misc_imm_offset): New function.
 476         (extract_nps_misc imm_offset): New function.
 477         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 478         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 479
 480 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 481
 482         * s390-mkopc.c (main): Remove vx2 check.
 483         * s390-opc.txt: Remove vx2 instruction flags.
 484
 485 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 486
 487         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 488         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 489         (insert_nps_imm_offset): New function.
 490         (extract_nps_imm_offset): New function.
 491         (insert_nps_imm_entry): New function.
 492         (extract_nps_imm_entry): New function.
 493
 494 2017-03-17  Alan Modra  <amodra@gmail.com>
 495
 496         PR 21248
 497         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 498         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 499         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 500
 501 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 502
 503         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 504         <c.andi>: Likewise.
 505         <c.addiw> Likewise.
 506
 507 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 508
 509         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 510
 511 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 512
 513         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 514         <srl> Likewise.
 515         <srai> Likewise.
 516         <sra> Likewise.
 517
 518 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 519
 520         * i386-gen.c (opcode_modifiers): Replace S with Load.
 521         * i386-opc.h (S): Removed.
 522         (Load): New.
 523         (i386_opcode_modifier): Replace s with load.
 524         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 525         and {evex}.  Replace S with Load.
 526         * i386-tbl.h: Regenerated.
 527
 528 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 529
 530         * i386-opc.tbl: Use CpuCET on rdsspq.
 531         * i386-tbl.h: Regenerated.
 532
 533 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 534
 535         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 536         <vsx>: Do not use PPC_OPCODE_VSX3;
 537
 538 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 539
 540         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 541
 542 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 543
 544         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 545         (MOD_0F1E_PREFIX_1): Likewise.
 546         (MOD_0F38F5_PREFIX_2): Likewise.
 547         (MOD_0F38F6_PREFIX_0): Likewise.
 548         (RM_0F1E_MOD_3_REG_7): Likewise.
 549         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 550         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 551         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 552         (PREFIX_0F1E): Likewise.
 553         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 554         (PREFIX_0F38F5): Likewise.
 555         (dis386_twobyte): Use PREFIX_0F1E.
 556         (reg_table): Add REG_0F1E_MOD_3.
 557         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 558         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 559         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 560         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 561         (three_byte_table): Use PREFIX_0F38F5.
 562         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 563         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 564         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 565         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 566         PREFIX_MOD_3_0F01_REG_5_RM_2.
 567         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 568         (cpu_flags): Add CpuCET.
 569         * i386-opc.h (CpuCET): New enum.
 570         (CpuUnused): Commented out.
 571         (i386_cpu_flags): Add cpucet.
 572         * i386-opc.tbl: Add Intel CET instructions.
 573         * i386-init.h: Regenerated.
 574         * i386-tbl.h: Likewise.
 575
 576 2017-03-06  Alan Modra  <amodra@gmail.com>
 577
 578         PR 21124
 579         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 580         (extract_raq, extract_ras, extract_rbx): New functions.
 581         (powerpc_operands): Use opposite corresponding insert function.
 582         (Q_MASK): Define.
 583         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 584         register restriction.
 585
 586 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 587
 588         * disassemble.c Include "safe-ctype.h".
 589         (disassemble_init_for_target): Handle s390 init.
 590         (remove_whitespace_and_extra_commas): New function.
 591         (disassembler_options_cmp): Likewise.
 592         * arm-dis.c: Include "libiberty.h".
 593         (NUM_ELEM): Delete.
 594         (regnames): Use long disassembler style names.
 595         Add force-thumb and no-force-thumb options.
 596         (NUM_ARM_REGNAMES): Rename from this...
 597         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 598         (get_arm_regname_num_options): Delete.
 599         (set_arm_regname_option): Likewise.
 600         (get_arm_regnames): Likewise.
 601         (parse_disassembler_options): Likewise.
 602         (parse_arm_disassembler_option): Rename from this...
 603         (parse_arm_disassembler_options): ...to this.  Make static.
 604         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 605         (print_insn): Use parse_arm_disassembler_options.
 606         (disassembler_options_arm): New function.
 607         (print_arm_disassembler_options): Handle updated regnames.
 608         * ppc-dis.c: Include "libiberty.h".
 609         (ppc_opts): Add "32" and "64" entries.
 610         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 611         (powerpc_init_dialect): Add break to switch statement.
 612         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 613         (disassembler_options_powerpc): New function.
 614         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 615         Remove printing of "32" and "64".
 616         * s390-dis.c: Include "libiberty.h".
 617         (init_flag): Remove unneeded variable.
 618         (struct s390_options_t): New structure type.
 619         (options): New structure.
 620         (init_disasm): Rename from this...
 621         (disassemble_init_s390): ...to this.  Add initializations for
 622         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 623         (print_insn_s390): Delete call to init_disasm.
 624         (disassembler_options_s390): New function.
 625         (print_s390_disassembler_options): Print using information from
 626         struct 'options'.
 627         * po/opcodes.pot: Regenerate.
 628
 629 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 630
 631         * i386-dis.c (PCMPESTR_Fixup): New.
 632         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 633         (prefix_table): Use PCMPESTR_Fixup.
 634         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 635         PCMPESTR_Fixup.
 636         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 637         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 638         Split 64-bit and non-64-bit variants.
 639         * opcodes/i386-tbl.h: Re-generate.
 640
 641 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 642
 643         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 644         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 645         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 646         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 647         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 648         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 649         (OP_SVE_V_HSD): New macros.
 650         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 651         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 652         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 653         (aarch64_opcode_table): Add new SVE instructions.
 654         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 655         for rotation operands.  Add new SVE operands.
 656         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 657         (ins_sve_quad_index): Likewise.
 658         (ins_imm_rotate): Split into...
 659         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 660         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 661         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 662         functions.
 663         (aarch64_ins_sve_addr_ri_s4): New function.
 664         (aarch64_ins_sve_quad_index): Likewise.
 665         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 666         * aarch64-asm-2.c: Regenerate.
 667         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 668         (ext_sve_quad_index): Likewise.
 669         (ext_imm_rotate): Split into...
 670         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 671         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 672         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 673         functions.
 674         (aarch64_ext_sve_addr_ri_s4): New function.
 675         (aarch64_ext_sve_quad_index): Likewise.
 676         (aarch64_ext_sve_index): Allow quad indices.
 677         (do_misc_decoding): Likewise.
 678         * aarch64-dis-2.c: Regenerate.
 679         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 680         aarch64_field_kinds.
 681         (OPD_F_OD_MASK): Widen by one bit.
 682         (OPD_F_NO_ZR): Bump accordingly.
 683         (get_operand_field_width): New function.
 684         * aarch64-opc.c (fields): Add new SVE fields.
 685         (operand_general_constraint_met_p): Handle new SVE operands.
 686         (aarch64_print_operand): Likewise.
 687         * aarch64-opc-2.c: Regenerate.
 688
 689 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 690
 691         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 692         (aarch64_feature_compnum): ...this.
 693         (SIMD_V8_3): Replace with...
 694         (COMPNUM): ...this.
 695         (CNUM_INSN): New macro.
 696         (aarch64_opcode_table): Use it for the complex number instructions.
 697
 698 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 699
 700         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 701
 702 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 703
 704         Add support for associating SPARC ASIs with an architecture level.
 705         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 706         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 707         decoding of SPARC ASIs.
 708
 709 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 710
 711         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 712         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 713
 714 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 715
 716         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 717         1 (instead of to itself). Correct typo.
 718
 719 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 720
 721         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 722         pseudoinstructions.
 723
 724 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 725
 726         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 727         (aarch64_sys_reg_supported_p): Handle them.
 728
 729 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 730
 731         * arc-opc.c (UIMM6_20R): Define.
 732         (SIMM12_20): Use above.
 733         (SIMM12_20R): Define.
 734         (SIMM3_5_S): Use above.
 735         (UIMM7_A32_11R_S): Define.
 736         (UIMM7_9_S): Use above.
 737         (UIMM3_13R_S): Define.
 738         (SIMM11_A32_7_S): Use above.
 739         (SIMM9_8R): Define.
 740         (UIMM10_A32_8_S): Use above.
 741         (UIMM8_8R_S): Define.
 742         (W6): Use above.
 743         (arc_relax_opcodes): Use all above defines.
 744
 745 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 746
 747         * arc-regs.h: Distinguish some of the registers different on
 748         ARC700 and HS38 cpus.
 749
 750 2017-02-14  Alan Modra  <amodra@gmail.com>
 751
 752         PR 21118
 753         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 754         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 755
 756 2017-02-11  Stafford Horne  <shorne@gmail.com>
 757             Alan Modra  <amodra@gmail.com>
 758
 759         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 760         Use insn_bytes_value and insn_int_value directly instead.  Don't
 761         free allocated memory until function exit.
 762
 763 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 764
 765         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 766
 767 2017-02-03  Nick Clifton  <nickc@redhat.com>
 768
 769         PR 21096
 770         * aarch64-opc.c (print_register_list): Ensure that the register
 771         list index will fir into the tb buffer.
 772         (print_register_offset_address): Likewise.
 773         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 774
 775 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 776
 777         PR 21056
 778         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 779         instructions when the previous fetch packet ends with a 32-bit
 780         instruction.
 781
 782 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 783
 784         * pru-opc.c: Remove vague reference to a future GDB port.
 785
 786 2017-01-20  Nick Clifton  <nickc@redhat.com>
 787
 788         * po/ga.po: Updated Irish translation.
 789
 790 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 791
 792         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 793
 794 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 795
 796         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 797         if FETCH_DATA returns 0.
 798         (m68k_scan_mask): Likewise.
 799         (print_insn_m68k): Update code to handle -1 return value.
 800
 801 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 802
 803         * m68k-dis.c (enum print_insn_arg_error): New.
 804         (NEXTBYTE): Replace -3 with
 805         PRINT_INSN_ARG_MEMORY_ERROR.
 806         (NEXTULONG): Likewise.
 807         (NEXTSINGLE): Likewise.
 808         (NEXTDOUBLE): Likewise.
 809         (NEXTDOUBLE): Likewise.
 810         (NEXTPACKED): Likewise.
 811         (FETCH_ARG): Likewise.
 812         (FETCH_DATA): Update comments.
 813         (print_insn_arg): Update comments. Replace magic numbers with
 814         enum.
 815         (match_insn_m68k): Likewise.
 816
 817 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 818
 819         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 820         * i386-dis-evex.h (evex_table): Updated.
 821         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 822         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 823         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 824         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 825         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 826         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 827         * i386-init.h: Regenerate.
 828         * i386-tbl.h: Ditto.
 829
 830 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 831
 832         * msp430-dis.c (msp430_singleoperand): Return -1 if
 833         msp430dis_opcode_signed returns false.
 834         (msp430_doubleoperand): Likewise.
 835         (msp430_branchinstr): Return -1 if
 836         msp430dis_opcode_unsigned returns false.
 837         (msp430x_calla_instr): Likewise.
 838         (print_insn_msp430): Likewise.
 839
 840 2017-01-05  Nick Clifton  <nickc@redhat.com>
 841
 842         PR 20946
 843         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 844         could not be matched.
 845         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 846         NULL.
 847
 848 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 849
 850         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 851         (aarch64_opcode_table): Use RCPC_INSN.
 852
 853 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 854
 855         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 856         extension.
 857         * riscv-opcodes/all-opcodes: Likewise.
 858
 859 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 860
 861         * riscv-dis.c (print_insn_args): Add fall through comment.
 862
 863 2017-01-03  Nick Clifton  <nickc@redhat.com>
 864
 865         * po/sr.po: New Serbian translation.
 866         * configure.ac (ALL_LINGUAS): Add sr.
 867         * configure: Regenerate.
 868
 869 2017-01-02  Alan Modra  <amodra@gmail.com>
 870
 871         * epiphany-desc.h: Regenerate.
 872         * epiphany-opc.h: Regenerate.
 873         * fr30-desc.h: Regenerate.
 874         * fr30-opc.h: Regenerate.
 875         * frv-desc.h: Regenerate.
 876         * frv-opc.h: Regenerate.
 877         * ip2k-desc.h: Regenerate.
 878         * ip2k-opc.h: Regenerate.
 879         * iq2000-desc.h: Regenerate.
 880         * iq2000-opc.h: Regenerate.
 881         * lm32-desc.h: Regenerate.
 882         * lm32-opc.h: Regenerate.
 883         * m32c-desc.h: Regenerate.
 884         * m32c-opc.h: Regenerate.
 885         * m32r-desc.h: Regenerate.
 886         * m32r-opc.h: Regenerate.
 887         * mep-desc.h: Regenerate.
 888         * mep-opc.h: Regenerate.
 889         * mt-desc.h: Regenerate.
 890         * mt-opc.h: Regenerate.
 891         * or1k-desc.h: Regenerate.
 892         * or1k-opc.h: Regenerate.
 893         * xc16x-desc.h: Regenerate.
 894         * xc16x-opc.h: Regenerate.
 895         * xstormy16-desc.h: Regenerate.
 896         * xstormy16-opc.h: Regenerate.
 897
 898 2017-01-02  Alan Modra  <amodra@gmail.com>
 899
 900         Update year range in copyright notice of all files.
 901
 902 For older changes see ChangeLog-2016
 903 \f
 904 Copyright (C) 2017 Free Software Foundation, Inc.
 905
 906 Copying and distribution of this file, with or without modification,
 907 are permitted in any medium without royalty provided the copyright
 908 notice and this notice are preserved.
 909
 910 Local Variables:
 911 mode: change-log
 912 left-margin: 8
 913 fill-column: 74
 914 version-control: never
 915 End: