opcodes/ChangeLog

   1 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_feature_lor): New.
   4         (LOR): New.
   5         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
   6         "stllrb", "stllrh".
   7         * aarch64-asm-2.c: Regenerate.
   8         * aarch64-dis-2.c: Regenerate.
   9         * aarch64-opc-2.c: Regenerate.
  10
  11 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
  12
  13         * aarch64-opc.c (F_ARCHEXT): New.
  14         (aarch64_sys_regs): Add "pan".
  15         (aarch64_sys_reg_supported_p): New.
  16         (aarch64_pstatefields): Add "pan".
  17         (aarch64_pstatefield_supported_p): New.
  18
  19 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  20
  21         * i386-tbl.h: Regenerate.
  22
  23 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-dis.c (print_insn): Swap rounding mode specifier and
  26         general purpose register in Intel mode.
  27
  28 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
  31         * i386-tbl.h: Regenerate.
  32
  33 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
  36         * i386-init.h: Regenerated.
  37
  38 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
  39
  40         PR binutis/18386
  41         * i386-dis.c: Add comments for '@'.
  42         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
  43         (enum x86_64_isa): New.
  44         (isa64): Likewise.
  45         (print_i386_disassembler_options): Add amd64 and intel64.
  46         (print_insn): Handle amd64 and intel64.
  47         (putop): Handle '@'.
  48         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
  49         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
  50         * i386-opc.h (AMD64): New.
  51         (CpuIntel64): Likewise.
  52         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
  53         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
  54         Mark direct call/jmp without Disp16|Disp32 as Intel64.
  55         * i386-init.h: Regenerated.
  56         * i386-tbl.h: Likewise.
  57
  58 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
  59
  60         * ppc-opc.c (IH) New define.
  61         (powerpc_opcodes) <wait>: Do not enable for POWER7.
  62         <tlbie>: Add RS operand for POWER7.
  63         <slbia>: Add IH operand for POWER6.
  64
  65 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
  68         direct branch.
  69         (jmp): Likewise.
  70         * i386-tbl.h: Regenerated.
  71
  72 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
  73
  74         * configure.ac: Support bfd_iamcu_arch.
  75         * disassemble.c (disassembler): Support bfd_iamcu_arch.
  76         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
  77         CPU_IAMCU_COMPAT_FLAGS.
  78         (cpu_flags): Add CpuIAMCU.
  79         * i386-opc.h (CpuIAMCU): New.
  80         (i386_cpu_flags): Add cpuiamcu.
  81         * configure: Regenerated.
  82         * i386-init.h: Likewise.
  83         * i386-tbl.h: Likewise.
  84
  85 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
  86
  87         PR binutis/18386
  88         * i386-dis.c (X86_64_E8): New.
  89         (X86_64_E9): Likewise.
  90         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
  91         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
  92         (x86_64_table): Add X86_64_E8 and X86_64_E9.
  93         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
  94         (putop): Handle '^'.
  95         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
  96         REX_W.
  97
  98 2015-04-30  DJ Delorie  <dj@redhat.com>
  99
 100         * disassemble.c (disassembler): Choose suitable disassembler based
 101         on E_ABI.
 102         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 103         it to decode mul/div insns.
 104         * rl78-decode.c: Regenerate.
 105         * rl78-dis.c (print_insn_rl78): Rename to...
 106         (print_insn_rl78_common): ...this, take ISA parameter.
 107         (print_insn_rl78): New.
 108         (print_insn_rl78_g10): New.
 109         (print_insn_rl78_g13): New.
 110         (print_insn_rl78_g14): New.
 111         (rl78_get_disassembler): New.
 112
 113 2015-04-29  Nick Clifton  <nickc@redhat.com>
 114
 115         * po/fr.po: Updated French translation.
 116
 117 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 118
 119         * ppc-opc.c (DCBT_EO): New define.
 120         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 121         <lharx>: Likewise.
 122         <stbcx.>: Likewise.
 123         <sthcx.>: Likewise.
 124         <waitrsv>: Do not enable for POWER7 and later.
 125         <waitimpl>: Likewise.
 126         <dcbt>: Default to the two operand form of the instruction for all
 127         "old" cpus.  For "new" cpus, use the operand ordering that matches
 128         whether the cpu is server or embedded.
 129         <dcbtst>: Likewise.
 130
 131 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 132
 133         * s390-opc.c: New instruction type VV0UU2.
 134         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 135         and WFC.
 136
 137 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 140         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 141         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 142         (vfpclasspd, vfpclassps): Add %XZ.
 143
 144 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 145
 146         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 147         (PREFIX_UD_REPZ): Likewise.
 148         (PREFIX_UD_REPNZ): Likewise.
 149         (PREFIX_UD_DATA): Likewise.
 150         (PREFIX_UD_ADDR): Likewise.
 151         (PREFIX_UD_LOCK): Likewise.
 152
 153 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 154
 155         * i386-dis.c (prefix_requirement): Removed.
 156         (print_insn): Don't set prefix_requirement.  Check
 157         dp->prefix_requirement instead of prefix_requirement.
 158
 159 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 160
 161         PR binutils/17898
 162         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 163         (PREFIX_MOD_0_0FC7_REG_6): This.
 164         (PREFIX_MOD_3_0FC7_REG_6): New.
 165         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 166         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 167         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 168         PREFIX_MOD_3_0FC7_REG_7.
 169         (mod_table): Replace PREFIX_0FC7_REG_6 with
 170         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 171         PREFIX_MOD_3_0FC7_REG_7.
 172
 173 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 174
 175         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 176         (PREFIX_MANDATORY_REPNZ): Likewise.
 177         (PREFIX_MANDATORY_DATA): Likewise.
 178         (PREFIX_MANDATORY_ADDR): Likewise.
 179         (PREFIX_MANDATORY_LOCK): Likewise.
 180         (PREFIX_MANDATORY): Likewise.
 181         (PREFIX_UD_SHIFT): Set to 8
 182         (PREFIX_UD_REPZ): Updated.
 183         (PREFIX_UD_REPNZ): Likewise.
 184         (PREFIX_UD_DATA): Likewise.
 185         (PREFIX_UD_ADDR): Likewise.
 186         (PREFIX_UD_LOCK): Likewise.
 187         (PREFIX_IGNORED_SHIFT): New.
 188         (PREFIX_IGNORED_REPZ): Likewise.
 189         (PREFIX_IGNORED_REPNZ): Likewise.
 190         (PREFIX_IGNORED_DATA): Likewise.
 191         (PREFIX_IGNORED_ADDR): Likewise.
 192         (PREFIX_IGNORED_LOCK): Likewise.
 193         (PREFIX_OPCODE): Likewise.
 194         (PREFIX_IGNORED): Likewise.
 195         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 196         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 197         (three_byte_table): Likewise.
 198         (mod_table): Likewise.
 199         (mandatory_prefix): Renamed to ...
 200         (prefix_requirement): This.
 201         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 202         Update PREFIX_90 entry.
 203         (get_valid_dis386): Check prefix_requirement to see if a prefix
 204         should be ignored.
 205         (print_insn): Replace mandatory_prefix with prefix_requirement.
 206
 207 2015-04-15  Renlin Li  <renlin.li@arm.com>
 208
 209         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 210         use it for ssat and ssat16.
 211         (print_insn_thumb32): Add handle case for 'D' control code.
 212
 213 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 214             H.J. Lu  <hongjiu.lu@intel.com>
 215
 216         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 217         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 218         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 219         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 220         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 221         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 222         Fill prefix_requirement field.
 223         (struct dis386): Add prefix_requirement field.
 224         (dis386): Fill prefix_requirement field.
 225         (dis386_twobyte): Ditto.
 226         (twobyte_has_mandatory_prefix_: Remove.
 227         (reg_table): Fill prefix_requirement field.
 228         (prefix_table): Ditto.
 229         (x86_64_table): Ditto.
 230         (three_byte_table): Ditto.
 231         (xop_table): Ditto.
 232         (vex_table): Ditto.
 233         (vex_len_table): Ditto.
 234         (vex_w_table): Ditto.
 235         (mod_table): Ditto.
 236         (bad_opcode): Ditto.
 237         (print_insn): Use prefix_requirement.
 238         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 239         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 240         (float_reg): Ditto.
 241
 242 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 243
 244         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 245
 246 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 247
 248         * Makefile.in: Regenerated.
 249
 250 2015-03-25  Anton Blanchard  <anton@samba.org>
 251
 252         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 253         powerpc_opcd_indices and vle_opcd_indices once.
 254
 255 2015-03-25  Anton Blanchard  <anton@samba.org>
 256
 257         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 258
 259 2015-03-24  Terry Guo  <terry.guo@arm.com>
 260
 261         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 262         (opcode16): Likewise.
 263         (coprocessor_opcodes): Replace bit with feature struct.
 264         (neon_opcodes): Likewise.
 265         (arm_opcodes): Likewise.
 266         (thumb_opcodes): Likewise.
 267         (thumb32_opcodes): Likewise.
 268         (print_insn_coprocessor): Likewise.
 269         (print_insn_arm): Likewise.
 270         (select_arm_features): Follow new feature struct.
 271
 272 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 273
 274         * i386-dis.c (rm_table): Add clzero.
 275         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 276         Add CPU_CLZERO_FLAGS.
 277         (cpu_flags): Add CpuCLZERO.
 278         * i386-opc.h: Add CpuCLZERO.
 279         * i386-opc.tbl: Add clzero.
 280         * i386-init.h: Re-generated.
 281         * i386-tbl.h: Re-generated.
 282
 283 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 284
 285         * mips-opc.c (decode_mips_operand): Fix constraint issues
 286         with u and y operands.
 287
 288 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 289
 290         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 291
 292 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 293
 294         * s390-opc.c: Add new IBM z13 instructions.
 295         * s390-opc.txt: Likewise.
 296
 297 2015-03-10  Renlin Li  <renlin.li@arm.com>
 298
 299         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 300         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 301         related alias.
 302         * aarch64-asm-2.c: Regenerate.
 303         * aarch64-dis-2.c: Likewise.
 304         * aarch64-opc-2.c: Likewise.
 305
 306 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 307
 308         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 309
 310 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 311
 312         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 313         arch_sh_up.
 314         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 315         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 316
 317 2015-02-23  Vinay  <Vinay.G@kpit.com>
 318
 319         * rl78-decode.opc (MOV): Added space between two operands for
 320         'mov' instruction in index addressing mode.
 321         * rl78-decode.c: Regenerate.
 322
 323 2015-02-19  Pedro Alves  <palves@redhat.com>
 324
 325         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 326
 327 2015-02-10  Pedro Alves  <palves@redhat.com>
 328             Tom Tromey  <tromey@redhat.com>
 329
 330         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 331         microblaze_and, microblaze_xor.
 332         * microblaze-opc.h (opcodes): Adjust.
 333
 334 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 335
 336         * Makefile.am: Add FT32 files.
 337         * configure.ac: Handle FT32.
 338         * disassemble.c (disassembler): Call print_insn_ft32.
 339         * ft32-dis.c: New file.
 340         * ft32-opc.c: New file.
 341         * Makefile.in: Regenerate.
 342         * configure: Regenerate.
 343         * po/POTFILES.in: Regenerate.
 344
 345 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 346
 347         * nds32-asm.c (keyword_sr): Add new system registers.
 348
 349 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 350
 351         * s390-dis.c (s390_extract_operand): Support vector register
 352         operands.
 353         (s390_print_insn_with_opcode): Support new operands types and add
 354         new handling of optional operands.
 355         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 356         and include opcode/s390.h instead.
 357         (struct op_struct): New field `flags'.
 358         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 359         (dumpTable): Dump flags.
 360         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 361         string.
 362         * s390-opc.c: Add new operands types, instruction formats, and
 363         instruction masks.
 364         (s390_opformats): Add new formats for .insn.
 365         * s390-opc.txt: Add new instructions.
 366
 367 2015-01-01  Alan Modra  <amodra@gmail.com>
 368
 369         Update year range in copyright notice of all files.
 370
 371 For older changes see ChangeLog-2014
 372 \f
 373 Copyright (C) 2015 Free Software Foundation, Inc.
 374
 375 Copying and distribution of this file, with or without modification,
 376 are permitted in any medium without royalty provided the copyright
 377 notice and this notice are preserved.
 378
 379 Local Variables:
 380 mode: change-log
 381 left-margin: 8
 382 fill-column: 74
 383 version-control: never
 384 End: