1 2018-01-02 Jan Beulich <jbeulich@suse.com>
3 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
4 and OPERAND_TYPE_REGZMM entries.
6 2017-12-20 Jim Wilson <jimw@sifive.com>
8 * riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New.
9 (riscv_opcodes) <li>: Delete "d,0" line. Change Cj to Co.
10 <andi, and, add, addiw, addw, c.addi>: Change Cj to Co.
11 <add>: Add explanatory comment for 4-operand add instruction.
12 <c.nop>: Add support for immediate operand.
13 <c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add.
14 <c.lui>: Use match_c_lui_with_hint instead of match_c_lui.
15 <c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.
17 2017-12-19 Tamar Christina <tamar.christina@arm.com>
20 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
22 * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
24 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
25 * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
27 2017-12-19 Tamar Christina <tamar.christina@arm.com>
30 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
32 2017-12-18 Jan Beulich <jbeulich@suse.com>
34 * i386-gen.c (operand_type_init): Delete OPERAND_TYPE_REGYMM and
35 OPERAND_TYPE_REGZMM entries.
36 * i386-opc.h (enum of opcode modifiers): Extend comment.
37 i386-opc.tbl (vaddpd, vaddps, vaddsubpd, vaddsubps, vandnpd,
38 vandnps, vandpd, vandps, vblendpd, vblendps, vblendvpd,
39 vblendvps, vbroadcastss, vcmpeq_ospd, vcmpeq_osps, vcmpeqpd,
40 vcmpeqps, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uspd, vcmpeq_usps,
41 vcmpfalse_ospd, vcmpfalse_osps, vcmpfalsepd, vcmpfalseps,
42 vcmpge_oqpd, vcmpge_oqps, vcmpgepd, vcmpgeps, vcmpgt_oqpd,
43 vcmpgt_oqps, vcmpgtpd, vcmpgtps, vcmple_oqpd, vcmple_oqps,
44 vcmplepd, vcmpleps, vcmplt_oqpd, vcmplt_oqps, vcmpltpd,
45 vcmpltps, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_ospd,
46 vcmpneq_osps, vcmpneqpd, vcmpneqps, vcmpneq_uspd, vcmpneq_usps,
47 vcmpngepd, vcmpngeps, vcmpnge_uqpd, vcmpnge_uqps, vcmpngtpd,
48 vcmpngtps, vcmpngt_uqpd, vcmpngt_uqps, vcmpnlepd, vcmpnleps,
49 vcmpnle_uqpd, vcmpnle_uqps, vcmpnltpd, vcmpnltps, vcmpnlt_uqpd,
50 vcmpnlt_uqps, vcmpordpd, vcmpordps, vcmpord_spd, vcmpord_sps,
51 vcmppd, vcmpps, vcmptruepd, vcmptrueps, vcmptrue_uspd,
52 vcmptrue_usps, vcmpunordpd, vcmpunordps, vcmpunord_spd,
53 vcmpunord_sps, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps, vcvtps2dq,
54 vcvttpd2dq, vcvttps2dq, vdivpd, vdivps, vdpps, vhaddpd, vhaddps,
55 vhsubpd, vhsubps, vlddqu, vmaskmovpd, vmaskmovps, vmaxpd,
56 vmaxps, vminpd, vminps, vmovapd, vmovaps, vmovdqa, vmovdqu,
57 vmovmskpd, vmovmskps, vmovntdq, vmovntpd, vmovntps, vmovshdup,
58 vmovsldup, vmovupd, vmovups, vmulpd, vmulps, vorpd, vorps,
59 vpermilpd, vpermilps, vptest, vrcpps, vroundpd, vroundps,
60 vrsqrtps, vshufpd, vshufps, vsqrtpd, vsqrtps, vsubpd, vsubps,
61 vtestpd, vtestps, vunpckhpd, vunpckhps, vunpcklpd, vunpcklps,
62 vxorpd, vxorps, vpblendd, vpbroadcastb, vpbroadcastd,
63 vpbroadcastw, vpbroadcastq, vpmaskmovd, vpmaskmovq, vpsllvd,
64 vpsllvq, vpsravd, vpsravq, vpsrlvd, vpsrlvq): Fold 128- and
65 256-bit forms. Use CheckRegSize instead of IgnoreSize where
66 appropriate. Drop Xmmword and Ymmword from the results where
68 * i386-tbl.h: Re-generate.
70 2017-12-18 Jan Beulich <jbeulich@suse.com>
72 * i386-gen.c (operand_type_shorthands): Add RegXMM, RegYMM, and
74 (opcode_modifiers): Drop FirstXmm0.
75 (operand_types): Replace RegXMM, RegYMM, and RegZMM with just
77 * i386-opc.h (enum of opcode modifiers): Drop FirstXmm0.
78 (struct i386_opcode_modifier): Drop firstxmm0.
79 (enum of operand types): Replace RegXMM, RegYMM, and RegZMM with
80 just RegSIMD. Extend comment.
81 (union i386_operand_type): Replace regxmm, regymm, and regzmm
83 * i386-opc.tbl (blendvpd, blendvps, pblendvb, sha256rnds2): Use
85 * i386-reg.tbl (xmm0): Add Acc.
86 * i386-init.h, i386-tbl.h: Re-generate.
88 2017-12-18 Jan Beulich <jbeulich@suse.com>
90 * i386-gen.c (operand_type_shorthands): Add FloatAcc and
92 (operand_types): Drop FloatAcc and FloatReg.
93 * i386-opc.h (enum of operand types): Likewise. Extend comment.
94 (union i386_operand_type): Drop floatacc and floatreg.
95 * i386-reg.tbl (st, st(0)): Replace FloatAcc by Acc.
96 * i386-init.h, i386-tbl.h: Re-generate.
98 2017-12-18 Jan Beulich <jbeulich@suse.com>
100 * i386-gen.c (operand_type_shorthands): New.
101 (opcode_modifiers): Replace Reg<N> with just Reg.
102 (set_bitfield_from_cpu_flag_init): Rename to
103 set_bitfield_from_shorthand. Drop value parameter. Process
104 operand_type_shorthands.
105 (set_bitfield): Adjust call accordingly.
106 * i386-opc.h (enum of operand types): Replace Reg<N> with just
108 (union i386_operand_type): Replace reg<N> with just reg.
109 * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
110 vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
111 separate register and memory forms.
112 * i386-reg.tbl (al): Drop Byte.
116 * i386-init.h, i386-tbl.h: Re-generate.
118 2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
120 * disassemble.c (disassemble_init_for_target): Don't put PRU
121 between powerpc and rs6000 cases.
123 2017-12-15 Jan Beulich <jbeulich@suse.com>
125 * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
126 movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
127 sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
128 stos, sub, test, xor): Drop CheckRegSize from variants not
129 allowing for two (or more) register operands.
130 * i386-tbl.h: Re-generate.
132 2017-12-13 Jim Wilson <jimw@sifive.com>
135 * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
137 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
139 * disassemble.c: Enable disassembler_needs_relocs for PRU.
141 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
142 Renlin Li <renlin.li@arm.com>
144 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
145 (get_sym_code_type): Here.
147 2017-12-03 Alan Modra <amodra@gmail.com>
149 * ppc-opc.c (extract_li20): Rewrite.
151 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
153 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
154 (operand_value_powerpc): Update return and argument type.
155 <value, top>: Update type.
156 (skip_optional_operands): Update argument type.
157 (lookup_powerpc): Likewise.
158 (lookup_vle): Likewise.
159 <table_opcd, table_mask, insn2>: Update type.
160 (lookup_spe2): Update argument type.
161 <table_opcd, table_mask, insn2>: Update type.
162 (print_insn_powerpc) <insn, value>: Update type.
163 Use PPC_INT_FMT for printing instructions and operands.
164 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
165 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
166 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
167 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
168 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
169 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
170 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
171 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
172 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
173 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
174 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
175 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
176 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
177 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
178 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
179 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
180 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
181 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
182 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
183 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
184 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
185 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
186 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
187 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
188 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
189 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
190 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
191 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
192 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
193 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
194 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
195 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
196 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
197 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
198 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
199 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
200 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
202 2017-11-29 Jan Beulich <jbeulich@suse.com>
204 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
206 (output_cpu_flags): Update active_cpu_flags.
207 (process_i386_opcode_modifier): Update active_isstring.
208 (output_operand_type): Rename "macro" parameter to "stage",
210 (process_i386_operand_type): Likewise. Track presence of
211 BaseIndex and emit DispN accordingly.
212 (output_i386_opcode, process_i386_registers,
213 process_i386_initializers): Adjust calls to
214 process_i386_operand_type() for its changed parameter type.
215 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
216 all insns operands having BaseIndex set.
217 * i386-tbl.h: Re-generate.
219 2017-11-29 Jan Beulich <jbeulich@suse.com>
221 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
223 (operand_types): Remove Vec_Disp8 entry.
224 * i386-opc.h (Vec_Disp8): Delete.
225 (union i386_operand_type): Remove vec_disp8.
226 (i386-opc.tbl): Remove Vec_Disp8.
227 * i386-init.h, i386-tbl.h: Re-generate.
229 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
231 * po/Make-in (datadir): Define as @datadir@.
232 (localedir): Define as @localedir@.
233 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
235 2017-11-27 Nick Clifton <nickc@redhat.com>
237 * po/zh_CN.po: Updated simplified Chinese translation.
239 2017-11-24 Jan Beulich <jbeulich@suse.com>
241 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
244 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
246 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
247 * i386-tbl.h: Regenerate.
249 2017-11-23 Jan Beulich <jbeulich@suse.com>
251 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
252 the 16-bit addressing case.
254 2017-11-23 Jan Beulich <jbeulich@suse.com>
256 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
257 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
258 * i386-opc.tbl (ud1, ud2b): Add operands.
260 * i386-tbl.h: Re-generate.
262 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
264 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
265 * i386-tbl.h: Regenerate.
267 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
269 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
270 * i386-tbl.h: Regenerate.
272 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
274 *arc-opc (insert_rhv2): Check h-regs range.
276 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
278 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
279 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
281 2017-11-16 Tamar Christina <tamar.christina@arm.com>
283 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
284 and AARCH64_FEATURE_F16.
286 2017-11-16 Tamar Christina <tamar.christina@arm.com>
288 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
289 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
290 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
291 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
292 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
293 (ldapur, ldapursw, stlur): New.
294 * aarch64-dis-2.c: Regenerate.
296 2017-11-16 Jan Beulich <jbeulich@suse.com>
298 (get_valid_dis386): Never flag bad opcode when
299 vex.register_specifier is beyond 7. Always store all four
300 bits of it. Move 16-/32-bit override in EVEX handling after
301 all to be overridden bits have been set.
302 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
303 Use rex to determine GPR register set.
304 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
305 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
307 2017-11-15 Jan Beulich <jbeulich@suse.com>
309 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
310 determine GPR register set.
312 2017-11-15 Jan Beulich <jbeulich@suse.com>
314 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
315 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
316 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
318 (OP_REG_VexI4): Drop low 4 bits check.
320 2017-11-15 Jan Beulich <jbeulich@suse.com>
322 * i386-reg.tbl (axl): Remove Acc and Byte.
323 * i386-tbl.h: Re-generate.
325 2017-11-14 Jan Beulich <jbeulich@suse.com>
327 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
328 (vex_len_table): Use VPCOM.
330 2017-11-14 Jan Beulich <jbeulich@suse.com>
332 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
333 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
334 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
336 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
337 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
338 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
339 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
341 * i386-tbl.h: Re-generate.
343 2017-11-14 Jan Beulich <jbeulich@suse.com>
345 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
346 smov, ssca, stos, ssto, xlat): Drop Disp*.
347 * i386-tbl.h: Re-generate.
349 2017-11-13 Jan Beulich <jbeulich@suse.com>
351 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
352 xsaveopt64): Add No_qSuf.
353 * i386-tbl.h: Re-generate.
355 2017-11-09 Tamar Christina <tamar.christina@arm.com>
357 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
358 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
359 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
360 sder32_el2, vncr_el2.
361 (aarch64_sys_reg_supported_p): Likewise.
362 (aarch64_pstatefields): Add dit register.
363 (aarch64_pstatefield_supported_p): Likewise.
364 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
365 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
366 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
367 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
368 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
369 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
370 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
372 2017-11-09 Tamar Christina <tamar.christina@arm.com>
374 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
375 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
376 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
377 (QL_STLW, QL_STLX): New.
379 2017-11-09 Tamar Christina <tamar.christina@arm.com>
381 * aarch64-asm.h (ins_addr_offset): New.
382 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
383 (aarch64_ins_addr_offset): New.
384 * aarch64-asm-2.c: Regenerate.
385 * aarch64-dis.h (ext_addr_offset): New.
386 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
387 (aarch64_ext_addr_offset): New.
388 * aarch64-dis-2.c: Regenerate.
389 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
390 FLD_imm4_2 and FLD_SM3_imm2.
391 * aarch64-opc.c (fields): Add FLD_imm6_2,
392 FLD_imm4_2 and FLD_SM3_imm2.
393 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
394 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
395 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
396 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
398 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
400 2017-11-09 Tamar Christina <tamar.christina@arm.com>
403 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
404 (aarch64_feature_sm4, aarch64_feature_sha3): New.
405 (aarch64_feature_fp_16_v8_2): New.
406 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
407 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
408 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
410 2017-11-08 Tamar Christina <tamar.christina@arm.com>
412 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
413 (aarch64_feature_sha2, aarch64_feature_aes): New.
415 (AES_INSN, SHA2_INSN): New.
416 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
417 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
418 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
421 2017-11-08 Jiong Wang <jiong.wang@arm.com>
422 Tamar Christina <tamar.christina@arm.com>
424 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
425 FP16 instructions, including vfmal.f16 and vfmsl.f16.
427 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
429 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
431 2017-11-07 Alan Modra <amodra@gmail.com>
433 * opintl.h: Formatting, comment fixes.
434 (gettext, ngettext): Redefine when ENABLE_NLS.
435 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
436 (_): Define using gettext.
437 (textdomain, bindtextdomain): Use safer "do nothing".
439 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
441 * arc-dis.c (print_hex): New variable.
442 (parse_option): Check for hex option.
443 (print_insn_arc): Use hexadecimal representation for short
444 immediate values when requested.
445 (print_arc_disassembler_options): Add hex option to the list.
447 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
449 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
450 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
451 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
452 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
453 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
454 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
455 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
456 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
457 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
458 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
459 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
460 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
461 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
462 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
463 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
464 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
465 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
466 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
467 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
469 (prealloc, prefetch*): Place them before ld instruction.
470 * arc-opc.c (skip_this_opcode): Add ARITH class.
472 2017-10-25 Alan Modra <amodra@gmail.com>
475 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
476 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
477 (imm4flag, size_changed): Likewise.
478 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
479 (words, allWords, processing_argument_number): Likewise.
480 (cst4flag, size_changed): Likewise.
481 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
482 (crx_cst4_maps): Rename from cst4_maps.
483 (crx_no_op_insn): Rename from no_op_insn.
485 2017-10-24 Andrew Waterman <andrew@sifive.com>
487 * riscv-opc.c (match_c_addi16sp) : New function.
488 (match_c_addi4spn): New function.
489 (match_c_lui): Don't allow 0-immediate encodings.
490 (riscv_opcodes) <addi>: Use the above functions.
492 <c.addi4spn>: Likewise.
493 <c.addi16sp>: Likewise.
495 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
497 * i386-init.h: Regenerate
498 * i386-tbl.h: Likewise
500 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
502 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
503 (enum): Add EVEX_W_0F3854_P_2.
504 * i386-dis-evex.h (evex_table): Updated.
505 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
506 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
507 (cpu_flags): Add CpuAVX512_BITALG.
508 * i386-opc.h (enum): Add CpuAVX512_BITALG.
509 (i386_cpu_flags): Add cpuavx512_bitalg..
510 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
511 * i386-init.h: Regenerate.
512 * i386-tbl.h: Likewise.
514 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
516 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
517 * i386-dis-evex.h (evex_table): Updated.
518 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
519 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
520 (cpu_flags): Add CpuAVX512_VNNI.
521 * i386-opc.h (enum): Add CpuAVX512_VNNI.
522 (i386_cpu_flags): Add cpuavx512_vnni.
523 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
524 * i386-init.h: Regenerate.
525 * i386-tbl.h: Likewise.
527 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
529 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
530 (enum): Remove VEX_LEN_0F3A44_P_2.
531 (vex_len_table): Ditto.
532 (enum): Remove VEX_W_0F3A44_P_2.
533 (vew_w_table): Ditto.
534 (prefix_table): Adjust instructions (see prefixes above).
535 * i386-dis-evex.h (evex_table):
536 Add new instructions (see prefixes above).
537 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
538 (bitfield_cpu_flags): Ditto.
539 * i386-opc.h (enum): Ditto.
540 (i386_cpu_flags): Ditto.
541 (CpuUnused): Comment out to avoid zero-width field problem.
542 * i386-opc.tbl (vpclmulqdq): New instruction.
543 * i386-init.h: Regenerate.
546 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
548 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
549 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
550 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
551 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
552 (vex_len_table): Ditto.
553 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
554 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
555 (vew_w_table): Ditto.
556 (prefix_table): Adjust instructions (see prefixes above).
557 * i386-dis-evex.h (evex_table):
558 Add new instructions (see prefixes above).
559 * i386-gen.c (cpu_flag_init): Add VAES.
560 (bitfield_cpu_flags): Ditto.
561 * i386-opc.h (enum): Ditto.
562 (i386_cpu_flags): Ditto.
563 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
564 * i386-init.h: Regenerate.
567 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
569 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
570 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
571 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
572 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
573 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
574 (prefix_table): Updated (see prefixes above).
575 (three_byte_table): Likewise.
576 (vex_w_table): Likewise.
577 * i386-dis-evex.h: Likewise.
578 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
579 (cpu_flags): Add CpuGFNI.
580 * i386-opc.h (enum): Add CpuGFNI.
581 (i386_cpu_flags): Add cpugfni.
582 * i386-opc.tbl: Add Intel GFNI instructions.
583 * i386-init.h: Regenerate.
584 * i386-tbl.h: Likewise.
586 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
588 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
589 Define EXbScalar and EXwScalar for OP_EX.
590 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
591 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
592 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
593 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
594 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
595 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
596 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
597 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
598 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
599 (OP_E_memory): Likewise.
600 * i386-dis-evex.h: Updated.
601 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
602 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
603 (cpu_flags): Add CpuAVX512_VBMI2.
604 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
605 (i386_cpu_flags): Add cpuavx512_vbmi2.
606 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
607 * i386-init.h: Regenerate.
608 * i386-tbl.h: Likewise.
610 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
612 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
614 2017-10-12 James Bowman <james.bowman@ftdichip.com>
616 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
617 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
618 K15. Add jmpix pattern.
620 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
622 * s390-opc.txt (prno, tpei, irbm): New instructions added.
624 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
626 * s390-opc.c (INSTR_SI_RD): New macro.
627 (INSTR_S_RD): Adjust example instruction.
628 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
631 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
633 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
634 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
635 VLE multimple load/store instructions. Old e_ldm* variants are
637 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
639 2017-09-27 Nick Clifton <nickc@redhat.com>
642 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
643 names for the fmv.x.s and fmv.s.x instructions respectively.
645 2017-09-26 do <do@nerilex.org>
648 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
649 be used on CPUs that have emacs support.
651 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
653 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
655 2017-09-09 Kamil Rytarowski <n54@gmx.com>
657 * nds32-asm.c: Rename __BIT() to N32_BIT().
658 * nds32-asm.h: Likewise.
659 * nds32-dis.c: Likewise.
661 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
663 * i386-dis.c (last_active_prefix): Removed.
664 (ckprefix): Don't set last_active_prefix.
665 (NOTRACK_Fixup): Don't check last_active_prefix.
667 2017-08-31 Nick Clifton <nickc@redhat.com>
669 * po/fr.po: Updated French translation.
671 2017-08-31 James Bowman <james.bowman@ftdichip.com>
673 * ft32-dis.c (print_insn_ft32): Correct display of non-address
676 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
677 Edmar Wienskoski <edmar.wienskoski@nxp.com>
679 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
680 PPC_OPCODE_EFS2 flag to "e200z4" entry.
681 New entries efs2 and spe2.
682 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
683 (SPE2_OPCD_SEGS): New macro.
684 (spe2_opcd_indices): New.
685 (disassemble_init_powerpc): Handle SPE2 opcodes.
686 (lookup_spe2): New function.
687 (print_insn_powerpc): call lookup_spe2.
688 * ppc-opc.c (insert_evuimm1_ex0): New function.
689 (extract_evuimm1_ex0): Likewise.
690 (insert_evuimm_lt8): Likewise.
691 (extract_evuimm_lt8): Likewise.
692 (insert_off_spe2): Likewise.
693 (extract_off_spe2): Likewise.
694 (insert_Ddd): Likewise.
695 (extract_Ddd): Likewise.
697 (EVUIMM_LT8): Likewise.
698 (EVUIMM_LT16): Adjust.
700 (EVUIMM_1): Likewise.
701 (EVUIMM_1_EX0): Likewise.
704 (VX_OFF_SPE2): Likewise.
707 (VX_MASK_DDD): New mask.
709 (VX_RA_CONST): New macro.
710 (VX_RA_CONST_MASK): Likewise.
711 (VX_RB_CONST): Likewise.
712 (VX_RB_CONST_MASK): Likewise.
713 (VX_OFF_SPE2_MASK): Likewise.
714 (VX_SPE_CRFD): Likewise.
715 (VX_SPE_CRFD_MASK VX): Likewise.
716 (VX_SPE2_CLR): Likewise.
717 (VX_SPE2_CLR_MASK): Likewise.
718 (VX_SPE2_SPLATB): Likewise.
719 (VX_SPE2_SPLATB_MASK): Likewise.
720 (VX_SPE2_OCTET): Likewise.
721 (VX_SPE2_OCTET_MASK): Likewise.
722 (VX_SPE2_DDHH): Likewise.
723 (VX_SPE2_DDHH_MASK): Likewise.
724 (VX_SPE2_HH): Likewise.
725 (VX_SPE2_HH_MASK): Likewise.
726 (VX_SPE2_EVMAR): Likewise.
727 (VX_SPE2_EVMAR_MASK): Likewise.
730 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
731 (powerpc_macros): Map old SPE instructions have new names
732 with the same opcodes. Add SPE2 instructions which just are
734 (spe2_opcodes): Add SPE2 opcodes.
736 2017-08-23 Alan Modra <amodra@gmail.com>
738 * ppc-opc.c: Formatting and comment fixes. Move insert and
739 extract functions earlier, deleting forward declarations.
740 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
743 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
745 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
747 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
748 Edmar Wienskoski <edmar.wienskoski@nxp.com>
750 * ppc-opc.c (insert_evuimm2_ex0): New function.
751 (extract_evuimm2_ex0): Likewise.
752 (insert_evuimm4_ex0): Likewise.
753 (extract_evuimm4_ex0): Likewise.
754 (insert_evuimm8_ex0): Likewise.
755 (extract_evuimm8_ex0): Likewise.
756 (insert_evuimm_lt16): Likewise.
757 (extract_evuimm_lt16): Likewise.
758 (insert_rD_rS_even): Likewise.
759 (extract_rD_rS_even): Likewise.
760 (insert_off_lsp): Likewise.
761 (extract_off_lsp): Likewise.
762 (RD_EVEN): New operand.
765 (EVUIMM_LT16): New operand.
767 (EVUIMM_2_EX0): New operand.
769 (EVUIMM_4_EX0): New operand.
771 (EVUIMM_8_EX0): New operand.
773 (VX_OFF): New operand.
775 (VX_LSP_MASK): Likewise.
776 (VX_LSP_OFF_MASK): Likewise.
777 (PPC_OPCODE_LSP): Likewise.
778 (vle_opcodes): Add LSP opcodes.
779 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
781 2017-08-09 Jiong Wang <jiong.wang@arm.com>
783 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
784 register operands in CRC instructions.
785 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
788 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
790 * disassemble.c (disassembler): Mark big and mach with
793 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
795 * disassemble.c (disassembler): Remove arch/mach/endian
798 2017-07-25 Nick Clifton <nickc@redhat.com>
801 * arc-opc.c (insert_rhv2): Use lower case first letter in error
803 (insert_r0): Likewise.
804 (insert_r1): Likewise.
805 (insert_r2): Likewise.
806 (insert_r3): Likewise.
807 (insert_sp): Likewise.
808 (insert_gp): Likewise.
809 (insert_pcl): Likewise.
810 (insert_blink): Likewise.
811 (insert_ilink1): Likewise.
812 (insert_ilink2): Likewise.
813 (insert_ras): Likewise.
814 (insert_rbs): Likewise.
815 (insert_rcs): Likewise.
816 (insert_simm3s): Likewise.
817 (insert_rrange): Likewise.
818 (insert_r13el): Likewise.
819 (insert_fpel): Likewise.
820 (insert_blinkel): Likewise.
821 (insert_pclel): Likewise.
822 (insert_nps_bitop_size_2b): Likewise.
823 (insert_nps_imm_offset): Likewise.
824 (insert_nps_imm_entry): Likewise.
825 (insert_nps_size_16bit): Likewise.
826 (insert_nps_##NAME##_pos): Likewise.
827 (insert_nps_##NAME): Likewise.
828 (insert_nps_bitop_ins_ext): Likewise.
829 (insert_nps_##NAME): Likewise.
830 (insert_nps_min_hofs): Likewise.
831 (insert_nps_##NAME): Likewise.
832 (insert_nps_rbdouble_64): Likewise.
833 (insert_nps_misc_imm_offset): Likewise.
834 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
837 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
838 Jiong Wang <jiong.wang@arm.com>
840 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
842 * aarch64-dis-2.c: Regenerated.
844 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
846 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
849 2017-07-20 Nick Clifton <nickc@redhat.com>
851 * po/de.po: Updated German translation.
853 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
855 * arc-regs.h (sec_stat): New aux register.
856 (aux_kernel_sp): Likewise.
857 (aux_sec_u_sp): Likewise.
858 (aux_sec_k_sp): Likewise.
859 (sec_vecbase_build): Likewise.
860 (nsc_table_top): Likewise.
861 (nsc_table_base): Likewise.
862 (ersec_stat): Likewise.
863 (aux_sec_except): Likewise.
865 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
867 * arc-opc.c (extract_uimm12_20): New function.
868 (UIMM12_20): New operand.
870 * arc-tbl.h (sjli): Add new instruction.
872 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
873 John Eric Martin <John.Martin@emmicro-us.com>
875 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
876 (UIMM3_23): Adjust accordingly.
877 * arc-regs.h: Add/correct jli_base register.
878 * arc-tbl.h (jli_s): Likewise.
880 2017-07-18 Nick Clifton <nickc@redhat.com>
883 * aarch64-opc.c: Fix spelling typos.
884 * i386-dis.c: Likewise.
886 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
888 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
889 max_addr_offset and octets variables to size_t.
891 2017-07-12 Alan Modra <amodra@gmail.com>
893 * po/da.po: Update from translationproject.org/latest/opcodes/.
894 * po/de.po: Likewise.
895 * po/es.po: Likewise.
896 * po/fi.po: Likewise.
897 * po/fr.po: Likewise.
898 * po/id.po: Likewise.
899 * po/it.po: Likewise.
900 * po/nl.po: Likewise.
901 * po/pt_BR.po: Likewise.
902 * po/ro.po: Likewise.
903 * po/sv.po: Likewise.
904 * po/tr.po: Likewise.
905 * po/uk.po: Likewise.
906 * po/vi.po: Likewise.
907 * po/zh_CN.po: Likewise.
909 2017-07-11 Yao Qi <yao.qi@linaro.org>
910 Alan Modra <amodra@gmail.com>
912 * cgen.sh: Mark generated files read-only.
913 * epiphany-asm.c: Regenerate.
914 * epiphany-desc.c: Regenerate.
915 * epiphany-desc.h: Regenerate.
916 * epiphany-dis.c: Regenerate.
917 * epiphany-ibld.c: Regenerate.
918 * epiphany-opc.c: Regenerate.
919 * epiphany-opc.h: Regenerate.
920 * fr30-asm.c: Regenerate.
921 * fr30-desc.c: Regenerate.
922 * fr30-desc.h: Regenerate.
923 * fr30-dis.c: Regenerate.
924 * fr30-ibld.c: Regenerate.
925 * fr30-opc.c: Regenerate.
926 * fr30-opc.h: Regenerate.
927 * frv-asm.c: Regenerate.
928 * frv-desc.c: Regenerate.
929 * frv-desc.h: Regenerate.
930 * frv-dis.c: Regenerate.
931 * frv-ibld.c: Regenerate.
932 * frv-opc.c: Regenerate.
933 * frv-opc.h: Regenerate.
934 * ip2k-asm.c: Regenerate.
935 * ip2k-desc.c: Regenerate.
936 * ip2k-desc.h: Regenerate.
937 * ip2k-dis.c: Regenerate.
938 * ip2k-ibld.c: Regenerate.
939 * ip2k-opc.c: Regenerate.
940 * ip2k-opc.h: Regenerate.
941 * iq2000-asm.c: Regenerate.
942 * iq2000-desc.c: Regenerate.
943 * iq2000-desc.h: Regenerate.
944 * iq2000-dis.c: Regenerate.
945 * iq2000-ibld.c: Regenerate.
946 * iq2000-opc.c: Regenerate.
947 * iq2000-opc.h: Regenerate.
948 * lm32-asm.c: Regenerate.
949 * lm32-desc.c: Regenerate.
950 * lm32-desc.h: Regenerate.
951 * lm32-dis.c: Regenerate.
952 * lm32-ibld.c: Regenerate.
953 * lm32-opc.c: Regenerate.
954 * lm32-opc.h: Regenerate.
955 * lm32-opinst.c: Regenerate.
956 * m32c-asm.c: Regenerate.
957 * m32c-desc.c: Regenerate.
958 * m32c-desc.h: Regenerate.
959 * m32c-dis.c: Regenerate.
960 * m32c-ibld.c: Regenerate.
961 * m32c-opc.c: Regenerate.
962 * m32c-opc.h: Regenerate.
963 * m32r-asm.c: Regenerate.
964 * m32r-desc.c: Regenerate.
965 * m32r-desc.h: Regenerate.
966 * m32r-dis.c: Regenerate.
967 * m32r-ibld.c: Regenerate.
968 * m32r-opc.c: Regenerate.
969 * m32r-opc.h: Regenerate.
970 * m32r-opinst.c: Regenerate.
971 * mep-asm.c: Regenerate.
972 * mep-desc.c: Regenerate.
973 * mep-desc.h: Regenerate.
974 * mep-dis.c: Regenerate.
975 * mep-ibld.c: Regenerate.
976 * mep-opc.c: Regenerate.
977 * mep-opc.h: Regenerate.
978 * mt-asm.c: Regenerate.
979 * mt-desc.c: Regenerate.
980 * mt-desc.h: Regenerate.
981 * mt-dis.c: Regenerate.
982 * mt-ibld.c: Regenerate.
983 * mt-opc.c: Regenerate.
984 * mt-opc.h: Regenerate.
985 * or1k-asm.c: Regenerate.
986 * or1k-desc.c: Regenerate.
987 * or1k-desc.h: Regenerate.
988 * or1k-dis.c: Regenerate.
989 * or1k-ibld.c: Regenerate.
990 * or1k-opc.c: Regenerate.
991 * or1k-opc.h: Regenerate.
992 * or1k-opinst.c: Regenerate.
993 * xc16x-asm.c: Regenerate.
994 * xc16x-desc.c: Regenerate.
995 * xc16x-desc.h: Regenerate.
996 * xc16x-dis.c: Regenerate.
997 * xc16x-ibld.c: Regenerate.
998 * xc16x-opc.c: Regenerate.
999 * xc16x-opc.h: Regenerate.
1000 * xstormy16-asm.c: Regenerate.
1001 * xstormy16-desc.c: Regenerate.
1002 * xstormy16-desc.h: Regenerate.
1003 * xstormy16-dis.c: Regenerate.
1004 * xstormy16-ibld.c: Regenerate.
1005 * xstormy16-opc.c: Regenerate.
1006 * xstormy16-opc.h: Regenerate.
1008 2017-07-07 Alan Modra <amodra@gmail.com>
1010 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
1011 * m32c-dis.c: Regenerate.
1012 * mep-dis.c: Regenerate.
1014 2017-07-05 Borislav Petkov <bp@suse.de>
1016 * i386-dis.c: Enable ModRM.reg /6 aliases.
1018 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1020 * opcodes/arm-dis.c: Support MVFR2 in disassembly
1023 2017-07-04 Tristan Gingold <gingold@adacore.com>
1025 * configure: Regenerate.
1027 2017-07-03 Tristan Gingold <gingold@adacore.com>
1029 * po/opcodes.pot: Regenerate.
1031 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
1033 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
1034 entries to the MSA ASE instruction block.
1036 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
1037 Maciej W. Rozycki <macro@imgtec.com>
1039 * micromips-opc.c (XPA, XPAVZ): New macros.
1040 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
1043 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
1044 Maciej W. Rozycki <macro@imgtec.com>
1046 * micromips-opc.c (I36): New macro.
1047 (micromips_opcodes): Add "eretnc".
1049 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
1050 Andrew Bennett <andrew.bennett@imgtec.com>
1052 * mips-dis.c (mips_calculate_combination_ases): Handle the
1054 (parse_mips_ase_option): New function.
1055 (parse_mips_dis_option): Factor out ASE option handling to the
1056 new function. Call `mips_calculate_combination_ases'.
1057 * mips-opc.c (XPAVZ): New macro.
1058 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
1059 "mfhgc0", "mthc0" and "mthgc0".
1061 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
1063 * mips-dis.c (mips_calculate_combination_ases): New function.
1064 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
1065 calculation to the new function.
1066 (set_default_mips_dis_options): Call the new function.
1068 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1070 * arc-dis.c (parse_disassembler_options): Use
1071 FOR_EACH_DISASSEMBLER_OPTION.
1073 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1075 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
1076 disassembler option strings.
1077 (parse_cpu_option): Likewise.
1079 2017-06-28 Tamar Christina <tamar.christina@arm.com>
1081 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
1082 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
1083 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
1084 (aarch64_feature_dotprod, DOT_INSN): New.
1086 * aarch64-dis-2.c: Regenerated.
1088 2017-06-28 Jiong Wang <jiong.wang@arm.com>
1090 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
1092 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
1093 Matthew Fortune <matthew.fortune@imgtec.com>
1094 Andrew Bennett <andrew.bennett@imgtec.com>
1096 * mips-formats.h (INT_BIAS): New macro.
1097 (INT_ADJ): Redefine in INT_BIAS terms.
1098 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
1099 (mips_print_save_restore): New function.
1100 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
1101 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
1103 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
1104 (print_mips16_insn_arg): Call `mips_print_save_restore' for
1105 OP_SAVE_RESTORE_LIST handling, factored out from here.
1106 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
1107 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
1108 (mips_builtin_opcodes): Add "restore" and "save" entries.
1109 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
1111 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
1113 2017-06-23 Andrew Waterman <andrew@sifive.com>
1115 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
1116 alias; do not mark SLTI instruction as an alias.
1118 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1120 * i386-dis.c (RM_0FAE_REG_5): Removed.
1121 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1122 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1123 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1124 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
1125 PREFIX_MOD_3_0F01_REG_5_RM_0.
1126 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
1127 PREFIX_MOD_3_0FAE_REG_5.
1128 (mod_table): Update MOD_0FAE_REG_5.
1129 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
1130 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1131 * i386-tbl.h: Regenerated.
1133 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1135 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1136 * i386-opc.tbl: Likewise.
1137 * i386-tbl.h: Regenerated.
1139 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1141 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1143 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1146 2017-06-19 Nick Clifton <nickc@redhat.com>
1149 * score-dis.c (score_opcodes): Add sentinel.
1151 2017-06-16 Alan Modra <amodra@gmail.com>
1153 * rx-decode.c: Regenerate.
1155 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1158 * i386-dis.c (OP_E_register): Check valid bnd register.
1161 2017-06-15 Nick Clifton <nickc@redhat.com>
1164 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1167 2017-06-15 Nick Clifton <nickc@redhat.com>
1170 * rl78-decode.opc (OP_BUF_LEN): Define.
1171 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1172 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1174 * rl78-decode.c: Regenerate.
1176 2017-06-15 Nick Clifton <nickc@redhat.com>
1179 * bfin-dis.c (gregs): Clip index to prevent overflow.
1181 (regs_lo): Likewise.
1182 (regs_hi): Likewise.
1184 2017-06-14 Nick Clifton <nickc@redhat.com>
1187 * score7-dis.c (score_opcodes): Add sentinel.
1189 2017-06-14 Yao Qi <yao.qi@linaro.org>
1191 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1192 * arm-dis.c: Likewise.
1193 * ia64-dis.c: Likewise.
1194 * mips-dis.c: Likewise.
1195 * spu-dis.c: Likewise.
1196 * disassemble.h (print_insn_aarch64): New declaration, moved from
1198 (print_insn_big_arm, print_insn_big_mips): Likewise.
1199 (print_insn_i386, print_insn_ia64): Likewise.
1200 (print_insn_little_arm, print_insn_little_mips): Likewise.
1202 2017-06-14 Nick Clifton <nickc@redhat.com>
1205 * rx-decode.opc: Include libiberty.h
1206 (GET_SCALE): New macro - validates access to SCALE array.
1207 (GET_PSCALE): New macro - validates access to PSCALE array.
1208 (DIs, SIs, S2Is, rx_disp): Use new macros.
1209 * rx-decode.c: Regenerate.
1211 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1213 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1215 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1217 * arc-dis.c (enforced_isa_mask): Declare.
1218 (cpu_types): Likewise.
1219 (parse_cpu_option): New function.
1220 (parse_disassembler_options): Use it.
1221 (print_insn_arc): Use enforced_isa_mask.
1222 (print_arc_disassembler_options): Document new options.
1224 2017-05-24 Yao Qi <yao.qi@linaro.org>
1226 * alpha-dis.c: Include disassemble.h, don't include
1228 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1229 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1230 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1231 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1232 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1233 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1234 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1235 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1236 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1237 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1238 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1239 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1240 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1241 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1242 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1243 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1244 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1245 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1246 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1247 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1248 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1249 * z80-dis.c, z8k-dis.c: Likewise.
1250 * disassemble.h: New file.
1252 2017-05-24 Yao Qi <yao.qi@linaro.org>
1254 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1255 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1257 2017-05-24 Yao Qi <yao.qi@linaro.org>
1259 * disassemble.c (disassembler): Add arguments a, big and mach.
1262 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1264 * i386-dis.c (NOTRACK_Fixup): New.
1265 (NOTRACK): Likewise.
1266 (NOTRACK_PREFIX): Likewise.
1267 (last_active_prefix): Likewise.
1268 (reg_table): Use NOTRACK on indirect call and jmp.
1269 (ckprefix): Set last_active_prefix.
1270 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1271 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1272 * i386-opc.h (NoTrackPrefixOk): New.
1273 (i386_opcode_modifier): Add notrackprefixok.
1274 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1276 * i386-tbl.h: Regenerated.
1278 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1280 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1282 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1283 bfd_mach_sparc_v9m8.
1284 (print_insn_sparc): Handle new operand types.
1285 * sparc-opc.c (MASK_M8): Define.
1287 (v6notlet): Likewise.
1298 (v9andleon): Likewise.
1301 (HWS2_VM8): Likewise.
1302 (sparc_opcode_archs): Add entry for "m8".
1303 (sparc_opcodes): Add OSA2017 and M8 instructions
1304 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1306 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1307 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1308 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1309 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1310 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1311 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1312 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1313 ASI_CORE_SELECT_COMMIT_NHT.
1315 2017-05-18 Alan Modra <amodra@gmail.com>
1317 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1318 * aarch64-dis.c: Likewise.
1319 * aarch64-gen.c: Likewise.
1320 * aarch64-opc.c: Likewise.
1322 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1323 Matthew Fortune <matthew.fortune@imgtec.com>
1325 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1326 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1327 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1328 (print_insn_arg) <OP_REG28>: Add handler.
1329 (validate_insn_args) <OP_REG28>: Handle.
1330 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1331 32-bit encoding and 9-bit immediates.
1332 (print_insn_mips16): Handle MIPS16 instructions that require
1333 32-bit encoding and MFC0/MTC0 operand decoding.
1334 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1335 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1336 (RD_C0, WR_C0, E2, E2MT): New macros.
1337 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1338 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1339 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1340 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1341 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1342 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1343 instructions, "swl", "swr", "sync" and its "sync_acquire",
1344 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1345 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1346 regular/extended entries for original MIPS16 ISA revision
1347 instructions whose extended forms are subdecoded in the MIPS16e2
1348 ISA revision: "li", "sll" and "srl".
1350 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1352 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1353 reference in CP0 move operand decoding.
1355 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1357 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1358 type to hexadecimal.
1359 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1361 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1363 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1364 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1365 "sync_rmb" and "sync_wmb" as aliases.
1366 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1367 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1369 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1371 * arc-dis.c (parse_option): Update quarkse_em option..
1372 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1374 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1376 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1378 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1380 2017-05-01 Michael Clark <michaeljclark@mac.com>
1382 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1385 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1387 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1388 and branches and not synthetic data instructions.
1390 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1392 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1394 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1396 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1397 * arc-opc.c (insert_r13el): New function.
1399 * arc-tbl.h: Add new enter/leave variants.
1401 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1403 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1405 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1407 * mips-dis.c (print_mips_disassembler_options): Add
1410 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1412 * mips16-opc.c (AL): New macro.
1413 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1414 of "ld" and "lw" as aliases.
1416 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1418 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1421 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1422 Alan Modra <amodra@gmail.com>
1424 * ppc-opc.c (ELEV): Define.
1425 (vle_opcodes): Add se_rfgi and e_sc.
1426 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1429 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1431 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1433 2017-04-21 Nick Clifton <nickc@redhat.com>
1436 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1439 2017-04-13 Alan Modra <amodra@gmail.com>
1441 * epiphany-desc.c: Regenerate.
1442 * fr30-desc.c: Regenerate.
1443 * frv-desc.c: Regenerate.
1444 * ip2k-desc.c: Regenerate.
1445 * iq2000-desc.c: Regenerate.
1446 * lm32-desc.c: Regenerate.
1447 * m32c-desc.c: Regenerate.
1448 * m32r-desc.c: Regenerate.
1449 * mep-desc.c: Regenerate.
1450 * mt-desc.c: Regenerate.
1451 * or1k-desc.c: Regenerate.
1452 * xc16x-desc.c: Regenerate.
1453 * xstormy16-desc.c: Regenerate.
1455 2017-04-11 Alan Modra <amodra@gmail.com>
1457 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1458 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1459 PPC_OPCODE_TMR for e6500.
1460 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1461 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1462 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1463 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1464 (PPCHTM): Define as PPC_OPCODE_POWER8.
1465 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1467 2017-04-10 Alan Modra <amodra@gmail.com>
1469 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1470 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1471 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1472 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1474 2017-04-09 Pip Cet <pipcet@gmail.com>
1476 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1477 appropriate floating-point precision directly.
1479 2017-04-07 Alan Modra <amodra@gmail.com>
1481 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1482 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1483 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1484 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1485 vector instructions with E6500 not PPCVEC2.
1487 2017-04-06 Pip Cet <pipcet@gmail.com>
1489 * Makefile.am: Add wasm32-dis.c.
1490 * configure.ac: Add wasm32-dis.c to wasm32 target.
1491 * disassemble.c: Add wasm32 disassembler code.
1492 * wasm32-dis.c: New file.
1493 * Makefile.in: Regenerate.
1494 * configure: Regenerate.
1495 * po/POTFILES.in: Regenerate.
1496 * po/opcodes.pot: Regenerate.
1498 2017-04-05 Pedro Alves <palves@redhat.com>
1500 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1501 * arm-dis.c (parse_arm_disassembler_options): Constify.
1502 * ppc-dis.c (powerpc_init_dialect): Constify local.
1503 * vax-dis.c (parse_disassembler_options): Constify.
1505 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1507 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1510 2017-03-30 Pip Cet <pipcet@gmail.com>
1512 * configure.ac: Add (empty) bfd_wasm32_arch target.
1513 * configure: Regenerate
1514 * po/opcodes.pot: Regenerate.
1516 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1518 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1520 * opcodes/sparc-opc.c (asi_table): New ASIs.
1522 2017-03-29 Alan Modra <amodra@gmail.com>
1524 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1526 (lookup_powerpc): Don't special case -1 dialect. Handle
1528 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1529 lookup_powerpc call, pass it on second.
1531 2017-03-27 Alan Modra <amodra@gmail.com>
1534 * ppc-dis.c (struct ppc_mopt): Comment.
1535 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1537 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1539 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1540 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1541 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1542 (insert_nps_misc_imm_offset): New function.
1543 (extract_nps_misc imm_offset): New function.
1544 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1545 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1547 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1549 * s390-mkopc.c (main): Remove vx2 check.
1550 * s390-opc.txt: Remove vx2 instruction flags.
1552 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1554 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1555 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1556 (insert_nps_imm_offset): New function.
1557 (extract_nps_imm_offset): New function.
1558 (insert_nps_imm_entry): New function.
1559 (extract_nps_imm_entry): New function.
1561 2017-03-17 Alan Modra <amodra@gmail.com>
1564 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1565 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1566 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1568 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1570 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1574 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1576 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1578 2017-03-13 Andrew Waterman <andrew@sifive.com>
1580 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1585 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1587 * i386-gen.c (opcode_modifiers): Replace S with Load.
1588 * i386-opc.h (S): Removed.
1590 (i386_opcode_modifier): Replace s with load.
1591 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1592 and {evex}. Replace S with Load.
1593 * i386-tbl.h: Regenerated.
1595 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1597 * i386-opc.tbl: Use CpuCET on rdsspq.
1598 * i386-tbl.h: Regenerated.
1600 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1602 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1603 <vsx>: Do not use PPC_OPCODE_VSX3;
1605 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1607 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1609 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1611 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1612 (MOD_0F1E_PREFIX_1): Likewise.
1613 (MOD_0F38F5_PREFIX_2): Likewise.
1614 (MOD_0F38F6_PREFIX_0): Likewise.
1615 (RM_0F1E_MOD_3_REG_7): Likewise.
1616 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1617 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1618 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1619 (PREFIX_0F1E): Likewise.
1620 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1621 (PREFIX_0F38F5): Likewise.
1622 (dis386_twobyte): Use PREFIX_0F1E.
1623 (reg_table): Add REG_0F1E_MOD_3.
1624 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1625 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1626 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1627 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1628 (three_byte_table): Use PREFIX_0F38F5.
1629 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1630 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1631 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1632 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1633 PREFIX_MOD_3_0F01_REG_5_RM_2.
1634 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1635 (cpu_flags): Add CpuCET.
1636 * i386-opc.h (CpuCET): New enum.
1637 (CpuUnused): Commented out.
1638 (i386_cpu_flags): Add cpucet.
1639 * i386-opc.tbl: Add Intel CET instructions.
1640 * i386-init.h: Regenerated.
1641 * i386-tbl.h: Likewise.
1643 2017-03-06 Alan Modra <amodra@gmail.com>
1646 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1647 (extract_raq, extract_ras, extract_rbx): New functions.
1648 (powerpc_operands): Use opposite corresponding insert function.
1650 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1651 register restriction.
1653 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1655 * disassemble.c Include "safe-ctype.h".
1656 (disassemble_init_for_target): Handle s390 init.
1657 (remove_whitespace_and_extra_commas): New function.
1658 (disassembler_options_cmp): Likewise.
1659 * arm-dis.c: Include "libiberty.h".
1661 (regnames): Use long disassembler style names.
1662 Add force-thumb and no-force-thumb options.
1663 (NUM_ARM_REGNAMES): Rename from this...
1664 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1665 (get_arm_regname_num_options): Delete.
1666 (set_arm_regname_option): Likewise.
1667 (get_arm_regnames): Likewise.
1668 (parse_disassembler_options): Likewise.
1669 (parse_arm_disassembler_option): Rename from this...
1670 (parse_arm_disassembler_options): ...to this. Make static.
1671 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1672 (print_insn): Use parse_arm_disassembler_options.
1673 (disassembler_options_arm): New function.
1674 (print_arm_disassembler_options): Handle updated regnames.
1675 * ppc-dis.c: Include "libiberty.h".
1676 (ppc_opts): Add "32" and "64" entries.
1677 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1678 (powerpc_init_dialect): Add break to switch statement.
1679 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1680 (disassembler_options_powerpc): New function.
1681 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1682 Remove printing of "32" and "64".
1683 * s390-dis.c: Include "libiberty.h".
1684 (init_flag): Remove unneeded variable.
1685 (struct s390_options_t): New structure type.
1686 (options): New structure.
1687 (init_disasm): Rename from this...
1688 (disassemble_init_s390): ...to this. Add initializations for
1689 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1690 (print_insn_s390): Delete call to init_disasm.
1691 (disassembler_options_s390): New function.
1692 (print_s390_disassembler_options): Print using information from
1694 * po/opcodes.pot: Regenerate.
1696 2017-02-28 Jan Beulich <jbeulich@suse.com>
1698 * i386-dis.c (PCMPESTR_Fixup): New.
1699 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1700 (prefix_table): Use PCMPESTR_Fixup.
1701 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1703 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1704 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1705 Split 64-bit and non-64-bit variants.
1706 * opcodes/i386-tbl.h: Re-generate.
1708 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1710 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1711 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1712 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1713 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1714 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1715 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1716 (OP_SVE_V_HSD): New macros.
1717 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1718 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1719 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1720 (aarch64_opcode_table): Add new SVE instructions.
1721 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1722 for rotation operands. Add new SVE operands.
1723 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1724 (ins_sve_quad_index): Likewise.
1725 (ins_imm_rotate): Split into...
1726 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1727 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1728 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1730 (aarch64_ins_sve_addr_ri_s4): New function.
1731 (aarch64_ins_sve_quad_index): Likewise.
1732 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1733 * aarch64-asm-2.c: Regenerate.
1734 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1735 (ext_sve_quad_index): Likewise.
1736 (ext_imm_rotate): Split into...
1737 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1738 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1739 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1741 (aarch64_ext_sve_addr_ri_s4): New function.
1742 (aarch64_ext_sve_quad_index): Likewise.
1743 (aarch64_ext_sve_index): Allow quad indices.
1744 (do_misc_decoding): Likewise.
1745 * aarch64-dis-2.c: Regenerate.
1746 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1747 aarch64_field_kinds.
1748 (OPD_F_OD_MASK): Widen by one bit.
1749 (OPD_F_NO_ZR): Bump accordingly.
1750 (get_operand_field_width): New function.
1751 * aarch64-opc.c (fields): Add new SVE fields.
1752 (operand_general_constraint_met_p): Handle new SVE operands.
1753 (aarch64_print_operand): Likewise.
1754 * aarch64-opc-2.c: Regenerate.
1756 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1758 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1759 (aarch64_feature_compnum): ...this.
1760 (SIMD_V8_3): Replace with...
1762 (CNUM_INSN): New macro.
1763 (aarch64_opcode_table): Use it for the complex number instructions.
1765 2017-02-24 Jan Beulich <jbeulich@suse.com>
1767 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1769 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1771 Add support for associating SPARC ASIs with an architecture level.
1772 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1773 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1774 decoding of SPARC ASIs.
1776 2017-02-23 Jan Beulich <jbeulich@suse.com>
1778 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1779 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1781 2017-02-21 Jan Beulich <jbeulich@suse.com>
1783 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1784 1 (instead of to itself). Correct typo.
1786 2017-02-14 Andrew Waterman <andrew@sifive.com>
1788 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1791 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1793 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1794 (aarch64_sys_reg_supported_p): Handle them.
1796 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1798 * arc-opc.c (UIMM6_20R): Define.
1799 (SIMM12_20): Use above.
1800 (SIMM12_20R): Define.
1801 (SIMM3_5_S): Use above.
1802 (UIMM7_A32_11R_S): Define.
1803 (UIMM7_9_S): Use above.
1804 (UIMM3_13R_S): Define.
1805 (SIMM11_A32_7_S): Use above.
1807 (UIMM10_A32_8_S): Use above.
1808 (UIMM8_8R_S): Define.
1810 (arc_relax_opcodes): Use all above defines.
1812 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1814 * arc-regs.h: Distinguish some of the registers different on
1815 ARC700 and HS38 cpus.
1817 2017-02-14 Alan Modra <amodra@gmail.com>
1820 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1821 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1823 2017-02-11 Stafford Horne <shorne@gmail.com>
1824 Alan Modra <amodra@gmail.com>
1826 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1827 Use insn_bytes_value and insn_int_value directly instead. Don't
1828 free allocated memory until function exit.
1830 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1832 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1834 2017-02-03 Nick Clifton <nickc@redhat.com>
1837 * aarch64-opc.c (print_register_list): Ensure that the register
1838 list index will fir into the tb buffer.
1839 (print_register_offset_address): Likewise.
1840 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1842 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1845 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1846 instructions when the previous fetch packet ends with a 32-bit
1849 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1851 * pru-opc.c: Remove vague reference to a future GDB port.
1853 2017-01-20 Nick Clifton <nickc@redhat.com>
1855 * po/ga.po: Updated Irish translation.
1857 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1859 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1861 2017-01-13 Yao Qi <yao.qi@linaro.org>
1863 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1864 if FETCH_DATA returns 0.
1865 (m68k_scan_mask): Likewise.
1866 (print_insn_m68k): Update code to handle -1 return value.
1868 2017-01-13 Yao Qi <yao.qi@linaro.org>
1870 * m68k-dis.c (enum print_insn_arg_error): New.
1871 (NEXTBYTE): Replace -3 with
1872 PRINT_INSN_ARG_MEMORY_ERROR.
1873 (NEXTULONG): Likewise.
1874 (NEXTSINGLE): Likewise.
1875 (NEXTDOUBLE): Likewise.
1876 (NEXTDOUBLE): Likewise.
1877 (NEXTPACKED): Likewise.
1878 (FETCH_ARG): Likewise.
1879 (FETCH_DATA): Update comments.
1880 (print_insn_arg): Update comments. Replace magic numbers with
1882 (match_insn_m68k): Likewise.
1884 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1886 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1887 * i386-dis-evex.h (evex_table): Updated.
1888 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1889 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1890 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1891 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1892 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1893 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1894 * i386-init.h: Regenerate.
1895 * i386-tbl.h: Ditto.
1897 2017-01-12 Yao Qi <yao.qi@linaro.org>
1899 * msp430-dis.c (msp430_singleoperand): Return -1 if
1900 msp430dis_opcode_signed returns false.
1901 (msp430_doubleoperand): Likewise.
1902 (msp430_branchinstr): Return -1 if
1903 msp430dis_opcode_unsigned returns false.
1904 (msp430x_calla_instr): Likewise.
1905 (print_insn_msp430): Likewise.
1907 2017-01-05 Nick Clifton <nickc@redhat.com>
1910 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1911 could not be matched.
1912 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1915 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1917 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1918 (aarch64_opcode_table): Use RCPC_INSN.
1920 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1922 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1924 * riscv-opcodes/all-opcodes: Likewise.
1926 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1928 * riscv-dis.c (print_insn_args): Add fall through comment.
1930 2017-01-03 Nick Clifton <nickc@redhat.com>
1932 * po/sr.po: New Serbian translation.
1933 * configure.ac (ALL_LINGUAS): Add sr.
1934 * configure: Regenerate.
1936 2017-01-02 Alan Modra <amodra@gmail.com>
1938 * epiphany-desc.h: Regenerate.
1939 * epiphany-opc.h: Regenerate.
1940 * fr30-desc.h: Regenerate.
1941 * fr30-opc.h: Regenerate.
1942 * frv-desc.h: Regenerate.
1943 * frv-opc.h: Regenerate.
1944 * ip2k-desc.h: Regenerate.
1945 * ip2k-opc.h: Regenerate.
1946 * iq2000-desc.h: Regenerate.
1947 * iq2000-opc.h: Regenerate.
1948 * lm32-desc.h: Regenerate.
1949 * lm32-opc.h: Regenerate.
1950 * m32c-desc.h: Regenerate.
1951 * m32c-opc.h: Regenerate.
1952 * m32r-desc.h: Regenerate.
1953 * m32r-opc.h: Regenerate.
1954 * mep-desc.h: Regenerate.
1955 * mep-opc.h: Regenerate.
1956 * mt-desc.h: Regenerate.
1957 * mt-opc.h: Regenerate.
1958 * or1k-desc.h: Regenerate.
1959 * or1k-opc.h: Regenerate.
1960 * xc16x-desc.h: Regenerate.
1961 * xc16x-opc.h: Regenerate.
1962 * xstormy16-desc.h: Regenerate.
1963 * xstormy16-opc.h: Regenerate.
1965 2017-01-02 Alan Modra <amodra@gmail.com>
1967 Update year range in copyright notice of all files.
1969 For older changes see ChangeLog-2016
1971 Copyright (C) 2017 Free Software Foundation, Inc.
1973 Copying and distribution of this file, with or without modification,
1974 are permitted in any medium without royalty provided the copyright
1975 notice and this notice are preserved.
1981 version-control: never