3595faf5285bbe4e92b51885973cb0504c31361f
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2012-03-15 Alan Modra <amodra@gmail.com>
2 James Lemke <jwlemke@codesourcery.com>
3
4 * disassemble.c (disassemble_init_for_target): Handle ppc init.
5 * ppc-dis.c (private): New var.
6 (powerpc_init_dialect): Don't return calloc failure, instead use
7 private.
8 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
9 (powerpc_opcd_indices): New array.
10 (disassemble_init_powerpc): New function.
11 (print_insn_big_powerpc): Don't init dialect here.
12 (print_insn_little_powerpc): Likewise.
13 (print_insn_powerpc): Start search using powerpc_opcd_indices.
14
15 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
16
17 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
18 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
19 (PPCVEC2, PPCTMR, E6500): New short names.
20 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
21 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
22 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
23 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
24 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
25 optional operands on sync instruction for E6500 target.
26
27 2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
28
29 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
30
31 2012-02-27 Alan Modra <amodra@gmail.com>
32
33 * mt-dis.c: Regenerate.
34
35 2012-02-27 Alan Modra <amodra@gmail.com>
36
37 * v850-opc.c (extract_v8): Rearrange to make it obvious this
38 is the inverse of corresponding insert function.
39 (extract_d22, extract_u9, extract_r4): Likewise.
40 (extract_d9): Correct sign extension.
41 (extract_d16_15): Don't assume "long" is 32 bits, and don't
42 rely on implementation defined behaviour for shift right of
43 signed types.
44 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
45 (extract_d23): Likewise, and correct mask.
46
47 2012-02-27 Alan Modra <amodra@gmail.com>
48
49 * crx-dis.c (print_arg): Mask constant to 32 bits.
50 * crx-opc.c (cst4_map): Use int array.
51
52 2012-02-27 Alan Modra <amodra@gmail.com>
53
54 * arc-dis.c (BITS): Don't use shifts to mask off bits.
55 (FIELDD): Sign extend with xor,sub.
56
57 2012-02-25 Walter Lee <walt@tilera.com>
58
59 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
60 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
61 TILEPRO_OPC_LW_TLS_SN.
62
63 2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
64
65 * i386-opc.h (HLEPrefixNone): New.
66 (HLEPrefixLock): Likewise.
67 (HLEPrefixAny): Likewise.
68 (HLEPrefixRelease): Likewise.
69
70 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
71
72 * i386-dis.c (HLE_Fixup1): New.
73 (HLE_Fixup2): Likewise.
74 (HLE_Fixup3): Likewise.
75 (Ebh1): Likewise.
76 (Evh1): Likewise.
77 (Ebh2): Likewise.
78 (Evh2): Likewise.
79 (Ebh3): Likewise.
80 (Evh3): Likewise.
81 (MOD_C6_REG_7): Likewise.
82 (MOD_C7_REG_7): Likewise.
83 (RM_C6_REG_7): Likewise.
84 (RM_C7_REG_7): Likewise.
85 (XACQUIRE_PREFIX): Likewise.
86 (XRELEASE_PREFIX): Likewise.
87 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
88 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
89 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
90 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
91 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
92 MOD_C6_REG_7 and MOD_C7_REG_7.
93 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
94 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
95 xtest.
96 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
97 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
98
99 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
100 CPU_RTM_FLAGS.
101 (cpu_flags): Add CpuHLE and CpuRTM.
102 (opcode_modifiers): Add HLEPrefixOk.
103
104 * i386-opc.h (CpuHLE): New.
105 (CpuRTM): Likewise.
106 (HLEPrefixOk): Likewise.
107 (i386_cpu_flags): Add cpuhle and cpurtm.
108 (i386_opcode_modifier): Add hleprefixok.
109
110 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
111 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
112 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
113 operand. Add xacquire, xrelease, xabort, xbegin, xend and
114 xtest.
115 * i386-init.h: Regenerated.
116 * i386-tbl.h: Likewise.
117
118 2012-01-24 DJ Delorie <dj@redhat.com>
119
120 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
121 * rl78-decode.c: Regenerate.
122
123 2012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
124
125 PR binutils/10173
126 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
127
128 2012-01-17 Andreas Schwab <schwab@linux-m68k.org>
129
130 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
131 register and move them after pmove with PSR/PCSR register.
132
133 2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
134
135 * i386-dis.c (mod_table): Add vmfunc.
136
137 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
138 (cpu_flags): CpuVMFUNC.
139
140 * i386-opc.h (CpuVMFUNC): New.
141 (i386_cpu_flags): Add cpuvmfunc.
142
143 * i386-opc.tbl: Add vmfunc.
144 * i386-init.h: Regenerated.
145 * i386-tbl.h: Likewise.
146
147 For older changes see ChangeLog-2011
148 \f
149 Local Variables:
150 mode: change-log
151 left-margin: 8
152 fill-column: 74
153 version-control: never
154 End:
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