opcodes/ChangeLog

   1 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
   4         pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
   5         pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
   6         pmscr_el2.
   7         (aarch64_sys_reg_supported_p): Add architecture feature tests for
   8         the new registers.
   9
  10 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  11
  12         * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
  13         (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
  14         feature test for "s1e1rp" and "s1e1wp".
  15
  16 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  17
  18         * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
  19         (aarch64_sys_ins_reg_supported_p): New.
  20
  21 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  22
  23         * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
  24         with aarch64_sys_ins_reg_has_xt.
  25         (aarch64_ext_sysins_op): Likewise.
  26         * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
  27         (F_HASXT): New.
  28         (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
  29         (aarch64_sys_regs_dc): Likewise.
  30         (aarch64_sys_regs_at): Likewise.
  31         (aarch64_sys_regs_tlbi): Likewise.
  32         (aarch64_sys_ins_reg_has_xt): New.
  33
  34 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  35
  36         * aarch64-opc.c (aarch64_sys_regs): Add "uao".
  37         (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
  38         (aarch64_pstatefields): Add "uao".
  39         (aarch64_pstatefield_supported_p): Add checks for "uao".
  40
  41 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  42
  43         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
  44         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
  45         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
  46         (aarch64_sys_reg_supported_p): Add architecture feature tests for
  47         new registers.
  48
  49 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  50
  51         * aarch64-asm-2.c: Regenerate.
  52         * aarch64-dis-2.c: Regenerate.
  53         * aarch64-tbl.h (aarch64_feature_ras): New.
  54         (RAS): New.
  55         (aarch64_opcode_table): Add "esb".
  56
  57 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
  58
  59         * i386-dis.c (MOD_0F01_REG_5): New.
  60         (RM_0F01_REG_5): Likewise.
  61         (reg_table): Use MOD_0F01_REG_5.
  62         (mod_table): Add MOD_0F01_REG_5.
  63         (rm_table): Add RM_0F01_REG_5.
  64         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
  65         (cpu_flags): Add CpuOSPKE.
  66         * i386-opc.h (CpuOSPKE): New.
  67         (i386_cpu_flags): Add cpuospke.
  68         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
  69         * i386-init.h: Regenerated.
  70         * i386-tbl.h: Likewise.
  71
  72 2015-12-07  DJ Delorie  <dj@redhat.com>
  73
  74         * rl78-decode.opc: Enable MULU for all ISAs.
  75         * rl78-decode.c: Regenerate.
  76
  77 2015-12-07  Alan Modra  <amodra@gmail.com>
  78
  79         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
  80         major opcode/xop.
  81
  82 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
  83
  84         * arc-dis.c (special_flag_p): Match full mnemonic.
  85         * arc-opc.c (print_insn_arc): Check section size to read
  86         appropriate number of bytes. Fix printing.
  87         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
  88         arguments.
  89
  90 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  91
  92         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
  93         <ldah>: ... to this.
  94
  95 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  96
  97         * aarch64-asm-2.c: Regenerate.
  98         * aarch64-dis-2.c: Regenerate.
  99         * aarch64-opc-2.c: Regenerate.
 100         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
 101         (QL_INT2FP_H, QL_FP2INT_H): New.
 102         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
 103         (QL_DST_H): New.
 104         (QL_FCCMP_H): New.
 105         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
 106         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
 107         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
 108         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
 109         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
 110         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
 111         fcsel.
 112
 113 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 114
 115         * aarch64-opc.c (half_conv_t): New.
 116         (expand_fp_imm): Replace is_dp flag with the parameter size to
 117         specify the number of bytes for the required expansion.  Treat
 118         a 16-bit expansion like a 32-bit expansion.  Add check for an
 119         unsupported size request.  Update comment.
 120         (aarch64_print_operand): Update to support 16-bit floating point
 121         values.  Update for changes to expand_fp_imm.
 122
 123 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 124
 125         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
 126         (FP_F16): New.
 127
 128 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 129
 130         * aarch64-asm-2.c: Regenerate.
 131         * aarch64-dis-2.c: Regenerate.
 132         * aarch64-opc-2.c: Regenerate.
 133         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
 134         "rev64".
 135
 136 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 137
 138         * aarch64-asm-2.c: Regenerate.
 139         * aarch64-asm.c (convert_bfc_to_bfm): New.
 140         (convert_to_real): Add case for OP_BFC.
 141         * aarch64-dis-2.c: Regenerate.
 142         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 143         (convert_to_alias): Add case for OP_BFC.
 144         * aarch64-opc-2.c: Regenerate.
 145         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 146         to allow width operand in three-operand instructions.
 147         * aarch64-tbl.h (QL_BF1): New.
 148         (aarch64_feature_v8_2): New.
 149         (ARMV8_2): New.
 150         (aarch64_opcode_table): Add "bfc".
 151
 152 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 153
 154         * aarch64-asm-2.c: Regenerate.
 155         * aarch64-dis-2.c: Regenerate.
 156         * aarch64-dis.c: Weaken assert.
 157         * aarch64-gen.c: Include the instruction in the list of its
 158         possible aliases.
 159
 160 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 161
 162         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 163         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 164         feature test.
 165
 166 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 167
 168         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 169
 170 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 171
 172         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 173         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 174         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 175         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 176         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 177         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 178         cnthv_ctl_el2, cnthv_cval_el2.
 179         (aarch64_sys_reg_supported_p): Update for the new system
 180         registers.
 181
 182 2015-11-20  Nick Clifton  <nickc@redhat.com>
 183
 184         PR binutils/19224
 185         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 186
 187 2015-11-20  Nick Clifton  <nickc@redhat.com>
 188
 189         * po/zh_CN.po: Updated simplified Chinese translation.
 190
 191 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 192
 193         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 194         of MSR PAN immediate operand.
 195
 196 2015-11-16  Nick Clifton  <nickc@redhat.com>
 197
 198         * rx-dis.c (condition_names): Replace always and never with
 199         invalid, since the always/never conditions can never be legal.
 200
 201 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 202
 203         * configure: Regenerate.
 204
 205 2015-11-11  Alan Modra  <amodra@gmail.com>
 206             Peter Bergner <bergner@vnet.ibm.com>
 207
 208         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 209         Add PPC_OPCODE_VSX3 to the vsx entry.
 210         (powerpc_init_dialect): Set default dialect to power9.
 211         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 212         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 213         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 214         (insert_esync): Test for illegal L operand value.
 215         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 216         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 217         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 218         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 219         PPCVSX3): New defines.
 220         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 221         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 222         <mcrxr>: Use XBFRARB_MASK.
 223         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 224         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 225         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 226         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 227         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 228         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 229         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 230         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 231         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 232         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 233         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 234         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 235         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 236         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 237         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 238         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 239         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 240         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 241         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 242         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 243         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 244         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 245         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 246         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 247         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 248         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 249         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 250         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 251         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 252         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 253         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 254         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 255
 256 2015-11-02  Nick Clifton  <nickc@redhat.com>
 257
 258         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 259         instructions.
 260         * rx-decode.c: Regenerate.
 261
 262 2015-11-02  Nick Clifton  <nickc@redhat.com>
 263
 264         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 265         type to RX_Operand_Zero_Indirect.
 266         * rx-decode.c: Regenerate.
 267         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 268
 269 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 270
 271         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 272         noaliases_p.  Update comments.  Pass noaliases_p rather than
 273         no_aliases to aarch64_opcode_decode.
 274         (print_insn_aarch64_word): Pass no_aliases to
 275         aarch64_decode_insn.
 276
 277 2015-10-27  Vinay  <Vinay.G@kpit.com>
 278
 279         PR binutils/19159
 280         * rl78-decode.opc (MOV): Added offset to DE register in index
 281         addressing mode.
 282         * rl78-decode.c: Regenerate.
 283
 284 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 285
 286         PR binutils/19158
 287         * rl78-decode.opc: Add 's' print operator to instructions that
 288         access system registers.
 289         * rl78-decode.c: Regenerate.
 290         * rl78-dis.c (print_insn_rl78_common): Decode all system
 291         registers.
 292
 293 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 294
 295         PR binutils/19157
 296         * rl78-decode.opc: Add 'a' print operator to mov instructions
 297         using stack pointer plus index addressing.
 298         * rl78-decode.c: Regenerate.
 299
 300 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 301
 302         * s390-opc.c: Fix comment.
 303         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 304         trtt to RRF_U0RER since the second parameter does not need to be a
 305         register pair.
 306
 307 2015-10-08  Nick Clifton  <nickc@redhat.com>
 308
 309         * arc-dis.c (print_insn_arc): Initiallise insn array.
 310
 311 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 312
 313         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 314         'name' rather than 'template'.
 315         * aarch64-opc.c (aarch64_print_operand): Likewise.
 316
 317 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 318
 319         * arc-dis.c: Revamped file for ARC support
 320         * arc-dis.h: Likewise.
 321         * arc-ext.c: Likewise.
 322         * arc-ext.h: Likewise.
 323         * arc-opc.c: Likewise.
 324         * arc-fxi.h: New file.
 325         * arc-regs.h: Likewise.
 326         * arc-tbl.h: Likewise.
 327
 328 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 329
 330         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 331         argument insn type to aarch64_insn.  Rename to ...
 332         (aarch64_decode_insn): ... it.
 333         (print_insn_aarch64_word): Caller updated.
 334
 335 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 336
 337         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 338         (print_insn_aarch64_word): Caller updated.
 339
 340 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 341
 342         * s390-mkopc.c (main): Parse htm and vx flag.
 343         * s390-opc.txt: Mark instructions from the hardware transactional
 344         memory and vector facilities with the "htm"/"vx" flag.
 345
 346 2015-09-28  Nick Clifton  <nickc@redhat.com>
 347
 348         * po/de.po: Updated German translation.
 349
 350 2015-09-28  Tom Rix  <tom@bumblecow.com>
 351
 352         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 353
 354 2015-09-23  Nick Clifton  <nickc@redhat.com>
 355
 356         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 357         function.
 358         * tic30-dis.c (print_branch): Likewise.
 359         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 360         value before left shifting.
 361         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 362         * hppa-dis.c (print_insn_hppa): Likewise.
 363         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 364         array.
 365         * msp430-dis.c (msp430_singleoperand): Likewise.
 366         (msp430_doubleoperand): Likewise.
 367         (print_insn_msp430): Likewise.
 368         * nds32-asm.c (parse_operand): Likewise.
 369         * sh-opc.h (MASK): Likewise.
 370         * v850-dis.c (get_operand_value): Likewise.
 371
 372 2015-09-22  Nick Clifton  <nickc@redhat.com>
 373
 374         * rx-decode.opc (bwl): Use RX_Bad_Size.
 375         (sbwl): Likewise.
 376         (ubwl): Likewise.  Rename to ubw.
 377         (uBWL): Rename to uBW.
 378         Replace all references to uBWL with uBW.
 379         * rx-decode.c: Regenerate.
 380         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 381         (opsize_names): Likewise.
 382         (print_insn_rx): Detect and report RX_Bad_Size.
 383
 384 2015-09-22  Anton Blanchard  <anton@samba.org>
 385
 386         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 387
 388 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 389
 390         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 391         %pmcdper.
 392
 393 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 394
 395         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 396
 397 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 398
 399         PR binutils/18257
 400         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 401         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 402         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 403         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 404         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 405         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 406         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 407         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 408         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 409         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 410         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 411         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 412         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 413         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 414         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 415         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 416         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 417         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 418         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 419         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 420         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 421         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 422         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 423         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 424         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 425         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 426         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 427         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 428         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 429         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 430         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 431         (vex_w_table): Replace terminals with MOD_TABLE entries for
 432         most of mask instructions.
 433
 434 2015-08-17  Alan Modra  <amodra@gmail.com>
 435
 436         * cgen.sh: Trim trailing space from cgen output.
 437         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 438         (print_dis_table): Likewise.
 439         * opc2c.c (dump_lines): Likewise.
 440         (orig_filename): Warning fix.
 441         * ia64-asmtab.c: Regenerate.
 442
 443 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 444
 445         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 446         and higher with ARM instruction set will now mark the 26-bit
 447         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 448         (arm_opcodes): Fix for unpredictable nop being recognized as a
 449         teq.
 450
 451 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 452
 453         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 454         based on 'or' is first.
 455         * mips-opc.c (mips_builtin_opcodes): Ditto.
 456
 457 2015-08-11  Nick Clifton  <nickc@redhat.com>
 458
 459         PR 18800
 460         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 461         instruction.
 462
 463 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 464
 465         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 466
 467 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 468
 469         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 470         * i386-init.h: Regenerated.
 471
 472 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 473
 474         PR binutils/13571
 475         * i386-dis.c (MOD_0FC3): New.
 476         (PREFIX_0FC3): Renamed to ...
 477         (PREFIX_MOD_0_0FC3): This.
 478         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 479         (prefix_table): Replace Ma with Ev on movntiS.
 480         (mod_table): Add MOD_0FC3.
 481
 482 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 483
 484         * configure: Regenerated.
 485
 486 2015-07-23  Alan Modra  <amodra@gmail.com>
 487
 488         PR 18708
 489         * i386-dis.c (get64): Avoid signed integer overflow.
 490
 491 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 492
 493         PR binutils/18631
 494         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 495         "EXEvexHalfBcstXmmq" for the second operand.
 496         (EVEX_W_0F79_P_2): Likewise.
 497         (EVEX_W_0F7A_P_2): Likewise.
 498         (EVEX_W_0F7B_P_2): Likewise.
 499
 500 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 501
 502         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 503         float bitfield format.
 504         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 505         quarter float bitfield format.
 506
 507 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 508
 509         * configure: Regenerated.
 510
 511 2015-07-03  Alan Modra  <amodra@gmail.com>
 512
 513         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 514         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 515         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 516
 517 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 518             Cesar Philippidis  <cesar@codesourcery.com>
 519
 520         * nios2-dis.c (nios2_extract_opcode): New.
 521         (nios2_disassembler_state): New.
 522         (nios2_find_opcode_hash): Use mach parameter to select correct
 523         disassembler state.
 524         (nios2_print_insn_arg): Extend to support new R2 argument letters
 525         and formats.
 526         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 527         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 528         (NIOS2_NUM_OPCODES): Rename to...
 529         (NIOS2_NUM_R1_OPCODES): This.
 530         (nios2_r2_opcodes): New.
 531         (NIOS2_NUM_R2_OPCODES): New.
 532         (nios2_num_r2_opcodes): New.
 533         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 534         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 535         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 536         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 537         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 538
 539 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 540
 541         * i386-dis.c (OP_Mwaitx): New.
 542         (rm_table): Add monitorx/mwaitx.
 543         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 544         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 545         (operand_type_init): Add CpuMWAITX.
 546         * i386-opc.h (CpuMWAITX): New.
 547         (i386_cpu_flags): Add cpumwaitx.
 548         * i386-opc.tbl: Add monitorx and mwaitx.
 549         * i386-init.h: Regenerated.
 550         * i386-tbl.h: Likewise.
 551
 552 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 553
 554         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 555         (insert_esync): New function.
 556         (LS, WC): Use insert_ls.
 557         (ESYNC): Use insert_esync.
 558
 559 2015-06-22  Nick Clifton  <nickc@redhat.com>
 560
 561         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 562         requested region lies beyond it.
 563         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 564         looking for 32-bit insns.
 565         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 566         data.
 567         * sh-dis.c (print_insn_sh): Likewise.
 568         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 569         blocks of instructions.
 570         * vax-dis.c (print_insn_vax): Check that the requested address
 571         does not clash with the stop_vma.
 572
 573 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 574
 575         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 576         * ppc-opc.c (FXM4): Add non-zero optional value.
 577         (TBR): Likewise.
 578         (SXL): Likewise.
 579         (insert_fxm): Handle new default operand value.
 580         (extract_fxm): Likewise.
 581         (insert_tbr): Likewise.
 582         (extract_tbr): Likewise.
 583
 584 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 585
 586         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 587
 588 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 589
 590         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 591
 592 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 593
 594         * ppc-opc.c: Add comment accidentally removed by old commit.
 595         (MTMSRD_L): Delete.
 596
 597 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 598
 599         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 600
 601 2015-06-04  Nick Clifton  <nickc@redhat.com>
 602
 603         PR 18474
 604         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 605
 606 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 607
 608         * arm-dis.c (arm_opcodes): Add "setpan".
 609         (thumb_opcodes): Add "setpan".
 610
 611 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 612
 613         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 614         macros.
 615
 616 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 617
 618         * aarch64-tbl.h (aarch64_feature_rdma): New.
 619         (RDMA): New.
 620         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 621         * aarch64-asm-2.c: Regenerate.
 622         * aarch64-dis-2.c: Regenerate.
 623         * aarch64-opc-2.c: Regenerate.
 624
 625 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 626
 627         * aarch64-tbl.h (aarch64_feature_lor): New.
 628         (LOR): New.
 629         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 630         "stllrb", "stllrh".
 631         * aarch64-asm-2.c: Regenerate.
 632         * aarch64-dis-2.c: Regenerate.
 633         * aarch64-opc-2.c: Regenerate.
 634
 635 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 636
 637         * aarch64-opc.c (F_ARCHEXT): New.
 638         (aarch64_sys_regs): Add "pan".
 639         (aarch64_sys_reg_supported_p): New.
 640         (aarch64_pstatefields): Add "pan".
 641         (aarch64_pstatefield_supported_p): New.
 642
 643 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 644
 645         * i386-tbl.h: Regenerate.
 646
 647 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-dis.c (print_insn): Swap rounding mode specifier and
 650         general purpose register in Intel mode.
 651
 652 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 655         * i386-tbl.h: Regenerate.
 656
 657 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 658
 659         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 660         * i386-init.h: Regenerated.
 661
 662 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 663
 664         PR binutis/18386
 665         * i386-dis.c: Add comments for '@'.
 666         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 667         (enum x86_64_isa): New.
 668         (isa64): Likewise.
 669         (print_i386_disassembler_options): Add amd64 and intel64.
 670         (print_insn): Handle amd64 and intel64.
 671         (putop): Handle '@'.
 672         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 673         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 674         * i386-opc.h (AMD64): New.
 675         (CpuIntel64): Likewise.
 676         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 677         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 678         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 679         * i386-init.h: Regenerated.
 680         * i386-tbl.h: Likewise.
 681
 682 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 683
 684         * ppc-opc.c (IH) New define.
 685         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 686         <tlbie>: Add RS operand for POWER7.
 687         <slbia>: Add IH operand for POWER6.
 688
 689 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 690
 691         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 692         direct branch.
 693         (jmp): Likewise.
 694         * i386-tbl.h: Regenerated.
 695
 696 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 697
 698         * configure.ac: Support bfd_iamcu_arch.
 699         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 700         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 701         CPU_IAMCU_COMPAT_FLAGS.
 702         (cpu_flags): Add CpuIAMCU.
 703         * i386-opc.h (CpuIAMCU): New.
 704         (i386_cpu_flags): Add cpuiamcu.
 705         * configure: Regenerated.
 706         * i386-init.h: Likewise.
 707         * i386-tbl.h: Likewise.
 708
 709 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 710
 711         PR binutis/18386
 712         * i386-dis.c (X86_64_E8): New.
 713         (X86_64_E9): Likewise.
 714         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 715         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 716         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 717         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 718         (putop): Handle '^'.
 719         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 720         REX_W.
 721
 722 2015-04-30  DJ Delorie  <dj@redhat.com>
 723
 724         * disassemble.c (disassembler): Choose suitable disassembler based
 725         on E_ABI.
 726         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 727         it to decode mul/div insns.
 728         * rl78-decode.c: Regenerate.
 729         * rl78-dis.c (print_insn_rl78): Rename to...
 730         (print_insn_rl78_common): ...this, take ISA parameter.
 731         (print_insn_rl78): New.
 732         (print_insn_rl78_g10): New.
 733         (print_insn_rl78_g13): New.
 734         (print_insn_rl78_g14): New.
 735         (rl78_get_disassembler): New.
 736
 737 2015-04-29  Nick Clifton  <nickc@redhat.com>
 738
 739         * po/fr.po: Updated French translation.
 740
 741 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 742
 743         * ppc-opc.c (DCBT_EO): New define.
 744         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 745         <lharx>: Likewise.
 746         <stbcx.>: Likewise.
 747         <sthcx.>: Likewise.
 748         <waitrsv>: Do not enable for POWER7 and later.
 749         <waitimpl>: Likewise.
 750         <dcbt>: Default to the two operand form of the instruction for all
 751         "old" cpus.  For "new" cpus, use the operand ordering that matches
 752         whether the cpu is server or embedded.
 753         <dcbtst>: Likewise.
 754
 755 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 756
 757         * s390-opc.c: New instruction type VV0UU2.
 758         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 759         and WFC.
 760
 761 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 764         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 765         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 766         (vfpclasspd, vfpclassps): Add %XZ.
 767
 768 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 771         (PREFIX_UD_REPZ): Likewise.
 772         (PREFIX_UD_REPNZ): Likewise.
 773         (PREFIX_UD_DATA): Likewise.
 774         (PREFIX_UD_ADDR): Likewise.
 775         (PREFIX_UD_LOCK): Likewise.
 776
 777 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 778
 779         * i386-dis.c (prefix_requirement): Removed.
 780         (print_insn): Don't set prefix_requirement.  Check
 781         dp->prefix_requirement instead of prefix_requirement.
 782
 783 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 784
 785         PR binutils/17898
 786         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 787         (PREFIX_MOD_0_0FC7_REG_6): This.
 788         (PREFIX_MOD_3_0FC7_REG_6): New.
 789         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 790         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 791         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 792         PREFIX_MOD_3_0FC7_REG_7.
 793         (mod_table): Replace PREFIX_0FC7_REG_6 with
 794         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 795         PREFIX_MOD_3_0FC7_REG_7.
 796
 797 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 798
 799         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 800         (PREFIX_MANDATORY_REPNZ): Likewise.
 801         (PREFIX_MANDATORY_DATA): Likewise.
 802         (PREFIX_MANDATORY_ADDR): Likewise.
 803         (PREFIX_MANDATORY_LOCK): Likewise.
 804         (PREFIX_MANDATORY): Likewise.
 805         (PREFIX_UD_SHIFT): Set to 8
 806         (PREFIX_UD_REPZ): Updated.
 807         (PREFIX_UD_REPNZ): Likewise.
 808         (PREFIX_UD_DATA): Likewise.
 809         (PREFIX_UD_ADDR): Likewise.
 810         (PREFIX_UD_LOCK): Likewise.
 811         (PREFIX_IGNORED_SHIFT): New.
 812         (PREFIX_IGNORED_REPZ): Likewise.
 813         (PREFIX_IGNORED_REPNZ): Likewise.
 814         (PREFIX_IGNORED_DATA): Likewise.
 815         (PREFIX_IGNORED_ADDR): Likewise.
 816         (PREFIX_IGNORED_LOCK): Likewise.
 817         (PREFIX_OPCODE): Likewise.
 818         (PREFIX_IGNORED): Likewise.
 819         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 820         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 821         (three_byte_table): Likewise.
 822         (mod_table): Likewise.
 823         (mandatory_prefix): Renamed to ...
 824         (prefix_requirement): This.
 825         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 826         Update PREFIX_90 entry.
 827         (get_valid_dis386): Check prefix_requirement to see if a prefix
 828         should be ignored.
 829         (print_insn): Replace mandatory_prefix with prefix_requirement.
 830
 831 2015-04-15  Renlin Li  <renlin.li@arm.com>
 832
 833         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 834         use it for ssat and ssat16.
 835         (print_insn_thumb32): Add handle case for 'D' control code.
 836
 837 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 838             H.J. Lu  <hongjiu.lu@intel.com>
 839
 840         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 841         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 842         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 843         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 844         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 845         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 846         Fill prefix_requirement field.
 847         (struct dis386): Add prefix_requirement field.
 848         (dis386): Fill prefix_requirement field.
 849         (dis386_twobyte): Ditto.
 850         (twobyte_has_mandatory_prefix_: Remove.
 851         (reg_table): Fill prefix_requirement field.
 852         (prefix_table): Ditto.
 853         (x86_64_table): Ditto.
 854         (three_byte_table): Ditto.
 855         (xop_table): Ditto.
 856         (vex_table): Ditto.
 857         (vex_len_table): Ditto.
 858         (vex_w_table): Ditto.
 859         (mod_table): Ditto.
 860         (bad_opcode): Ditto.
 861         (print_insn): Use prefix_requirement.
 862         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 863         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 864         (float_reg): Ditto.
 865
 866 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 867
 868         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 869
 870 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         * Makefile.in: Regenerated.
 873
 874 2015-03-25  Anton Blanchard  <anton@samba.org>
 875
 876         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 877         powerpc_opcd_indices and vle_opcd_indices once.
 878
 879 2015-03-25  Anton Blanchard  <anton@samba.org>
 880
 881         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 882
 883 2015-03-24  Terry Guo  <terry.guo@arm.com>
 884
 885         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 886         (opcode16): Likewise.
 887         (coprocessor_opcodes): Replace bit with feature struct.
 888         (neon_opcodes): Likewise.
 889         (arm_opcodes): Likewise.
 890         (thumb_opcodes): Likewise.
 891         (thumb32_opcodes): Likewise.
 892         (print_insn_coprocessor): Likewise.
 893         (print_insn_arm): Likewise.
 894         (select_arm_features): Follow new feature struct.
 895
 896 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 897
 898         * i386-dis.c (rm_table): Add clzero.
 899         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 900         Add CPU_CLZERO_FLAGS.
 901         (cpu_flags): Add CpuCLZERO.
 902         * i386-opc.h: Add CpuCLZERO.
 903         * i386-opc.tbl: Add clzero.
 904         * i386-init.h: Re-generated.
 905         * i386-tbl.h: Re-generated.
 906
 907 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 908
 909         * mips-opc.c (decode_mips_operand): Fix constraint issues
 910         with u and y operands.
 911
 912 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 913
 914         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 915
 916 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 917
 918         * s390-opc.c: Add new IBM z13 instructions.
 919         * s390-opc.txt: Likewise.
 920
 921 2015-03-10  Renlin Li  <renlin.li@arm.com>
 922
 923         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 924         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 925         related alias.
 926         * aarch64-asm-2.c: Regenerate.
 927         * aarch64-dis-2.c: Likewise.
 928         * aarch64-opc-2.c: Likewise.
 929
 930 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 931
 932         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 933
 934 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 935
 936         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 937         arch_sh_up.
 938         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 939         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 940
 941 2015-02-23  Vinay  <Vinay.G@kpit.com>
 942
 943         * rl78-decode.opc (MOV): Added space between two operands for
 944         'mov' instruction in index addressing mode.
 945         * rl78-decode.c: Regenerate.
 946
 947 2015-02-19  Pedro Alves  <palves@redhat.com>
 948
 949         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 950
 951 2015-02-10  Pedro Alves  <palves@redhat.com>
 952             Tom Tromey  <tromey@redhat.com>
 953
 954         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 955         microblaze_and, microblaze_xor.
 956         * microblaze-opc.h (opcodes): Adjust.
 957
 958 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 959
 960         * Makefile.am: Add FT32 files.
 961         * configure.ac: Handle FT32.
 962         * disassemble.c (disassembler): Call print_insn_ft32.
 963         * ft32-dis.c: New file.
 964         * ft32-opc.c: New file.
 965         * Makefile.in: Regenerate.
 966         * configure: Regenerate.
 967         * po/POTFILES.in: Regenerate.
 968
 969 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 970
 971         * nds32-asm.c (keyword_sr): Add new system registers.
 972
 973 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 974
 975         * s390-dis.c (s390_extract_operand): Support vector register
 976         operands.
 977         (s390_print_insn_with_opcode): Support new operands types and add
 978         new handling of optional operands.
 979         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 980         and include opcode/s390.h instead.
 981         (struct op_struct): New field `flags'.
 982         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 983         (dumpTable): Dump flags.
 984         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 985         string.
 986         * s390-opc.c: Add new operands types, instruction formats, and
 987         instruction masks.
 988         (s390_opformats): Add new formats for .insn.
 989         * s390-opc.txt: Add new instructions.
 990
 991 2015-01-01  Alan Modra  <amodra@gmail.com>
 992
 993         Update year range in copyright notice of all files.
 994
 995 For older changes see ChangeLog-2014
 996 \f
 997 Copyright (C) 2015 Free Software Foundation, Inc.
 998
 999 Copying and distribution of this file, with or without modification,
1000 are permitted in any medium without royalty provided the copyright
1001 notice and this notice are preserved.
1002
1003 Local Variables:
1004 mode: change-log
1005 left-margin: 8
1006 fill-column: 74
1007 version-control: never
1008 End: