opcodes/ChangeLog

   1 2015-04-30  DJ Delorie  <dj@redhat.com>
   2
   3         * disassemble.c (disassembler): Choose suitable disassembler based
   4         on E_ABI.
   5         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
   6         it to decode mul/div insns.
   7         * rl78-decode.c: Regenerate.
   8         * rl78-dis.c (print_insn_rl78): Rename to...
   9         (print_insn_rl78_common): ...this, take ISA parameter.
  10         (print_insn_rl78): New.
  11         (print_insn_rl78_g10): New.
  12         (print_insn_rl78_g13): New.
  13         (print_insn_rl78_g14): New.
  14         (rl78_get_disassembler): New.
  15
  16 2015-04-29  Nick Clifton  <nickc@redhat.com>
  17
  18         * po/fr.po: Updated French translation.
  19
  20 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
  21
  22         * ppc-opc.c (DCBT_EO): New define.
  23         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
  24         <lharx>: Likewise.
  25         <stbcx.>: Likewise.
  26         <sthcx.>: Likewise.
  27         <waitrsv>: Do not enable for POWER7 and later.
  28         <waitimpl>: Likewise.
  29         <dcbt>: Default to the two operand form of the instruction for all
  30         "old" cpus.  For "new" cpus, use the operand ordering that matches
  31         whether the cpu is server or embedded.
  32         <dcbtst>: Likewise.
  33
  34 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  35
  36         * s390-opc.c: New instruction type VV0UU2.
  37         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
  38         and WFC.
  39
  40 2015-04-23  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
  43         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
  44         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
  45         (vfpclasspd, vfpclassps): Add %XZ.
  46
  47 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
  50         (PREFIX_UD_REPZ): Likewise.
  51         (PREFIX_UD_REPNZ): Likewise.
  52         (PREFIX_UD_DATA): Likewise.
  53         (PREFIX_UD_ADDR): Likewise.
  54         (PREFIX_UD_LOCK): Likewise.
  55
  56 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  57
  58         * i386-dis.c (prefix_requirement): Removed.
  59         (print_insn): Don't set prefix_requirement.  Check
  60         dp->prefix_requirement instead of prefix_requirement.
  61
  62 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  63
  64         PR binutils/17898
  65         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
  66         (PREFIX_MOD_0_0FC7_REG_6): This.
  67         (PREFIX_MOD_3_0FC7_REG_6): New.
  68         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
  69         (prefix_table): Replace PREFIX_0FC7_REG_6 with
  70         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
  71         PREFIX_MOD_3_0FC7_REG_7.
  72         (mod_table): Replace PREFIX_0FC7_REG_6 with
  73         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
  74         PREFIX_MOD_3_0FC7_REG_7.
  75
  76 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  77
  78         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
  79         (PREFIX_MANDATORY_REPNZ): Likewise.
  80         (PREFIX_MANDATORY_DATA): Likewise.
  81         (PREFIX_MANDATORY_ADDR): Likewise.
  82         (PREFIX_MANDATORY_LOCK): Likewise.
  83         (PREFIX_MANDATORY): Likewise.
  84         (PREFIX_UD_SHIFT): Set to 8
  85         (PREFIX_UD_REPZ): Updated.
  86         (PREFIX_UD_REPNZ): Likewise.
  87         (PREFIX_UD_DATA): Likewise.
  88         (PREFIX_UD_ADDR): Likewise.
  89         (PREFIX_UD_LOCK): Likewise.
  90         (PREFIX_IGNORED_SHIFT): New.
  91         (PREFIX_IGNORED_REPZ): Likewise.
  92         (PREFIX_IGNORED_REPNZ): Likewise.
  93         (PREFIX_IGNORED_DATA): Likewise.
  94         (PREFIX_IGNORED_ADDR): Likewise.
  95         (PREFIX_IGNORED_LOCK): Likewise.
  96         (PREFIX_OPCODE): Likewise.
  97         (PREFIX_IGNORED): Likewise.
  98         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
  99         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 100         (three_byte_table): Likewise.
 101         (mod_table): Likewise.
 102         (mandatory_prefix): Renamed to ...
 103         (prefix_requirement): This.
 104         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 105         Update PREFIX_90 entry.
 106         (get_valid_dis386): Check prefix_requirement to see if a prefix
 107         should be ignored.
 108         (print_insn): Replace mandatory_prefix with prefix_requirement.
 109
 110 2015-04-15  Renlin Li  <renlin.li@arm.com>
 111
 112         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 113         use it for ssat and ssat16.
 114         (print_insn_thumb32): Add handle case for 'D' control code.
 115
 116 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 117             H.J. Lu  <hongjiu.lu@intel.com>
 118
 119         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 120         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 121         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 122         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 123         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 124         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 125         Fill prefix_requirement field.
 126         (struct dis386): Add prefix_requirement field.
 127         (dis386): Fill prefix_requirement field.
 128         (dis386_twobyte): Ditto.
 129         (twobyte_has_mandatory_prefix_: Remove.
 130         (reg_table): Fill prefix_requirement field.
 131         (prefix_table): Ditto.
 132         (x86_64_table): Ditto.
 133         (three_byte_table): Ditto.
 134         (xop_table): Ditto.
 135         (vex_table): Ditto.
 136         (vex_len_table): Ditto.
 137         (vex_w_table): Ditto.
 138         (mod_table): Ditto.
 139         (bad_opcode): Ditto.
 140         (print_insn): Use prefix_requirement.
 141         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 142         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 143         (float_reg): Ditto.
 144
 145 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 146
 147         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 148
 149 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         * Makefile.in: Regenerated.
 152
 153 2015-03-25  Anton Blanchard  <anton@samba.org>
 154
 155         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 156         powerpc_opcd_indices and vle_opcd_indices once.
 157
 158 2015-03-25  Anton Blanchard  <anton@samba.org>
 159
 160         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 161
 162 2015-03-24  Terry Guo  <terry.guo@arm.com>
 163
 164         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 165         (opcode16): Likewise.
 166         (coprocessor_opcodes): Replace bit with feature struct.
 167         (neon_opcodes): Likewise.
 168         (arm_opcodes): Likewise.
 169         (thumb_opcodes): Likewise.
 170         (thumb32_opcodes): Likewise.
 171         (print_insn_coprocessor): Likewise.
 172         (print_insn_arm): Likewise.
 173         (select_arm_features): Follow new feature struct.
 174
 175 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 176
 177         * i386-dis.c (rm_table): Add clzero.
 178         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 179         Add CPU_CLZERO_FLAGS.
 180         (cpu_flags): Add CpuCLZERO.
 181         * i386-opc.h: Add CpuCLZERO.
 182         * i386-opc.tbl: Add clzero.
 183         * i386-init.h: Re-generated.
 184         * i386-tbl.h: Re-generated.
 185
 186 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 187
 188         * mips-opc.c (decode_mips_operand): Fix constraint issues
 189         with u and y operands.
 190
 191 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 192
 193         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 194
 195 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 196
 197         * s390-opc.c: Add new IBM z13 instructions.
 198         * s390-opc.txt: Likewise.
 199
 200 2015-03-10  Renlin Li  <renlin.li@arm.com>
 201
 202         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 203         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 204         related alias.
 205         * aarch64-asm-2.c: Regenerate.
 206         * aarch64-dis-2.c: Likewise.
 207         * aarch64-opc-2.c: Likewise.
 208
 209 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 210
 211         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 212
 213 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 214
 215         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 216         arch_sh_up.
 217         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 218         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 219
 220 2015-02-23  Vinay  <Vinay.G@kpit.com>
 221
 222         * rl78-decode.opc (MOV): Added space between two operands for
 223         'mov' instruction in index addressing mode.
 224         * rl78-decode.c: Regenerate.
 225
 226 2015-02-19  Pedro Alves  <palves@redhat.com>
 227
 228         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 229
 230 2015-02-10  Pedro Alves  <palves@redhat.com>
 231             Tom Tromey  <tromey@redhat.com>
 232
 233         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 234         microblaze_and, microblaze_xor.
 235         * microblaze-opc.h (opcodes): Adjust.
 236
 237 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 238
 239         * Makefile.am: Add FT32 files.
 240         * configure.ac: Handle FT32.
 241         * disassemble.c (disassembler): Call print_insn_ft32.
 242         * ft32-dis.c: New file.
 243         * ft32-opc.c: New file.
 244         * Makefile.in: Regenerate.
 245         * configure: Regenerate.
 246         * po/POTFILES.in: Regenerate.
 247
 248 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 249
 250         * nds32-asm.c (keyword_sr): Add new system registers.
 251
 252 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 253
 254         * s390-dis.c (s390_extract_operand): Support vector register
 255         operands.
 256         (s390_print_insn_with_opcode): Support new operands types and add
 257         new handling of optional operands.
 258         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 259         and include opcode/s390.h instead.
 260         (struct op_struct): New field `flags'.
 261         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 262         (dumpTable): Dump flags.
 263         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 264         string.
 265         * s390-opc.c: Add new operands types, instruction formats, and
 266         instruction masks.
 267         (s390_opformats): Add new formats for .insn.
 268         * s390-opc.txt: Add new instructions.
 269
 270 2015-01-01  Alan Modra  <amodra@gmail.com>
 271
 272         Update year range in copyright notice of all files.
 273
 274 For older changes see ChangeLog-2014
 275 \f
 276 Copyright (C) 2015 Free Software Foundation, Inc.
 277
 278 Copying and distribution of this file, with or without modification,
 279 are permitted in any medium without royalty provided the copyright
 280 notice and this notice are preserved.
 281
 282 Local Variables:
 283 mode: change-log
 284 left-margin: 8
 285 fill-column: 74
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 287 End: