1 2020-07-14 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
5 2020-07-14 Jan Beulich <jbeulich@suse.com>
7 * i386-dis.c (OP_R, Rm): Delete.
8 (MOD_0F24, MOD_0F26): Rename to ...
9 (X86_64_0F24, X86_64_0F26): ... respectively.
10 (dis386): Update 'L' and 'Z' comments.
11 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
13 (mod_table): Move opcode 0F24 and 0F26 entries ...
14 (x86_64_table): ... here.
15 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
18 2020-07-14 Jan Beulich <jbeulich@suse.com>
20 * i386-dis.c (Rd, Rdq, MaskR): Delete.
21 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
22 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
23 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
24 MOD_EVEX_0F387C): New enumerators.
25 (reg_table): Use Edq for rdssp.
26 (prefix_table): Use Edq for incssp.
27 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
28 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
29 ktest*, and kshift*. Use Edq / MaskE for kmov*.
30 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
31 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
32 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
33 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
34 0F3828_P_1 and 0F3838_P_1.
35 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
36 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
38 2020-07-14 Jan Beulich <jbeulich@suse.com>
40 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
41 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
42 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
43 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
44 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
45 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
46 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
47 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
48 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
49 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
50 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
51 (reg_table, prefix_table, three_byte_table, vex_table,
52 vex_len_table, mod_table, rm_table): Replace / remove respective
54 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
55 of PREFIX_DATA in used_prefixes.
57 2020-07-14 Jan Beulich <jbeulich@suse.com>
59 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
60 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
61 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
62 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
63 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
64 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
65 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
66 VEX_W_0F3A33_L_0): Delete.
67 (dis386): Adjust "BW" description.
68 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
69 0F3A31, 0F3A32, and 0F3A33.
70 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
72 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
75 2020-07-14 Jan Beulich <jbeulich@suse.com>
77 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
78 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
79 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
80 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
81 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
82 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
83 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
84 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
85 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
86 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
87 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
88 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
89 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
90 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
91 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
92 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
93 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
94 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
95 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
96 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
97 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
98 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
99 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
100 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
101 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
102 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
103 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
104 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
105 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
106 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
107 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
108 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
109 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
110 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
111 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
112 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
113 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
114 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
115 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
116 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
117 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
118 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
119 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
120 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
121 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
122 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
123 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
124 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
125 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
126 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
127 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
128 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
129 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
130 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
131 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
132 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
133 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
134 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
135 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
136 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
137 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
138 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
139 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
140 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
141 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
142 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
143 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
144 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
145 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
146 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
147 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
148 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
149 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
150 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
151 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
152 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
153 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
154 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
155 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
156 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
157 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
158 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
159 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
160 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
161 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
162 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
163 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
164 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
165 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
166 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
167 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
168 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
169 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
170 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
171 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
172 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
173 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
174 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
175 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
176 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
177 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
178 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
179 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
180 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
181 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
182 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
183 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
184 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
185 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
186 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
187 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
188 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
189 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
190 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
191 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
192 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
193 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
194 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
195 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
196 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
197 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
198 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
199 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
200 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
201 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
202 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
203 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
204 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
205 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
206 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
207 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
208 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
209 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
210 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
211 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
212 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
213 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
214 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
215 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
216 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
217 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
218 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
219 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
220 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
221 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
222 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
223 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
224 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
225 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
226 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
227 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
228 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
229 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
230 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
231 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
232 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
233 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
234 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
235 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
236 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
237 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
238 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
239 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
240 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
241 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
242 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
243 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
244 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
245 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
246 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
247 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
248 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
249 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
250 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
251 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
252 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
253 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
254 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
255 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
256 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
257 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
258 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
259 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
260 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
261 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
262 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
263 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
264 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
265 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
266 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
267 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
268 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
269 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
270 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
271 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
272 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
273 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
274 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
275 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
276 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
277 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
278 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
279 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
280 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
281 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
282 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
283 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
284 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
285 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
286 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
287 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
288 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
289 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
290 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
291 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
292 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
293 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
294 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
295 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
296 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
297 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
298 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
299 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
300 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
301 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
302 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
303 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
304 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
305 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
306 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
307 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
308 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
309 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
310 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
311 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
312 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
313 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
314 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
315 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
316 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
317 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
318 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
319 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
320 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
321 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
322 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
323 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
324 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
325 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
326 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
327 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
328 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
329 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
330 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
331 EVEX_W_0F3A72_P_2): Rename to ...
332 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
333 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
334 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
335 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
336 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
337 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
338 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
339 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
340 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
341 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
342 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
343 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
344 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
345 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
346 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
347 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
348 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
349 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
350 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
351 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
352 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
353 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
354 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
355 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
356 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
357 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
358 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
359 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
360 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
361 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
362 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
363 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
364 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
365 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
366 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
367 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
368 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
369 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
370 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
371 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
372 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
373 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
374 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
375 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
376 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
377 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
378 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
379 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
380 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
381 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
382 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
383 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
384 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
385 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
386 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
387 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
388 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
389 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
390 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
391 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
392 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
393 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
394 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
395 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
396 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
397 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
398 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
399 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
400 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
401 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
402 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
403 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
405 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
406 vex_w_table, mod_table): Replace / remove respective entries.
407 (print_insn): Move up dp->prefix_requirement handling. Handle
409 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
410 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
411 Replace / remove respective entries.
413 2020-07-14 Jan Beulich <jbeulich@suse.com>
415 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
416 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
417 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
418 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
419 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
421 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
422 0F2C, 0F2D, 0F2E, and 0F2F.
423 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
426 2020-07-14 Jan Beulich <jbeulich@suse.com>
428 * i386-dis.c (OP_VexR, VexScalarR): New.
429 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
430 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
431 need_vex_reg): Delete.
432 (prefix_table): Replace VexScalar by VexScalarR and
433 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
434 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
435 (vex_len_table): Replace EXqVexScalarS by EXqS.
436 (get_valid_dis386): Don't set need_vex_reg.
437 (print_insn): Don't initialize need_vex_reg.
438 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
439 q_scalar_swap_mode cases.
440 (OP_EX): Don't check for d_scalar_swap_mode and
442 (OP_VEX): Done check need_vex_reg.
443 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
444 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
445 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
447 2020-07-14 Jan Beulich <jbeulich@suse.com>
449 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
450 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
451 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
452 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
453 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
454 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
455 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
456 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
457 (vex_table): Replace Vex128 by Vex.
458 (vex_len_table): Likewise. Adjust referenced enum names.
459 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
460 referenced enum names.
461 (OP_VEX): Drop vex128_mode and vex256_mode cases.
462 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
464 2020-07-14 Jan Beulich <jbeulich@suse.com>
466 * i386-dis.c (dis386): "LW" description now applies to "DQ".
467 (putop): Handle "DQ". Don't handle "LW" anymore.
468 (prefix_table, mod_table): Replace %LW by %DQ.
469 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
471 2020-07-14 Jan Beulich <jbeulich@suse.com>
473 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
474 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
475 d_scalar_swap_mode case handling. Move shift adjsutment into
476 the case its applicable to.
478 2020-07-14 Jan Beulich <jbeulich@suse.com>
480 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
481 (EXbScalar, EXwScalar): Fold to ...
482 (EXbwUnit): ... this.
483 (b_scalar_mode, w_scalar_mode): Fold to ...
484 (bw_unit_mode): ... this.
485 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
486 w_scalar_mode handling by bw_unit_mode one.
487 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
489 * i386-dis-evex-prefix.h: ... here.
491 2020-07-14 Jan Beulich <jbeulich@suse.com>
493 * i386-dis.c (PCMPESTR_Fixup): Delete.
494 (dis386): Adjust "LQ" description.
495 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
496 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
497 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
498 vpcmpestrm, and vpcmpestri.
499 (putop): Honor "cond" when handling LQ.
500 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
501 vcvtsi2ss and vcvtusi2ss.
502 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
503 vcvtsi2sd and vcvtusi2sd.
505 2020-07-14 Jan Beulich <jbeulich@suse.com>
507 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
508 (simd_cmp_op): Add const.
509 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
510 (CMP_Fixup): Handle VEX case.
511 (prefix_table): Replace VCMP by CMP.
512 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
514 2020-07-14 Jan Beulich <jbeulich@suse.com>
516 * i386-dis.c (MOVBE_Fixup): Delete.
518 (prefix_table): Use Mv for movbe entries.
520 2020-07-14 Jan Beulich <jbeulich@suse.com>
522 * i386-dis.c (CRC32_Fixup): Delete.
523 (prefix_table): Use Eb/Ev for crc32 entries.
525 2020-07-14 Jan Beulich <jbeulich@suse.com>
527 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
528 Conditionalize invocations of "USED_REX (0)".
530 2020-07-14 Jan Beulich <jbeulich@suse.com>
532 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
533 CH, DH, BH, AX, DX): Delete.
534 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
535 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
536 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
538 2020-07-10 Lili Cui <lili.cui@intel.com>
540 * i386-dis.c (TMM): New.
543 (MVexSIBMEM): Likewise.
544 (tmm_mode): Likewise.
545 (vex_sibmem_mode): Likewise.
546 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
547 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
548 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
549 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
550 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
551 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
552 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
553 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
554 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
555 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
556 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
557 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
558 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
559 (PREFIX_VEX_0F3849_X86_64): Likewise.
560 (PREFIX_VEX_0F384B_X86_64): Likewise.
561 (PREFIX_VEX_0F385C_X86_64): Likewise.
562 (PREFIX_VEX_0F385E_X86_64): Likewise.
563 (X86_64_VEX_0F3849): Likewise.
564 (X86_64_VEX_0F384B): Likewise.
565 (X86_64_VEX_0F385C): Likewise.
566 (X86_64_VEX_0F385E): Likewise.
567 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
568 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
569 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
570 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
571 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
572 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
573 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
574 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
575 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
576 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
577 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
578 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
579 (VEX_W_0F3849_X86_64_P_0): Likewise.
580 (VEX_W_0F3849_X86_64_P_2): Likewise.
581 (VEX_W_0F3849_X86_64_P_3): Likewise.
582 (VEX_W_0F384B_X86_64_P_1): Likewise.
583 (VEX_W_0F384B_X86_64_P_2): Likewise.
584 (VEX_W_0F384B_X86_64_P_3): Likewise.
585 (VEX_W_0F385C_X86_64_P_1): Likewise.
586 (VEX_W_0F385E_X86_64_P_0): Likewise.
587 (VEX_W_0F385E_X86_64_P_1): Likewise.
588 (VEX_W_0F385E_X86_64_P_2): Likewise.
589 (VEX_W_0F385E_X86_64_P_3): Likewise.
590 (names_tmm): Likewise.
591 (att_names_tmm): Likewise.
592 (intel_operand_size): Handle void_mode.
593 (OP_XMM): Handle tmm_mode.
596 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
597 CpuAMX_BF16 and CpuAMX_TILE.
598 (operand_type_shorthands): Add RegTMM.
599 (operand_type_init): Likewise.
600 (operand_types): Add Tmmword.
601 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
602 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
603 * i386-opc.h (CpuAMX_INT8): New.
604 (CpuAMX_BF16): Likewise.
605 (CpuAMX_TILE): Likewise.
608 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
609 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
610 (i386_operand_type): Add tmmword.
611 * i386-opc.tbl: Add AMX instructions.
612 * i386-reg.tbl: Add AMX registers.
613 * i386-init.h: Regenerated.
614 * i386-tbl.h: Likewise.
616 2020-07-08 Jan Beulich <jbeulich@suse.com>
618 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
619 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
621 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
622 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
624 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
625 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
626 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
627 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
628 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
629 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
630 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
631 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
632 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
633 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
634 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
635 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
636 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
637 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
638 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
639 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
640 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
641 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
642 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
643 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
644 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
645 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
646 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
647 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
648 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
649 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
650 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
651 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
652 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
653 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
654 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
655 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
656 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
657 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
658 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
659 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
660 (reg_table): Re-order XOP entries. Adjust their operands.
661 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
662 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
663 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
664 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
665 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
666 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
667 entries by references ...
668 (vex_len_table): ... to resepctive new entries here. For several
669 new and existing entries reference ...
670 (vex_w_table): ... new entries here.
671 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
673 2020-07-08 Jan Beulich <jbeulich@suse.com>
675 * i386-dis.c (XMVexScalarI4): Define.
676 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
677 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
678 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
679 (vex_len_table): Move scalar FMA4 entries ...
680 (prefix_table): ... here.
681 (OP_REG_VexI4): Handle scalar_mode.
682 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
683 * i386-tbl.h: Re-generate.
685 2020-07-08 Jan Beulich <jbeulich@suse.com>
687 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
689 (OP_VexW, VexW): New.
690 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
691 for shifts and rotates by register.
693 2020-07-08 Jan Beulich <jbeulich@suse.com>
695 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
696 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
697 OP_EX_VexReg): Delete.
698 (OP_VexI4, VexI4): New.
699 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
700 (prefix_table): ... here.
701 (print_insn): Drop setting of vex_w_done.
703 2020-07-08 Jan Beulich <jbeulich@suse.com>
705 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
706 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
707 (xop_table): Replace operands of 4-operand insns.
708 (OP_REG_VexI4): Move VEX.W based operand swaping here.
710 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
712 * arc-opc.c (insert_rbd): New function.
715 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
718 2020-07-07 Jan Beulich <jbeulich@suse.com>
720 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
721 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
722 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
723 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
725 (putop): Handle "BW".
726 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
727 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
729 * i386-dis-evex-prefix.h: ... here.
731 2020-07-06 Jan Beulich <jbeulich@suse.com>
733 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
734 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
735 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
736 VEX_W_0FXOP_09_83): New enumerators.
737 (xop_table): Reference the above.
738 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
739 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
740 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
741 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
743 2020-07-06 Jan Beulich <jbeulich@suse.com>
745 * i386-dis.c (EVEX_W_0F3838_P_1,
746 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
747 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
748 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
749 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
750 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
751 (putop): Centralize management of last[]. Delete SAVE_LAST.
752 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
753 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
754 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
755 * i386-dis-evex-prefix.h: here.
757 2020-07-06 Jan Beulich <jbeulich@suse.com>
759 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
760 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
761 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
762 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
764 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
765 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
766 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
767 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
768 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
769 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
770 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
771 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
773 * i386-dis-evex-len.h: Adjust comments.
774 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
775 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
776 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
777 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
778 MOD_EVEX_0F385B_P_2_W_1 table entries.
779 * i386-dis-evex-w.h: Reference mod_table[] for
780 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
783 2020-07-06 Jan Beulich <jbeulich@suse.com>
785 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
786 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
788 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
789 Likewise. Mark 256-bit entries invalid.
791 2020-07-06 Jan Beulich <jbeulich@suse.com>
793 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
794 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
795 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
796 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
797 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
798 PREFIX_EVEX_0F382B): Delete.
799 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
800 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
801 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
802 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
803 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
805 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
806 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
807 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
808 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
810 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
811 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
812 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
813 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
814 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
815 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
816 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
817 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
818 PREFIX_EVEX_0F382B): Remove table entries.
819 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
820 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
821 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
823 2020-07-06 Jan Beulich <jbeulich@suse.com>
825 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
826 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
828 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
829 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
830 EVEX_LEN_0F3A01_P_2_W_1 table entries.
831 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
834 2020-07-06 Jan Beulich <jbeulich@suse.com>
836 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
837 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
838 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
839 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
840 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
841 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
842 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
843 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
844 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
847 2020-07-06 Jan Beulich <jbeulich@suse.com>
849 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
850 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
851 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
853 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
855 * i386-dis-evex.h (evex_table): Reference VEX table entry for
857 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
859 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
861 2020-07-06 Jan Beulich <jbeulich@suse.com>
863 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
864 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
865 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
866 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
867 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
868 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
869 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
870 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
871 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
872 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
873 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
874 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
875 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
876 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
877 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
878 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
879 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
880 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
881 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
882 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
883 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
884 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
885 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
886 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
887 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
888 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
889 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
890 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
891 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
892 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
893 (prefix_table): Add EXxEVexR to FMA table entries.
894 (OP_Rounding): Move abort() invocation.
895 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
896 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
897 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
898 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
899 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
900 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
901 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
902 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
903 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
904 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
906 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
907 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
908 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
909 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
910 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
911 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
912 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
913 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
914 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
915 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
916 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
917 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
918 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
919 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
920 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
921 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
922 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
923 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
924 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
925 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
926 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
927 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
928 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
929 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
930 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
931 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
932 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
933 Delete table entries.
934 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
935 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
936 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
939 2020-07-06 Jan Beulich <jbeulich@suse.com>
941 * i386-dis.c (EXqScalarS): Delete.
942 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
943 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
945 2020-07-06 Jan Beulich <jbeulich@suse.com>
947 * i386-dis.c (safe-ctype.h): Include.
948 (EXdScalar, EXqScalar): Delete.
949 (d_scalar_mode, q_scalar_mode): Delete.
950 (prefix_table, vex_len_table): Use EXxmm_md in place of
951 EXdScalar and EXxmm_mq in place of EXqScalar.
952 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
953 d_scalar_mode and q_scalar_mode.
954 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
955 (vmovsd): Use EXxmm_mq.
957 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
960 * arc-dis.c: Fix spelling mistake.
961 * po/opcodes.pot: Regenerate.
963 2020-07-06 Nick Clifton <nickc@redhat.com>
965 * po/pt_BR.po: Updated Brazilian Portugugese translation.
966 * po/uk.po: Updated Ukranian translation.
968 2020-07-04 Nick Clifton <nickc@redhat.com>
970 * configure: Regenerate.
971 * po/opcodes.pot: Regenerate.
973 2020-07-04 Nick Clifton <nickc@redhat.com>
975 Binutils 2.35 branch created.
977 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
979 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
980 * i386-opc.h (VexSwapSources): New.
981 (i386_opcode_modifier): Add vexswapsources.
982 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
983 with two source operands swapped.
984 * i386-tbl.h: Regenerated.
986 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
988 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
989 unprivileged CSR can also be initialized.
991 2020-06-29 Alan Modra <amodra@gmail.com>
993 * arm-dis.c: Use C style comments.
994 * cr16-opc.c: Likewise.
995 * ft32-dis.c: Likewise.
996 * moxie-opc.c: Likewise.
997 * tic54x-dis.c: Likewise.
998 * s12z-opc.c: Remove useless comment.
999 * xgate-dis.c: Likewise.
1001 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1003 * i386-opc.tbl: Add a blank line.
1005 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1007 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1008 (VecSIB128): Renamed to ...
1010 (VecSIB256): Renamed to ...
1012 (VecSIB512): Renamed to ...
1014 (VecSIB): Renamed to ...
1016 (i386_opcode_modifier): Replace vecsib with sib.
1017 * i386-opc.tbl (VecSIB128): New.
1018 (VecSIB256): Likewise.
1019 (VecSIB512): Likewise.
1020 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1021 and VecSIB512, respectively.
1023 2020-06-26 Jan Beulich <jbeulich@suse.com>
1025 * i386-dis.c: Adjust description of I macro.
1026 (x86_64_table): Drop use of I.
1027 (float_mem): Replace use of I.
1028 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1030 2020-06-26 Jan Beulich <jbeulich@suse.com>
1032 * i386-dis.c: (print_insn): Avoid straight assignment to
1033 priv.orig_sizeflag when processing -M sub-options.
1035 2020-06-25 Jan Beulich <jbeulich@suse.com>
1037 * i386-dis.c: Adjust description of J macro.
1038 (dis386, x86_64_table, mod_table): Replace J.
1039 (putop): Remove handling of J.
1041 2020-06-25 Jan Beulich <jbeulich@suse.com>
1043 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1045 2020-06-25 Jan Beulich <jbeulich@suse.com>
1047 * i386-dis.c: Adjust description of "LQ" macro.
1048 (dis386_twobyte): Use LQ for sysret.
1049 (putop): Adjust handling of LQ.
1051 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1053 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1054 * riscv-dis.c: Include elfxx-riscv.h.
1056 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1058 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1060 2020-06-17 Lili Cui <lili.cui@intel.com>
1062 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1064 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1067 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1068 * i386-opc.tbl: Likewise.
1069 * i386-tbl.h: Regenerated.
1071 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1073 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1075 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1077 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1078 (SR_CORE): Likewise.
1079 (SR_FEAT): Likewise.
1081 (SR_V8_1): Likewise.
1082 (SR_V8_2): Likewise.
1083 (SR_V8_3): Likewise.
1084 (SR_V8_4): Likewise.
1087 (SR_SSBS): Likewise.
1089 (SR_ID_PFR2): Likewise.
1090 (SR_PROFILE): Likewise.
1091 (SR_MEMTAG): Likewise.
1092 (SR_SCXTNUM): Likewise.
1093 (aarch64_sys_regs): Refactor to store feature information in the table.
1094 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1095 that now describe their own features.
1096 (aarch64_pstatefield_supported_p): Likewise.
1098 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1100 * i386-dis.c (prefix_table): Fix a typo in comments.
1102 2020-06-09 Jan Beulich <jbeulich@suse.com>
1104 * i386-dis.c (rex_ignored): Delete.
1105 (ckprefix): Drop rex_ignored initialization.
1106 (get_valid_dis386): Drop setting of rex_ignored.
1107 (print_insn): Drop checking of rex_ignored. Don't record data
1108 size prefix as used with VEX-and-alike encodings.
1110 2020-06-09 Jan Beulich <jbeulich@suse.com>
1112 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1113 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1114 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1115 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1116 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1117 VEX_0F12, and VEX_0F16.
1118 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1119 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1120 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1121 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1122 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1123 MOD_VEX_0F16_PREFIX_2 entries.
1125 2020-06-09 Jan Beulich <jbeulich@suse.com>
1127 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1128 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1129 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1130 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1131 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1132 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1133 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1134 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1135 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1136 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1137 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1138 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1139 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1140 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1141 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1142 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1143 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1144 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1145 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1146 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1147 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1148 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1149 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1150 EVEX_W_0FC6_P_2): Delete.
1151 (print_insn): Add EVEX.W vs embedded prefix consistency check
1152 to prefix validation.
1153 * i386-dis-evex.h (evex_table): Don't further descend for
1154 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1155 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1157 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1158 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1159 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1160 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1161 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1162 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1163 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1164 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1165 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1166 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1167 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1168 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1169 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1170 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1171 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1172 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1173 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1174 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1175 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1176 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1177 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1178 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1179 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1180 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1181 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1182 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1183 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1185 2020-06-09 Jan Beulich <jbeulich@suse.com>
1187 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1188 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1189 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1191 (print_insn): Drop pointless check against bad_opcode. Split
1192 prefix validation into legacy and VEX-and-alike parts.
1193 (putop): Re-work 'X' macro handling.
1195 2020-06-09 Jan Beulich <jbeulich@suse.com>
1197 * i386-dis.c (MOD_0F51): Rename to ...
1198 (MOD_0F50): ... this.
1200 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1202 * arm-dis.c (arm_opcodes): Add dfb.
1203 (thumb32_opcodes): Add dfb.
1205 2020-06-08 Jan Beulich <jbeulich@suse.com>
1207 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1209 2020-06-06 Alan Modra <amodra@gmail.com>
1211 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1213 2020-06-05 Alan Modra <amodra@gmail.com>
1215 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1216 size is large enough.
1218 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1220 * disassemble.c (disassemble_init_for_target): Set endian_code for
1222 * bpf-desc.c: Regenerate.
1223 * bpf-opc.c: Likewise.
1224 * bpf-dis.c: Likewise.
1226 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1228 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1229 (cgen_put_insn_value): Likewise.
1230 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1231 * cgen-dis.in (print_insn): Likewise.
1232 * cgen-ibld.in (insert_1): Likewise.
1233 (insert_1): Likewise.
1234 (insert_insn_normal): Likewise.
1235 (extract_1): Likewise.
1236 * bpf-dis.c: Regenerate.
1237 * bpf-ibld.c: Likewise.
1238 * bpf-ibld.c: Likewise.
1239 * cgen-dis.in: Likewise.
1240 * cgen-ibld.in: Likewise.
1241 * cgen-opc.c: Likewise.
1242 * epiphany-dis.c: Likewise.
1243 * epiphany-ibld.c: Likewise.
1244 * fr30-dis.c: Likewise.
1245 * fr30-ibld.c: Likewise.
1246 * frv-dis.c: Likewise.
1247 * frv-ibld.c: Likewise.
1248 * ip2k-dis.c: Likewise.
1249 * ip2k-ibld.c: Likewise.
1250 * iq2000-dis.c: Likewise.
1251 * iq2000-ibld.c: Likewise.
1252 * lm32-dis.c: Likewise.
1253 * lm32-ibld.c: Likewise.
1254 * m32c-dis.c: Likewise.
1255 * m32c-ibld.c: Likewise.
1256 * m32r-dis.c: Likewise.
1257 * m32r-ibld.c: Likewise.
1258 * mep-dis.c: Likewise.
1259 * mep-ibld.c: Likewise.
1260 * mt-dis.c: Likewise.
1261 * mt-ibld.c: Likewise.
1262 * or1k-dis.c: Likewise.
1263 * or1k-ibld.c: Likewise.
1264 * xc16x-dis.c: Likewise.
1265 * xc16x-ibld.c: Likewise.
1266 * xstormy16-dis.c: Likewise.
1267 * xstormy16-ibld.c: Likewise.
1269 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1271 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1272 (print_insn_): Handle instruction endian.
1273 * bpf-dis.c: Regenerate.
1274 * bpf-desc.c: Regenerate.
1275 * epiphany-dis.c: Likewise.
1276 * epiphany-desc.c: Likewise.
1277 * fr30-dis.c: Likewise.
1278 * fr30-desc.c: Likewise.
1279 * frv-dis.c: Likewise.
1280 * frv-desc.c: Likewise.
1281 * ip2k-dis.c: Likewise.
1282 * ip2k-desc.c: Likewise.
1283 * iq2000-dis.c: Likewise.
1284 * iq2000-desc.c: Likewise.
1285 * lm32-dis.c: Likewise.
1286 * lm32-desc.c: Likewise.
1287 * m32c-dis.c: Likewise.
1288 * m32c-desc.c: Likewise.
1289 * m32r-dis.c: Likewise.
1290 * m32r-desc.c: Likewise.
1291 * mep-dis.c: Likewise.
1292 * mep-desc.c: Likewise.
1293 * mt-dis.c: Likewise.
1294 * mt-desc.c: Likewise.
1295 * or1k-dis.c: Likewise.
1296 * or1k-desc.c: Likewise.
1297 * xc16x-dis.c: Likewise.
1298 * xc16x-desc.c: Likewise.
1299 * xstormy16-dis.c: Likewise.
1300 * xstormy16-desc.c: Likewise.
1302 2020-06-03 Nick Clifton <nickc@redhat.com>
1304 * po/sr.po: Updated Serbian translation.
1306 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1308 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1309 (riscv_get_priv_spec_class): Likewise.
1311 2020-06-01 Alan Modra <amodra@gmail.com>
1313 * bpf-desc.c: Regenerate.
1315 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1316 David Faust <david.faust@oracle.com>
1318 * bpf-desc.c: Regenerate.
1319 * bpf-opc.h: Likewise.
1320 * bpf-opc.c: Likewise.
1321 * bpf-dis.c: Likewise.
1323 2020-05-28 Alan Modra <amodra@gmail.com>
1325 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1328 2020-05-28 Alan Modra <amodra@gmail.com>
1330 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1332 (print_insn_ns32k): Revert last change.
1334 2020-05-28 Nick Clifton <nickc@redhat.com>
1336 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1339 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1341 Fix extraction of signed constants in nios2 disassembler (again).
1343 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1344 extractions of signed fields.
1346 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1348 * s390-opc.txt: Relocate vector load/store instructions with
1349 additional alignment parameter and change architecture level
1350 constraint from z14 to z13.
1352 2020-05-21 Alan Modra <amodra@gmail.com>
1354 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1355 * sparc-dis.c: Likewise.
1356 * tic4x-dis.c: Likewise.
1357 * xtensa-dis.c: Likewise.
1358 * bpf-desc.c: Regenerate.
1359 * epiphany-desc.c: Regenerate.
1360 * fr30-desc.c: Regenerate.
1361 * frv-desc.c: Regenerate.
1362 * ip2k-desc.c: Regenerate.
1363 * iq2000-desc.c: Regenerate.
1364 * lm32-desc.c: Regenerate.
1365 * m32c-desc.c: Regenerate.
1366 * m32r-desc.c: Regenerate.
1367 * mep-asm.c: Regenerate.
1368 * mep-desc.c: Regenerate.
1369 * mt-desc.c: Regenerate.
1370 * or1k-desc.c: Regenerate.
1371 * xc16x-desc.c: Regenerate.
1372 * xstormy16-desc.c: Regenerate.
1374 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1376 * riscv-opc.c (riscv_ext_version_table): The table used to store
1377 all information about the supported spec and the corresponding ISA
1378 versions. Currently, only Zicsr is supported to verify the
1379 correctness of Z sub extension settings. Others will be supported
1380 in the future patches.
1381 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1382 classes and the corresponding strings.
1383 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1384 spec class by giving a ISA spec string.
1385 * riscv-opc.c (struct priv_spec_t): New structure.
1386 (struct priv_spec_t priv_specs): List for all supported privilege spec
1387 classes and the corresponding strings.
1388 (riscv_get_priv_spec_class): New function. Get the corresponding
1389 privilege spec class by giving a spec string.
1390 (riscv_get_priv_spec_name): New function. Get the corresponding
1391 privilege spec string by giving a CSR version class.
1392 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1393 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1394 according to the chosen version. Build a hash table riscv_csr_hash to
1395 store the valid CSR for the chosen pirv verison. Dump the direct
1396 CSR address rather than it's name if it is invalid.
1397 (parse_riscv_dis_option_without_args): New function. Parse the options
1399 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1400 parse the options without arguments first, and then handle the options
1401 with arguments. Add the new option -Mpriv-spec, which has argument.
1402 * riscv-dis.c (print_riscv_disassembler_options): Add description
1403 about the new OBJDUMP option.
1405 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1407 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1408 WC values on POWER10 sync, dcbf and wait instructions.
1409 (insert_pl, extract_pl): New functions.
1410 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1411 (LS3): New , 3-bit L for sync.
1412 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1413 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1414 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1415 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1416 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1417 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1418 <wait>: Enable PL operand on POWER10.
1419 <dcbf>: Enable L3OPT operand on POWER10.
1420 <sync>: Enable SC2 operand on POWER10.
1422 2020-05-19 Stafford Horne <shorne@gmail.com>
1425 * or1k-asm.c: Regenerate.
1426 * or1k-desc.c: Regenerate.
1427 * or1k-desc.h: Regenerate.
1428 * or1k-dis.c: Regenerate.
1429 * or1k-ibld.c: Regenerate.
1430 * or1k-opc.c: Regenerate.
1431 * or1k-opc.h: Regenerate.
1432 * or1k-opinst.c: Regenerate.
1434 2020-05-11 Alan Modra <amodra@gmail.com>
1436 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1439 2020-05-11 Alan Modra <amodra@gmail.com>
1441 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1442 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1444 2020-05-11 Alan Modra <amodra@gmail.com>
1446 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1448 2020-05-11 Alan Modra <amodra@gmail.com>
1450 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1451 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1453 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1455 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1458 2020-05-11 Alan Modra <amodra@gmail.com>
1460 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1461 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1462 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1463 (prefix_opcodes): Add xxeval.
1465 2020-05-11 Alan Modra <amodra@gmail.com>
1467 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1468 xxgenpcvwm, xxgenpcvdm.
1470 2020-05-11 Alan Modra <amodra@gmail.com>
1472 * ppc-opc.c (MP, VXVAM_MASK): Define.
1473 (VXVAPS_MASK): Use VXVA_MASK.
1474 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1475 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1476 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1477 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1479 2020-05-11 Alan Modra <amodra@gmail.com>
1480 Peter Bergner <bergner@linux.ibm.com>
1482 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1484 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1485 YMSK2, XA6a, XA6ap, XB6a entries.
1486 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1487 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1489 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1490 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1491 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1492 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1493 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1494 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1495 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1496 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1497 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1498 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1499 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1500 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1501 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1502 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1504 2020-05-11 Alan Modra <amodra@gmail.com>
1506 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1507 (insert_xts, extract_xts): New functions.
1508 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1509 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1510 (VXRC_MASK, VXSH_MASK): Define.
1511 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1512 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1513 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1514 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1515 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1516 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1517 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1519 2020-05-11 Alan Modra <amodra@gmail.com>
1521 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1522 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1523 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1524 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1525 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1527 2020-05-11 Alan Modra <amodra@gmail.com>
1529 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1530 (XTP, DQXP, DQXP_MASK): Define.
1531 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1532 (prefix_opcodes): Add plxvp and pstxvp.
1534 2020-05-11 Alan Modra <amodra@gmail.com>
1536 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1537 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1538 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1540 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1542 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1544 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1546 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1548 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1550 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1552 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1554 2020-05-11 Alan Modra <amodra@gmail.com>
1556 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1558 2020-05-11 Alan Modra <amodra@gmail.com>
1560 * ppc-dis.c (ppc_opts): Add "power10" entry.
1561 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1562 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1564 2020-05-11 Nick Clifton <nickc@redhat.com>
1566 * po/fr.po: Updated French translation.
1568 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1570 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1571 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1572 (operand_general_constraint_met_p): validate
1573 AARCH64_OPND_UNDEFINED.
1574 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1576 * aarch64-asm-2.c: Regenerated.
1577 * aarch64-dis-2.c: Regenerated.
1578 * aarch64-opc-2.c: Regenerated.
1580 2020-04-29 Nick Clifton <nickc@redhat.com>
1583 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1586 2020-04-29 Nick Clifton <nickc@redhat.com>
1588 * po/sv.po: Updated Swedish translation.
1590 2020-04-29 Nick Clifton <nickc@redhat.com>
1593 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1594 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1595 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1598 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1601 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1602 cmpi only on m68020up and cpu32.
1604 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1606 * aarch64-asm.c (aarch64_ins_none): New.
1607 * aarch64-asm.h (ins_none): New declaration.
1608 * aarch64-dis.c (aarch64_ext_none): New.
1609 * aarch64-dis.h (ext_none): New declaration.
1610 * aarch64-opc.c (aarch64_print_operand): Update case for
1611 AARCH64_OPND_BARRIER_PSB.
1612 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1613 (AARCH64_OPERANDS): Update inserter/extracter for
1614 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1615 * aarch64-asm-2.c: Regenerated.
1616 * aarch64-dis-2.c: Regenerated.
1617 * aarch64-opc-2.c: Regenerated.
1619 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1621 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1622 (aarch64_feature_ras, RAS): Likewise.
1623 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1624 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1625 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1626 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1627 * aarch64-asm-2.c: Regenerated.
1628 * aarch64-dis-2.c: Regenerated.
1629 * aarch64-opc-2.c: Regenerated.
1631 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1633 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1634 (print_insn_neon): Support disassembly of conditional
1637 2020-02-16 David Faust <david.faust@oracle.com>
1639 * bpf-desc.c: Regenerate.
1640 * bpf-desc.h: Likewise.
1641 * bpf-opc.c: Regenerate.
1642 * bpf-opc.h: Likewise.
1644 2020-04-07 Lili Cui <lili.cui@intel.com>
1646 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1647 (prefix_table): New instructions (see prefixes above).
1648 (rm_table): Likewise
1649 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1650 CPU_ANY_TSXLDTRK_FLAGS.
1651 (cpu_flags): Add CpuTSXLDTRK.
1652 * i386-opc.h (enum): Add CpuTSXLDTRK.
1653 (i386_cpu_flags): Add cputsxldtrk.
1654 * i386-opc.tbl: Add XSUSPLDTRK insns.
1655 * i386-init.h: Regenerate.
1656 * i386-tbl.h: Likewise.
1658 2020-04-02 Lili Cui <lili.cui@intel.com>
1660 * i386-dis.c (prefix_table): New instructions serialize.
1661 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1662 CPU_ANY_SERIALIZE_FLAGS.
1663 (cpu_flags): Add CpuSERIALIZE.
1664 * i386-opc.h (enum): Add CpuSERIALIZE.
1665 (i386_cpu_flags): Add cpuserialize.
1666 * i386-opc.tbl: Add SERIALIZE insns.
1667 * i386-init.h: Regenerate.
1668 * i386-tbl.h: Likewise.
1670 2020-03-26 Alan Modra <amodra@gmail.com>
1672 * disassemble.h (opcodes_assert): Declare.
1673 (OPCODES_ASSERT): Define.
1674 * disassemble.c: Don't include assert.h. Include opintl.h.
1675 (opcodes_assert): New function.
1676 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1677 (bfd_h8_disassemble): Reduce size of data array. Correctly
1678 calculate maxlen. Omit insn decoding when insn length exceeds
1679 maxlen. Exit from nibble loop when looking for E, before
1680 accessing next data byte. Move processing of E outside loop.
1681 Replace tests of maxlen in loop with assertions.
1683 2020-03-26 Alan Modra <amodra@gmail.com>
1685 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1687 2020-03-25 Alan Modra <amodra@gmail.com>
1689 * z80-dis.c (suffix): Init mybuf.
1691 2020-03-22 Alan Modra <amodra@gmail.com>
1693 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1694 successflly read from section.
1696 2020-03-22 Alan Modra <amodra@gmail.com>
1698 * arc-dis.c (find_format): Use ISO C string concatenation rather
1699 than line continuation within a string. Don't access needs_limm
1700 before testing opcode != NULL.
1702 2020-03-22 Alan Modra <amodra@gmail.com>
1704 * ns32k-dis.c (print_insn_arg): Update comment.
1705 (print_insn_ns32k): Reduce size of index_offset array, and
1706 initialize, passing -1 to print_insn_arg for args that are not
1707 an index. Don't exit arg loop early. Abort on bad arg number.
1709 2020-03-22 Alan Modra <amodra@gmail.com>
1711 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1712 * s12z-opc.c: Formatting.
1713 (operands_f): Return an int.
1714 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1715 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1716 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1717 (exg_sex_discrim): Likewise.
1718 (create_immediate_operand, create_bitfield_operand),
1719 (create_register_operand_with_size, create_register_all_operand),
1720 (create_register_all16_operand, create_simple_memory_operand),
1721 (create_memory_operand, create_memory_auto_operand): Don't
1722 segfault on malloc failure.
1723 (z_ext24_decode): Return an int status, negative on fail, zero
1725 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1726 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1727 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1728 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1729 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1730 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1731 (loop_primitive_decode, shift_decode, psh_pul_decode),
1732 (bit_field_decode): Similarly.
1733 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1734 to return value, update callers.
1735 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1736 Don't segfault on NULL operand.
1737 (decode_operation): Return OP_INVALID on first fail.
1738 (decode_s12z): Check all reads, returning -1 on fail.
1740 2020-03-20 Alan Modra <amodra@gmail.com>
1742 * metag-dis.c (print_insn_metag): Don't ignore status from
1745 2020-03-20 Alan Modra <amodra@gmail.com>
1747 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1748 Initialize parts of buffer not written when handling a possible
1749 2-byte insn at end of section. Don't attempt decoding of such
1750 an insn by the 4-byte machinery.
1752 2020-03-20 Alan Modra <amodra@gmail.com>
1754 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1755 partially filled buffer. Prevent lookup of 4-byte insns when
1756 only VLE 2-byte insns are possible due to section size. Print
1757 ".word" rather than ".long" for 2-byte leftovers.
1759 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1762 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1764 2020-03-13 Jan Beulich <jbeulich@suse.com>
1766 * i386-dis.c (X86_64_0D): Rename to ...
1767 (X86_64_0E): ... this.
1769 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1771 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1772 * Makefile.in: Regenerated.
1774 2020-03-09 Jan Beulich <jbeulich@suse.com>
1776 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1778 * i386-tbl.h: Re-generate.
1780 2020-03-09 Jan Beulich <jbeulich@suse.com>
1782 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1783 vprot*, vpsha*, and vpshl*.
1784 * i386-tbl.h: Re-generate.
1786 2020-03-09 Jan Beulich <jbeulich@suse.com>
1788 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1789 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1790 * i386-tbl.h: Re-generate.
1792 2020-03-09 Jan Beulich <jbeulich@suse.com>
1794 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1795 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1796 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1797 * i386-tbl.h: Re-generate.
1799 2020-03-09 Jan Beulich <jbeulich@suse.com>
1801 * i386-gen.c (struct template_arg, struct template_instance,
1802 struct template_param, struct template, templates,
1803 parse_template, expand_templates): New.
1804 (process_i386_opcodes): Various local variables moved to
1805 expand_templates. Call parse_template and expand_templates.
1806 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1807 * i386-tbl.h: Re-generate.
1809 2020-03-06 Jan Beulich <jbeulich@suse.com>
1811 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1812 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1813 register and memory source templates. Replace VexW= by VexW*
1815 * i386-tbl.h: Re-generate.
1817 2020-03-06 Jan Beulich <jbeulich@suse.com>
1819 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1820 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1821 * i386-tbl.h: Re-generate.
1823 2020-03-06 Jan Beulich <jbeulich@suse.com>
1825 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1826 * i386-tbl.h: Re-generate.
1828 2020-03-06 Jan Beulich <jbeulich@suse.com>
1830 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1831 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1832 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1833 VexW0 on SSE2AVX variants.
1834 (vmovq): Drop NoRex64 from XMM/XMM variants.
1835 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1836 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1837 applicable use VexW0.
1838 * i386-tbl.h: Re-generate.
1840 2020-03-06 Jan Beulich <jbeulich@suse.com>
1842 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1843 * i386-opc.h (Rex64): Delete.
1844 (struct i386_opcode_modifier): Remove rex64 field.
1845 * i386-opc.tbl (crc32): Drop Rex64.
1846 Replace Rex64 with Size64 everywhere else.
1847 * i386-tbl.h: Re-generate.
1849 2020-03-06 Jan Beulich <jbeulich@suse.com>
1851 * i386-dis.c (OP_E_memory): Exclude recording of used address
1852 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1853 addressed memory operands for MPX insns.
1855 2020-03-06 Jan Beulich <jbeulich@suse.com>
1857 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1858 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1859 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1860 (ptwrite): Split into non-64-bit and 64-bit forms.
1861 * i386-tbl.h: Re-generate.
1863 2020-03-06 Jan Beulich <jbeulich@suse.com>
1865 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1867 * i386-tbl.h: Re-generate.
1869 2020-03-04 Jan Beulich <jbeulich@suse.com>
1871 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1872 (prefix_table): Move vmmcall here. Add vmgexit.
1873 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1874 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1875 (cpu_flags): Add CpuSEV_ES entry.
1876 * i386-opc.h (CpuSEV_ES): New.
1877 (union i386_cpu_flags): Add cpusev_es field.
1878 * i386-opc.tbl (vmgexit): New.
1879 * i386-init.h, i386-tbl.h: Re-generate.
1881 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1883 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1885 * i386-opc.h (IGNORESIZE): New.
1886 (DEFAULTSIZE): Likewise.
1887 (IgnoreSize): Removed.
1888 (DefaultSize): Likewise.
1889 (MnemonicSize): New.
1890 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1892 * i386-opc.tbl (IgnoreSize): New.
1893 (DefaultSize): Likewise.
1894 * i386-tbl.h: Regenerated.
1896 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1899 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1902 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1905 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1906 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1907 * i386-tbl.h: Regenerated.
1909 2020-02-26 Alan Modra <amodra@gmail.com>
1911 * aarch64-asm.c: Indent labels correctly.
1912 * aarch64-dis.c: Likewise.
1913 * aarch64-gen.c: Likewise.
1914 * aarch64-opc.c: Likewise.
1915 * alpha-dis.c: Likewise.
1916 * i386-dis.c: Likewise.
1917 * nds32-asm.c: Likewise.
1918 * nfp-dis.c: Likewise.
1919 * visium-dis.c: Likewise.
1921 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1923 * arc-regs.h (int_vector_base): Make it available for all ARC
1926 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
1928 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1931 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
1933 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1934 c.mv/c.li if rs1 is zero.
1936 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1938 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1939 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1941 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1942 * i386-opc.h (CpuABM): Removed.
1944 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1945 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1946 popcnt. Remove CpuABM from lzcnt.
1947 * i386-init.h: Regenerated.
1948 * i386-tbl.h: Likewise.
1950 2020-02-17 Jan Beulich <jbeulich@suse.com>
1952 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1953 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1954 VexW1 instead of open-coding them.
1955 * i386-tbl.h: Re-generate.
1957 2020-02-17 Jan Beulich <jbeulich@suse.com>
1959 * i386-opc.tbl (AddrPrefixOpReg): Define.
1960 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1961 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1962 templates. Drop NoRex64.
1963 * i386-tbl.h: Re-generate.
1965 2020-02-17 Jan Beulich <jbeulich@suse.com>
1968 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1969 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1970 into Intel syntax instance (with Unpsecified) and AT&T one
1972 (vcvtneps2bf16): Likewise, along with folding the two so far
1974 * i386-tbl.h: Re-generate.
1976 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1978 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1979 CPU_ANY_SSE4A_FLAGS.
1981 2020-02-17 Alan Modra <amodra@gmail.com>
1983 * i386-gen.c (cpu_flag_init): Correct last change.
1985 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1987 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1990 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1992 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1995 2020-02-14 Jan Beulich <jbeulich@suse.com>
1998 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1999 destination for Cpu64-only variant.
2000 (movzx): Fold patterns.
2001 * i386-tbl.h: Re-generate.
2003 2020-02-13 Jan Beulich <jbeulich@suse.com>
2005 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2006 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2007 CPU_ANY_SSE4_FLAGS entry.
2008 * i386-init.h: Re-generate.
2010 2020-02-12 Jan Beulich <jbeulich@suse.com>
2012 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2013 with Unspecified, making the present one AT&T syntax only.
2014 * i386-tbl.h: Re-generate.
2016 2020-02-12 Jan Beulich <jbeulich@suse.com>
2018 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2019 * i386-tbl.h: Re-generate.
2021 2020-02-12 Jan Beulich <jbeulich@suse.com>
2024 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2025 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2026 Amd64 and Intel64 templates.
2027 (call, jmp): Likewise for far indirect variants. Dro
2029 * i386-tbl.h: Re-generate.
2031 2020-02-11 Jan Beulich <jbeulich@suse.com>
2033 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2034 * i386-opc.h (ShortForm): Delete.
2035 (struct i386_opcode_modifier): Remove shortform field.
2036 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2037 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2038 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2039 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2041 * i386-tbl.h: Re-generate.
2043 2020-02-11 Jan Beulich <jbeulich@suse.com>
2045 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2046 fucompi): Drop ShortForm from operand-less templates.
2047 * i386-tbl.h: Re-generate.
2049 2020-02-11 Alan Modra <amodra@gmail.com>
2051 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2052 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2053 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2054 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2055 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2057 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2059 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2060 (cde_opcodes): Add VCX* instructions.
2062 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2063 Matthew Malcomson <matthew.malcomson@arm.com>
2065 * arm-dis.c (struct cdeopcode32): New.
2066 (CDE_OPCODE): New macro.
2067 (cde_opcodes): New disassembly table.
2068 (regnames): New option to table.
2069 (cde_coprocs): New global variable.
2070 (print_insn_cde): New
2071 (print_insn_thumb32): Use print_insn_cde.
2072 (parse_arm_disassembler_options): Parse coprocN args.
2074 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2077 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2079 * i386-opc.h (AMD64): Removed.
2080 (Intel64): Likewose.
2082 (INTEL64): Likewise.
2083 (INTEL64ONLY): Likewise.
2084 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2085 * i386-opc.tbl (Amd64): New.
2086 (Intel64): Likewise.
2087 (Intel64Only): Likewise.
2088 Replace AMD64 with Amd64. Update sysenter/sysenter with
2089 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2090 * i386-tbl.h: Regenerated.
2092 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2095 * z80-dis.c: Add support for GBZ80 opcodes.
2097 2020-02-04 Alan Modra <amodra@gmail.com>
2099 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2101 2020-02-03 Alan Modra <amodra@gmail.com>
2103 * m32c-ibld.c: Regenerate.
2105 2020-02-01 Alan Modra <amodra@gmail.com>
2107 * frv-ibld.c: Regenerate.
2109 2020-01-31 Jan Beulich <jbeulich@suse.com>
2111 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2112 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2113 (OP_E_memory): Replace xmm_mdq_mode case label by
2114 vex_scalar_w_dq_mode one.
2115 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2117 2020-01-31 Jan Beulich <jbeulich@suse.com>
2119 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2120 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2121 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2122 (intel_operand_size): Drop vex_w_dq_mode case label.
2124 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2126 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2127 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2129 2020-01-30 Alan Modra <amodra@gmail.com>
2131 * m32c-ibld.c: Regenerate.
2133 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2135 * bpf-opc.c: Regenerate.
2137 2020-01-30 Jan Beulich <jbeulich@suse.com>
2139 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2140 (dis386): Use them to replace C2/C3 table entries.
2141 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2142 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2143 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2144 * i386-tbl.h: Re-generate.
2146 2020-01-30 Jan Beulich <jbeulich@suse.com>
2148 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2150 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2152 * i386-tbl.h: Re-generate.
2154 2020-01-30 Alan Modra <amodra@gmail.com>
2156 * tic4x-dis.c (tic4x_dp): Make unsigned.
2158 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2159 Jan Beulich <jbeulich@suse.com>
2162 * i386-dis.c (MOVSXD_Fixup): New function.
2163 (movsxd_mode): New enum.
2164 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2165 (intel_operand_size): Handle movsxd_mode.
2166 (OP_E_register): Likewise.
2168 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2169 register on movsxd. Add movsxd with 16-bit destination register
2170 for AMD64 and Intel64 ISAs.
2171 * i386-tbl.h: Regenerated.
2173 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2176 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2177 * aarch64-asm-2.c: Regenerate
2178 * aarch64-dis-2.c: Likewise.
2179 * aarch64-opc-2.c: Likewise.
2181 2020-01-21 Jan Beulich <jbeulich@suse.com>
2183 * i386-opc.tbl (sysret): Drop DefaultSize.
2184 * i386-tbl.h: Re-generate.
2186 2020-01-21 Jan Beulich <jbeulich@suse.com>
2188 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2190 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2191 * i386-tbl.h: Re-generate.
2193 2020-01-20 Nick Clifton <nickc@redhat.com>
2195 * po/de.po: Updated German translation.
2196 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2197 * po/uk.po: Updated Ukranian translation.
2199 2020-01-20 Alan Modra <amodra@gmail.com>
2201 * hppa-dis.c (fput_const): Remove useless cast.
2203 2020-01-20 Alan Modra <amodra@gmail.com>
2205 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2207 2020-01-18 Nick Clifton <nickc@redhat.com>
2209 * configure: Regenerate.
2210 * po/opcodes.pot: Regenerate.
2212 2020-01-18 Nick Clifton <nickc@redhat.com>
2214 Binutils 2.34 branch created.
2216 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2218 * opintl.h: Fix spelling error (seperate).
2220 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2222 * i386-opc.tbl: Add {vex} pseudo prefix.
2223 * i386-tbl.h: Regenerated.
2225 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2228 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2229 (neon_opcodes): Likewise.
2230 (select_arm_features): Make sure we enable MVE bits when selecting
2231 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2234 2020-01-16 Jan Beulich <jbeulich@suse.com>
2236 * i386-opc.tbl: Drop stale comment from XOP section.
2238 2020-01-16 Jan Beulich <jbeulich@suse.com>
2240 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2241 (extractps): Add VexWIG to SSE2AVX forms.
2242 * i386-tbl.h: Re-generate.
2244 2020-01-16 Jan Beulich <jbeulich@suse.com>
2246 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2247 Size64 from and use VexW1 on SSE2AVX forms.
2248 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2249 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2250 * i386-tbl.h: Re-generate.
2252 2020-01-15 Alan Modra <amodra@gmail.com>
2254 * tic4x-dis.c (tic4x_version): Make unsigned long.
2255 (optab, optab_special, registernames): New file scope vars.
2256 (tic4x_print_register): Set up registernames rather than
2257 malloc'd registertable.
2258 (tic4x_disassemble): Delete optable and optable_special. Use
2259 optab and optab_special instead. Throw away old optab,
2260 optab_special and registernames when info->mach changes.
2262 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2265 * z80-dis.c (suffix): Use .db instruction to generate double
2268 2020-01-14 Alan Modra <amodra@gmail.com>
2270 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2271 values to unsigned before shifting.
2273 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2275 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2277 (print_insn_thumb16, print_insn_thumb32): Likewise.
2278 (print_insn): Initialize the insn info.
2279 * i386-dis.c (print_insn): Initialize the insn info fields, and
2282 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2284 * arc-opc.c (C_NE): Make it required.
2286 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2288 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2289 reserved register name.
2291 2020-01-13 Alan Modra <amodra@gmail.com>
2293 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2294 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2296 2020-01-13 Alan Modra <amodra@gmail.com>
2298 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2299 result of wasm_read_leb128 in a uint64_t and check that bits
2300 are not lost when copying to other locals. Use uint32_t for
2301 most locals. Use PRId64 when printing int64_t.
2303 2020-01-13 Alan Modra <amodra@gmail.com>
2305 * score-dis.c: Formatting.
2306 * score7-dis.c: Formatting.
2308 2020-01-13 Alan Modra <amodra@gmail.com>
2310 * score-dis.c (print_insn_score48): Use unsigned variables for
2311 unsigned values. Don't left shift negative values.
2312 (print_insn_score32): Likewise.
2313 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2315 2020-01-13 Alan Modra <amodra@gmail.com>
2317 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2319 2020-01-13 Alan Modra <amodra@gmail.com>
2321 * fr30-ibld.c: Regenerate.
2323 2020-01-13 Alan Modra <amodra@gmail.com>
2325 * xgate-dis.c (print_insn): Don't left shift signed value.
2326 (ripBits): Formatting, use 1u.
2328 2020-01-10 Alan Modra <amodra@gmail.com>
2330 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2331 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2333 2020-01-10 Alan Modra <amodra@gmail.com>
2335 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2336 and XRREG value earlier to avoid a shift with negative exponent.
2337 * m10200-dis.c (disassemble): Similarly.
2339 2020-01-09 Nick Clifton <nickc@redhat.com>
2342 * z80-dis.c (ld_ii_ii): Use correct cast.
2344 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2347 * z80-dis.c (ld_ii_ii): Use character constant when checking
2350 2020-01-09 Jan Beulich <jbeulich@suse.com>
2352 * i386-dis.c (SEP_Fixup): New.
2354 (dis386_twobyte): Use it for sysenter/sysexit.
2355 (enum x86_64_isa): Change amd64 enumerator to value 1.
2356 (OP_J): Compare isa64 against intel64 instead of amd64.
2357 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2359 * i386-tbl.h: Re-generate.
2361 2020-01-08 Alan Modra <amodra@gmail.com>
2363 * z8k-dis.c: Include libiberty.h
2364 (instr_data_s): Make max_fetched unsigned.
2365 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2366 Don't exceed byte_info bounds.
2367 (output_instr): Make num_bytes unsigned.
2368 (unpack_instr): Likewise for nibl_count and loop.
2369 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2371 * z8k-opc.h: Regenerate.
2373 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2375 * arc-tbl.h (llock): Use 'LLOCK' as class.
2377 (scond): Use 'SCOND' as class.
2379 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2382 2020-01-06 Alan Modra <amodra@gmail.com>
2384 * m32c-ibld.c: Regenerate.
2386 2020-01-06 Alan Modra <amodra@gmail.com>
2389 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2390 Peek at next byte to prevent recursion on repeated prefix bytes.
2391 Ensure uninitialised "mybuf" is not accessed.
2392 (print_insn_z80): Don't zero n_fetch and n_used here,..
2393 (print_insn_z80_buf): ..do it here instead.
2395 2020-01-04 Alan Modra <amodra@gmail.com>
2397 * m32r-ibld.c: Regenerate.
2399 2020-01-04 Alan Modra <amodra@gmail.com>
2401 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2403 2020-01-04 Alan Modra <amodra@gmail.com>
2405 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2407 2020-01-04 Alan Modra <amodra@gmail.com>
2409 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2411 2020-01-03 Jan Beulich <jbeulich@suse.com>
2413 * aarch64-tbl.h (aarch64_opcode_table): Use
2414 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2416 2020-01-03 Jan Beulich <jbeulich@suse.com>
2418 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2419 forms of SUDOT and USDOT.
2421 2020-01-03 Jan Beulich <jbeulich@suse.com>
2423 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2425 * opcodes/aarch64-dis-2.c: Re-generate.
2427 2020-01-03 Jan Beulich <jbeulich@suse.com>
2429 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2431 * opcodes/aarch64-dis-2.c: Re-generate.
2433 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2435 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2437 2020-01-01 Alan Modra <amodra@gmail.com>
2439 Update year range in copyright notice of all files.
2441 For older changes see ChangeLog-2019
2443 Copyright (C) 2020 Free Software Foundation, Inc.
2445 Copying and distribution of this file, with or without modification,
2446 are permitted in any medium without royalty provided the copyright
2447 notice and this notice are preserved.
2453 version-control: never
projects / deliverable / binutils-gdb.git / blob