opcodes/ChangeLog

   1 2005-01-31  Andrew Cagney  <cagney@gnu.org>
   2
   3         * configure: Regenerate to track ../gettext.m4.
   4
   5 2005-01-31  Jan Beulich  <jbeulich@novell.com>
   6
   7         * ia64-gen.c (NELEMS): Define.
   8         (shrink): Generate alias with missing second predicate register when
   9         opcode has two outputs and these are both predicates.
  10         * ia64-opc-i.c (FULL17): Define.
  11         (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
  12         here to generate output template.
  13         (TBITCM, TNATCM): Undefine after use.
  14         * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
  15         first input. Add ld16 aliases without ar.csd as second output. Add
  16         st16 aliases without ar.csd as second input. Add cmpxchg aliases
  17         without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
  18         ar.ccv as third/fourth inputs. Consolidate through...
  19         (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
  20         CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
  21         * ia64-asmtab.c: Regenerate.
  22
  23 2005-01-27  Andrew Cagney  <cagney@gnu.org>
  24
  25         * configure: Regenerate to track ../gettext.m4 change.
  26
  27 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  28
  29         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  30         * frv-asm.c: Rebuilt.
  31         * frv-desc.c: Rebuilt.
  32         * frv-desc.h: Rebuilt.
  33         * frv-dis.c: Rebuilt.
  34         * frv-ibld.c: Rebuilt.
  35         * frv-opc.c: Rebuilt.
  36         * frv-opc.h: Rebuilt.
  37
  38 2005-01-24  Andrew Cagney  <cagney@gnu.org>
  39
  40         * configure: Regenerate, ../gettext.m4 was updated.
  41
  42 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  43
  44         * mips-opc.c:  Change INSN_ALIAS to INSN2_ALIAS.
  45         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  46         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  47         * mips-dis.c: Ditto.
  48
  49 2005-01-20  Alan Modra  <amodra@bigpond.net.au>
  50
  51         * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
  52
  53 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  54
  55         * mips-dis.c (no_aliases): New disassembly option flag.
  56         (set_default_mips_dis_options): Init no_aliases to zero.
  57         (parse_mips_dis_option): Handle no-aliases option.
  58         (print_insn_mips): Ignore table entries that are aliases
  59         if no_aliases is set.
  60         (print_insn_mips16): Ditto.
  61         * mips-opc.c (mips_builtin_opcodes): Add initializer column for
  62         new pinfo2 member and add INSN_ALIAS initializers as needed.  Also
  63         move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
  64         * mips16-opc.c (mips16_opcodes): Ditto.
  65
  66 2005-01-17  Andrew Stubbs  <andrew.stubbs@st.com>
  67
  68         * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
  69         (inheritance diagram): Add missing edge.
  70         (arch_sh1_up): Rename arch_sh_up to match external name to make life
  71         easier for the testsuite.
  72         (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
  73         (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
  74         (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
  75         arch_sh2a_or_sh4_up child.
  76         (sh_table): Do renaming as above.
  77         Correct comment for ldc.l for gas testsuite to read.
  78         Remove rogue mul.l from sh1 (duplicate of the one for sh2).
  79         Correct comments for movy.w and movy.l for gas testsuite to read.
  80         Correct comments for fmov.d and fmov.s for gas testsuite to read.
  81
  82 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
  83
  84         * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
  85
  86 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
  87
  88         * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
  89
  90 2005-01-10  Andreas Schwab  <schwab@suse.de>
  91
  92         * disassemble.c (disassemble_init_for_target) <case
  93         bfd_arch_ia64>: Set skip_zeroes to 16.
  94         <case bfd_arch_tic4x>: Set skip_zeroes to 32.
  95
  96 2004-12-23  Tomer Levi  <Tomer.Levi@nsc.com>
  97
  98         * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
  99
 100 2004-12-14  Svein E. Seldal  <Svein.Seldal@solidas.com>
 101
 102         * avr-dis.c: Prettyprint. Added printing of symbol names in all
 103         memory references. Convert avr_operand() to C90 formatting.
 104
 105 2004-12-05  Tomer Levi  <Tomer.Levi@nsc.com>
 106
 107         * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
 108
 109 2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 110
 111         * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
 112         (no_op_insn): Initialize array with instructions that have no
 113         operands.
 114         * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
 115
 116 2004-11-29  Richard Earnshaw  <rearnsha@arm.com>
 117
 118         * arm-dis.c: Correct top-level comment.
 119
 120 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
 121
 122         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
 123         architecuture defining the insn.
 124         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
 125         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
 126         field.
 127         Also include opcode/arm.h.
 128         * Makefile.am (arm-dis.lo): Update dependency list.
 129         * Makefile.in: Regenerate.
 130
 131 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
 132
 133         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
 134         reflect the change to the short immediate syntax.
 135
 136 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 137
 138         * or32-opc.c (debug): Warning fix.
 139         * po/POTFILES.in: Regenerate.
 140
 141         * maxq-dis.c: Formatting.
 142         (print_insn): Warning fix.
 143
 144 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
 145
 146         * arm-dis.c (WORD_ADDRESS): Define.
 147         (print_insn): Use it.  Correct big-endian end-of-section handling.
 148
 149 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 150             Vineet Sharma      <vineets@noida.hcltech.com>
 151
 152         * maxq-dis.c: New file.
 153         * disassemble.c (ARCH_maxq): Define.
 154         (disassembler): Add 'print_insn_maxq_little' for handling maxq
 155         instructions..
 156         * configure.in: Add case for bfd_maxq_arch.
 157         * configure: Regenerate.
 158         * Makefile.am: Add support for maxq-dis.c
 159         * Makefile.in: Regenerate.
 160         * aclocal.m4: Regenerate.
 161
 162 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 163
 164         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
 165         mode.
 166         * crx-dis.c: Likewise.
 167
 168 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 169
 170         Generally, handle CRISv32.
 171         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
 172         (struct cris_disasm_data): New type.
 173         (format_reg, format_hex, cris_constraint, print_flags)
 174         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
 175         callers changed.
 176         (format_sup_reg, print_insn_crisv32_with_register_prefix)
 177         (print_insn_crisv32_without_register_prefix)
 178         (print_insn_crisv10_v32_with_register_prefix)
 179         (print_insn_crisv10_v32_without_register_prefix)
 180         (cris_parse_disassembler_options): New functions.
 181         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
 182         parameter.  All callers changed.
 183         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
 184         failure.
 185         (cris_constraint) <case 'Y', 'U'>: New cases.
 186         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
 187         for constraint 'n'.
 188         (print_with_operands) <case 'Y'>: New case.
 189         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
 190         <case 'N', 'Y', 'Q'>: New cases.
 191         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
 192         (print_insn_cris_with_register_prefix)
 193         (print_insn_cris_without_register_prefix): Call
 194         cris_parse_disassembler_options.
 195         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
 196         for CRISv32 and the size of immediate operands.  New v32-only
 197         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
 198         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
 199         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
 200         Change brp to be v3..v10.
 201         (cris_support_regs): New vector.
 202         (cris_opcodes): Update head comment.  New format characters '[',
 203         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
 204         Add new opcodes for v32 and adjust existing opcodes to accommodate
 205         differences to earlier variants.
 206         (cris_cond15s): New vector.
 207
 208 2004-11-04 Jan Beulich <jbeulich@novell.com>
 209
 210         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
 211         (indirEb): Remove.
 212         (Mp): Use f_mode rather than none at all.
 213         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
 214         replaces what previously was x_mode; x_mode now means 128-bit SSE
 215         operands.
 216         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
 217         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
 218         pinsrw's second operand is Edqw.
 219         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 220         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 221         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 222         mode when an operand size override is present or always suffixing.
 223         More instructions will need to be added to this group.
 224         (putop): Handle new macro chars 'C' (short/long suffix selector),
 225         'I' (Intel mode override for following macro char), and 'J' (for
 226         adding the 'l' prefix to far branches in AT&T mode). When an
 227         alternative was specified in the template, honor macro character when
 228         specified for Intel mode.
 229         (OP_E): Handle new *_mode values. Correct pointer specifications for
 230         memory operands. Consolidate output of index register.
 231         (OP_G): Handle new *_mode values.
 232         (OP_I): Handle const_1_mode.
 233         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 234         respective opcode prefix bits have been consumed.
 235         (OP_EM, OP_EX): Provide some default handling for generating pointer
 236         specifications.
 237
 238 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 239
 240         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 241         COP_INST macro.
 242
 243 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 244
 245         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 246         (getregliststring): Support HI/LO and user registers.
 247         * crx-opc.c (crx_instruction): Update data structure according to the
 248         rearrangement done in CRX opcode header file.
 249         (crx_regtab):  Likewise.
 250         (crx_optab):  Likewise.
 251         (crx_instruction): Reorder load/stor instructions, remove unsupported
 252         formats.
 253         support new Co-Processor instruction 'cpi'.
 254
 255 2004-10-27  Nick Clifton  <nickc@redhat.com>
 256
 257         * opcodes/iq2000-asm.c: Regenerate.
 258         * opcodes/iq2000-desc.c: Regenerate.
 259         * opcodes/iq2000-desc.h: Regenerate.
 260         * opcodes/iq2000-dis.c: Regenerate.
 261         * opcodes/iq2000-ibld.c: Regenerate.
 262         * opcodes/iq2000-opc.c: Regenerate.
 263         * opcodes/iq2000-opc.h: Regenerate.
 264
 265 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 266
 267         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 268         us4, us5 (respectively).
 269         Remove unsupported 'popa' instruction.
 270         Reverse operands order in store co-processor instructions.
 271
 272 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 273
 274         * Makefile.am: Run "make dep-am"
 275         * Makefile.in: Regenerate.
 276
 277 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 278
 279         * xtensa-dis.c: Use ISO C90 formatting.
 280
 281 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 282
 283         * ppc-opc.c: Revert 2004-09-09 change.
 284
 285 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 286
 287         * xtensa-dis.c (state_names): Delete.
 288         (fetch_data): Use xtensa_isa_maxlength.
 289         (print_xtensa_operand): Replace operand parameter with opcode/operand
 290         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 291         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 292         instruction bundles.  Use xmalloc instead of malloc.
 293
 294 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 295
 296         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 297         initializers.
 298
 299 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 300
 301         * crx-opc.c (crx_instruction): Support Co-processor insns.
 302         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 303         (getregliststring): Change function to use the above enum.
 304         (print_arg): Handle CO-Processor insns.
 305         (crx_cinvs): Add 'b' option to invalidate the branch-target
 306         cache.
 307
 308 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 309
 310         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 311         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 312         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 313         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 314         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 315
 316 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 317
 318         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 319         rather than add it.
 320
 321 2004-09-30  Paul Brook  <paul@codesourcery.com>
 322
 323         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 324         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 325
 326 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 329         (CONFIG_STATUS_DEPENDENCIES): New.
 330         (Makefile): Removed.
 331         (config.status): Likewise.
 332         * Makefile.in: Regenerated.
 333
 334 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 335
 336         * Makefile.am: Run "make dep-am".
 337         * Makefile.in: Regenerate.
 338         * aclocal.m4: Regenerate.
 339         * configure: Regenerate.
 340         * po/POTFILES.in: Regenerate.
 341         * po/opcodes.pot: Regenerate.
 342
 343 2004-09-11  Andreas Schwab  <schwab@suse.de>
 344
 345         * configure: Rebuild.
 346
 347 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 348
 349         * ppc-opc.c (L): Make this field not optional.
 350
 351 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 352
 353         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 354         Fix parameter to 'm[t|f]csr' insns.
 355
 356 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 357
 358         * configure.in: Autoupdate to autoconf 2.59.
 359         * aclocal.m4: Rebuild with aclocal 1.4p6.
 360         * configure: Rebuild with autoconf 2.59.
 361         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 362         bfd changes for autoconf 2.59 on the way).
 363         * config.in: Rebuild with autoheader 2.59.
 364
 365 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 366
 367         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 368
 369 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 370
 371         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 372         (GRPPADLCK2): New define.
 373         (twobyte_has_modrm): True for 0xA6.
 374         (grps): GRPPADLCK2 for opcode 0xA6.
 375
 376 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 377
 378         Introduce SH2a support.
 379         * sh-opc.h (arch_sh2a_base): Renumber.
 380         (arch_sh2a_nofpu_base): Remove.
 381         (arch_sh_base_mask): Adjust.
 382         (arch_opann_mask): New.
 383         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 384         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 385         (sh_table): Adjust whitespace.
 386         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 387         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 388         instruction list throughout.
 389         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 390         of arch_sh2a in instruction list throughout.
 391         (arch_sh2e_up): Accomodate above changes.
 392         (arch_sh2_up): Ditto.
 393         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 394         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 395         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 396         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 397         * sh-opc.h (arch_sh2a_nofpu): New.
 398         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 399         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 400         instruction.
 401         2004-01-20  DJ Delorie  <dj@redhat.com>
 402         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 403         2003-12-29  DJ Delorie  <dj@redhat.com>
 404         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 405         sh_opcode_info, sh_table): Add sh2a support.
 406         (arch_op32): New, to tag 32-bit opcodes.
 407         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 408         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 409         * sh-opc.h (arch_sh2a): Add.
 410         * sh-dis.c (arch_sh2a): Handle.
 411         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 412
 413 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 414
 415         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 416
 417 2004-07-22  Nick Clifton  <nickc@redhat.com>
 418
 419         PR/280
 420         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 421         insns - this is done by objdump itself.
 422         * h8500-dis.c (print_insn_h8500): Likewise.
 423
 424 2004-07-21  Jan Beulich <jbeulich@novell.com>
 425
 426         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 427         regardless of address size prefix in effect.
 428         (ptr_reg): Size or address registers does not depend on rex64, but
 429         on the presence of an address size override.
 430         (OP_MMX): Use rex.x only for xmm registers.
 431         (OP_EM): Use rex.z only for xmm registers.
 432
 433 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 434
 435         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 436         move/branch operations to the bottom so that VR5400 multimedia
 437         instructions take precedence in disassembly.
 438
 439 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 440
 441         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 442         ISA-specific "break" encoding.
 443
 444 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 445
 446         * arm-opc.h: Fix typo in comment.
 447
 448 2004-07-11  Andreas Schwab  <schwab@suse.de>
 449
 450         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 451
 452 2004-07-09  Andreas Schwab  <schwab@suse.de>
 453
 454         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 455
 456 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 457
 458         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 459         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 460         (crx-dis.lo): New target.
 461         (crx-opc.lo): Likewise.
 462         * Makefile.in: Regenerate.
 463         * configure.in: Handle bfd_crx_arch.
 464         * configure: Regenerate.
 465         * crx-dis.c: New file.
 466         * crx-opc.c: New file.
 467         * disassemble.c (ARCH_crx): Define.
 468         (disassembler): Handle ARCH_crx.
 469
 470 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 471
 472         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 473         * ia64-asmtab.c: Regnerate.
 474
 475 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 476
 477         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 478         (extract_fxm): Don't test dialect.
 479         (XFXFXM_MASK): Include the power4 bit.
 480         (XFXM): Add p4 param.
 481         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 482
 483 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 484
 485         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 486         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 487
 488 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 489
 490         * ppc-opc.c (BH, XLBH_MASK): Define.
 491         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 492
 493 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 494
 495         * i386-dis.c (x_mode): Comment.
 496         (two_source_ops): File scope.
 497         (float_mem): Correct fisttpll and fistpll.
 498         (float_mem_mode): New table.
 499         (dofloat): Use it.
 500         (OP_E): Correct intel mode PTR output.
 501         (ptr_reg): Use open_char and close_char.
 502         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 503         operands.  Set two_source_ops.
 504
 505 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 506
 507         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 508         instead of _raw_size.
 509
 510 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 511
 512         * ia64-gen.c (in_iclass): Handle more postinc st
 513         and ld variants.
 514         * ia64-asmtab.c: Rebuilt.
 515
 516 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 517
 518         * s390-opc.txt: Correct architecture mask for some opcodes.
 519         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 520         in the esa mode as well.
 521
 522 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 523
 524         * sh-dis.c (target_arch): Make unsigned.
 525         (print_insn_sh): Replace (most of) switch with a call to
 526         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 527         * sh-opc.h: Redefine architecture flags values.
 528         Add sh3-nommu architecture.
 529         Reorganise <arch>_up macros so they make more visual sense.
 530         (SH_MERGE_ARCH_SET): Define new macro.
 531         (SH_VALID_BASE_ARCH_SET): Likewise.
 532         (SH_VALID_MMU_ARCH_SET): Likewise.
 533         (SH_VALID_CO_ARCH_SET): Likewise.
 534         (SH_VALID_ARCH_SET): Likewise.
 535         (SH_MERGE_ARCH_SET_VALID): Likewise.
 536         (SH_ARCH_SET_HAS_FPU): Likewise.
 537         (SH_ARCH_SET_HAS_DSP): Likewise.
 538         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 539         (sh_get_arch_from_bfd_mach): Add prototype.
 540         (sh_get_arch_up_from_bfd_mach): Likewise.
 541         (sh_get_bfd_mach_from_arch_set): Likewise.
 542         (sh_merge_bfd_arc): Likewise.
 543
 544 2004-05-24  Peter Barada  <peter@the-baradas.com>
 545
 546         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 547         into new match_insn_m68k function.  Loop over canidate
 548         matches and select first that completely matches.
 549         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 550         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 551         to verify addressing for MAC/EMAC.
 552         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 553         reigster halves since 'fpu' and 'spl' look misleading.
 554         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 555         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 556         first, tighten up match masks.
 557         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 558         'size' from special case code in print_insn_m68k to
 559         determine decode size of insns.
 560
 561 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 562
 563         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 564         well as when -mpower4.
 565
 566 2004-05-13  Nick Clifton  <nickc@redhat.com>
 567
 568         * po/fr.po: Updated French translation.
 569
 570 2004-05-05  Peter Barada  <peter@the-baradas.com>
 571
 572         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 573         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 574         * m68k-op.c: Switch from ColdFire chips to core variants.
 575
 576 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 577
 578         PR 147.
 579         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 580
 581 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 582
 583         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 584         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 585
 586 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 587
 588         * sh-dis.c (print_insn_sh): Print the value in constant pool
 589         as a symbol if it looks like a symbol.
 590
 591 2004-04-22  Peter Barada <peter@the-baradas.com>
 592
 593         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 594         appropriate ColdFire architectures.
 595         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 596         mask addressing.
 597         Add EMAC instructions, fix MAC instructions. Remove
 598         macmw/macml/msacmw/msacml instructions since mask addressing now
 599         supported.
 600
 601 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 602
 603         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 604         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 605         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 606         macro.  Adjust all users.
 607
 608 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 609
 610         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 611         separately.
 612
 613 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 614
 615         * m32r-asm.c: Regenerate.
 616
 617 2004-03-29  Stan Shebs  <shebs@apple.com>
 618
 619         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 620         used.
 621
 622 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 623
 624         * aclocal.m4: Regenerate.
 625         * config.in: Regenerate.
 626         * configure: Regenerate.
 627         * po/POTFILES.in: Regenerate.
 628         * po/opcodes.pot: Regenerate.
 629
 630 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 631
 632         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 633         PPC_OPERANDS_GPR_0.
 634         * ppc-opc.c (RA0): Define.
 635         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 636         (RAOPT): Rename from RAO.  Update all uses.
 637         (powerpc_opcodes): Use RA0 as appropriate.
 638
 639 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 640
 641         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 642
 643 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 644
 645         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 646
 647 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 648
 649         * i386-dis.c (GRPPLOCK): Delete.
 650         (grps): Delete GRPPLOCK entry.
 651
 652 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 653
 654         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 655         (M, Mp): Use OP_M.
 656         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 657         (GRPPADLCK): Define.
 658         (dis386): Use NOP_Fixup on "nop".
 659         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 660         (twobyte_has_modrm): Set for 0xa7.
 661         (padlock_table): Delete.  Move to..
 662         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 663         and clflush.
 664         (print_insn): Revert PADLOCK_SPECIAL code.
 665         (OP_E): Delete sfence, lfence, mfence checks.
 666
 667 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 668
 669         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 670         (INVLPG_Fixup): New function.
 671         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 672
 673 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 674
 675         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 676         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 677         (padlock_table): New struct with PadLock instructions.
 678         (print_insn): Handle PADLOCK_SPECIAL.
 679
 680 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 681
 682         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 683         (OP_E): Twiddle clflush to sfence here.
 684
 685 2004-03-08  Nick Clifton  <nickc@redhat.com>
 686
 687         * po/de.po: Updated German translation.
 688
 689 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 690
 691         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 692         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 693         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 694         accordingly.
 695
 696 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 697
 698         * frv-asm.c: Regenerate.
 699         * frv-desc.c: Regenerate.
 700         * frv-desc.h: Regenerate.
 701         * frv-dis.c: Regenerate.
 702         * frv-ibld.c: Regenerate.
 703         * frv-opc.c: Regenerate.
 704         * frv-opc.h: Regenerate.
 705
 706 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 707
 708         * frv-desc.c, frv-opc.c: Regenerate.
 709
 710 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 711
 712         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 713
 714 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 715
 716         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 717         Also correct mistake in the comment.
 718
 719 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 720
 721         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 722         ensure that double registers have even numbers.
 723         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 724         that reserved instruction 0xfffd does not decode the same
 725         as 0xfdfd (ftrv).
 726         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 727         REG_N refers to a double register.
 728         Add REG_N_B01 nibble type and use it instead of REG_NM
 729         in ftrv.
 730         Adjust the bit patterns in a few comments.
 731
 732 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 733
 734         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 735
 736 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 737
 738         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 739
 740 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 741
 742         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 743
 744 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 745
 746         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 747         mtivor32, mtivor33, mtivor34.
 748
 749 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 750
 751         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 752
 753 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 754
 755         * arm-opc.h Maverick accumulator register opcode fixes.
 756
 757 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 758
 759         * m32r-dis.c: Regenerate.
 760
 761 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 762
 763         * sh-opc.h (sh_table): "fsrra", not "fssra".
 764
 765 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 766
 767         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 768         contraints.
 769
 770 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 771
 772         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 773
 774 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 775
 776         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 777         1.  Don't print scale factor on AT&T mode when index missing.
 778
 779 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 780
 781         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 782         when loaded into XR registers.
 783
 784 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 785
 786         * frv-desc.h: Regenerate.
 787         * frv-desc.c: Regenerate.
 788         * frv-opc.c: Regenerate.
 789
 790 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 791
 792         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 793
 794 2004-01-09  Paul Brook  <paul@codesourcery.com>
 795
 796         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 797         specific opcodes.
 798
 799 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 800
 801         * Makefile.am (libopcodes_la_DEPENDENCIES)
 802         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 803         comment about the problem.
 804         * Makefile.in: Regenerate.
 805
 806 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 807
 808         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 809         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 810         cut&paste errors in shifting/truncating numerical operands.
 811         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 812         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 813         (parse_uslo16): Likewise.
 814         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 815         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 816         (parse_s12): Likewise.
 817         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 818         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 819         (parse_uslo16): Likewise.
 820         (parse_uhi16): Parse gothi and gotfuncdeschi.
 821         (parse_d12): Parse got12 and gotfuncdesc12.
 822         (parse_s12): Likewise.
 823
 824 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 825
 826         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 827         instruction which looks similar to an 'rla' instruction.
 828
 829 For older changes see ChangeLog-0203
 830 \f
 831 Local Variables:
 832 mode: change-log
 833 left-margin: 8
 834 fill-column: 74
 835 version-control: never
 836 End: