opcodes/ChangeLog

   1 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
   4         (aarch64_sys_ins_reg_supported_p): New.
   5
   6 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
   7
   8         * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
   9         with aarch64_sys_ins_reg_has_xt.
  10         (aarch64_ext_sysins_op): Likewise.
  11         * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
  12         (F_HASXT): New.
  13         (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
  14         (aarch64_sys_regs_dc): Likewise.
  15         (aarch64_sys_regs_at): Likewise.
  16         (aarch64_sys_regs_tlbi): Likewise.
  17         (aarch64_sys_ins_reg_has_xt): New.
  18
  19 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  20
  21         * aarch64-opc.c (aarch64_sys_regs): Add "uao".
  22         (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
  23         (aarch64_pstatefields): Add "uao".
  24         (aarch64_pstatefield_supported_p): Add checks for "uao".
  25
  26 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  27
  28         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
  29         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
  30         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
  31         (aarch64_sys_reg_supported_p): Add architecture feature tests for
  32         new registers.
  33
  34 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  35
  36         * aarch64-asm-2.c: Regenerate.
  37         * aarch64-dis-2.c: Regenerate.
  38         * aarch64-tbl.h (aarch64_feature_ras): New.
  39         (RAS): New.
  40         (aarch64_opcode_table): Add "esb".
  41
  42 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         * i386-dis.c (MOD_0F01_REG_5): New.
  45         (RM_0F01_REG_5): Likewise.
  46         (reg_table): Use MOD_0F01_REG_5.
  47         (mod_table): Add MOD_0F01_REG_5.
  48         (rm_table): Add RM_0F01_REG_5.
  49         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
  50         (cpu_flags): Add CpuOSPKE.
  51         * i386-opc.h (CpuOSPKE): New.
  52         (i386_cpu_flags): Add cpuospke.
  53         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
  54         * i386-init.h: Regenerated.
  55         * i386-tbl.h: Likewise.
  56
  57 2015-12-07  DJ Delorie  <dj@redhat.com>
  58
  59         * rl78-decode.opc: Enable MULU for all ISAs.
  60         * rl78-decode.c: Regenerate.
  61
  62 2015-12-07  Alan Modra  <amodra@gmail.com>
  63
  64         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
  65         major opcode/xop.
  66
  67 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
  68
  69         * arc-dis.c (special_flag_p): Match full mnemonic.
  70         * arc-opc.c (print_insn_arc): Check section size to read
  71         appropriate number of bytes. Fix printing.
  72         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
  73         arguments.
  74
  75 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  76
  77         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
  78         <ldah>: ... to this.
  79
  80 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  81
  82         * aarch64-asm-2.c: Regenerate.
  83         * aarch64-dis-2.c: Regenerate.
  84         * aarch64-opc-2.c: Regenerate.
  85         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
  86         (QL_INT2FP_H, QL_FP2INT_H): New.
  87         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
  88         (QL_DST_H): New.
  89         (QL_FCCMP_H): New.
  90         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
  91         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
  92         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
  93         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
  94         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
  95         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
  96         fcsel.
  97
  98 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  99
 100         * aarch64-opc.c (half_conv_t): New.
 101         (expand_fp_imm): Replace is_dp flag with the parameter size to
 102         specify the number of bytes for the required expansion.  Treat
 103         a 16-bit expansion like a 32-bit expansion.  Add check for an
 104         unsupported size request.  Update comment.
 105         (aarch64_print_operand): Update to support 16-bit floating point
 106         values.  Update for changes to expand_fp_imm.
 107
 108 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 109
 110         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
 111         (FP_F16): New.
 112
 113 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 114
 115         * aarch64-asm-2.c: Regenerate.
 116         * aarch64-dis-2.c: Regenerate.
 117         * aarch64-opc-2.c: Regenerate.
 118         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
 119         "rev64".
 120
 121 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 122
 123         * aarch64-asm-2.c: Regenerate.
 124         * aarch64-asm.c (convert_bfc_to_bfm): New.
 125         (convert_to_real): Add case for OP_BFC.
 126         * aarch64-dis-2.c: Regenerate.
 127         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 128         (convert_to_alias): Add case for OP_BFC.
 129         * aarch64-opc-2.c: Regenerate.
 130         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 131         to allow width operand in three-operand instructions.
 132         * aarch64-tbl.h (QL_BF1): New.
 133         (aarch64_feature_v8_2): New.
 134         (ARMV8_2): New.
 135         (aarch64_opcode_table): Add "bfc".
 136
 137 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 138
 139         * aarch64-asm-2.c: Regenerate.
 140         * aarch64-dis-2.c: Regenerate.
 141         * aarch64-dis.c: Weaken assert.
 142         * aarch64-gen.c: Include the instruction in the list of its
 143         possible aliases.
 144
 145 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 146
 147         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 148         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 149         feature test.
 150
 151 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 152
 153         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 154
 155 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 156
 157         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 158         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 159         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 160         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 161         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 162         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 163         cnthv_ctl_el2, cnthv_cval_el2.
 164         (aarch64_sys_reg_supported_p): Update for the new system
 165         registers.
 166
 167 2015-11-20  Nick Clifton  <nickc@redhat.com>
 168
 169         PR binutils/19224
 170         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 171
 172 2015-11-20  Nick Clifton  <nickc@redhat.com>
 173
 174         * po/zh_CN.po: Updated simplified Chinese translation.
 175
 176 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 177
 178         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 179         of MSR PAN immediate operand.
 180
 181 2015-11-16  Nick Clifton  <nickc@redhat.com>
 182
 183         * rx-dis.c (condition_names): Replace always and never with
 184         invalid, since the always/never conditions can never be legal.
 185
 186 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 187
 188         * configure: Regenerate.
 189
 190 2015-11-11  Alan Modra  <amodra@gmail.com>
 191             Peter Bergner <bergner@vnet.ibm.com>
 192
 193         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 194         Add PPC_OPCODE_VSX3 to the vsx entry.
 195         (powerpc_init_dialect): Set default dialect to power9.
 196         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 197         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 198         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 199         (insert_esync): Test for illegal L operand value.
 200         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 201         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 202         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 203         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 204         PPCVSX3): New defines.
 205         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 206         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 207         <mcrxr>: Use XBFRARB_MASK.
 208         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 209         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 210         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 211         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 212         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 213         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 214         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 215         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 216         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 217         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 218         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 219         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 220         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 221         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 222         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 223         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 224         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 225         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 226         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 227         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 228         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 229         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 230         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 231         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 232         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 233         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 234         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 235         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 236         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 237         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 238         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 239         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 240
 241 2015-11-02  Nick Clifton  <nickc@redhat.com>
 242
 243         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 244         instructions.
 245         * rx-decode.c: Regenerate.
 246
 247 2015-11-02  Nick Clifton  <nickc@redhat.com>
 248
 249         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 250         type to RX_Operand_Zero_Indirect.
 251         * rx-decode.c: Regenerate.
 252         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 253
 254 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 255
 256         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 257         noaliases_p.  Update comments.  Pass noaliases_p rather than
 258         no_aliases to aarch64_opcode_decode.
 259         (print_insn_aarch64_word): Pass no_aliases to
 260         aarch64_decode_insn.
 261
 262 2015-10-27  Vinay  <Vinay.G@kpit.com>
 263
 264         PR binutils/19159
 265         * rl78-decode.opc (MOV): Added offset to DE register in index
 266         addressing mode.
 267         * rl78-decode.c: Regenerate.
 268
 269 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 270
 271         PR binutils/19158
 272         * rl78-decode.opc: Add 's' print operator to instructions that
 273         access system registers.
 274         * rl78-decode.c: Regenerate.
 275         * rl78-dis.c (print_insn_rl78_common): Decode all system
 276         registers.
 277
 278 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 279
 280         PR binutils/19157
 281         * rl78-decode.opc: Add 'a' print operator to mov instructions
 282         using stack pointer plus index addressing.
 283         * rl78-decode.c: Regenerate.
 284
 285 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 286
 287         * s390-opc.c: Fix comment.
 288         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 289         trtt to RRF_U0RER since the second parameter does not need to be a
 290         register pair.
 291
 292 2015-10-08  Nick Clifton  <nickc@redhat.com>
 293
 294         * arc-dis.c (print_insn_arc): Initiallise insn array.
 295
 296 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 297
 298         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 299         'name' rather than 'template'.
 300         * aarch64-opc.c (aarch64_print_operand): Likewise.
 301
 302 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 303
 304         * arc-dis.c: Revamped file for ARC support
 305         * arc-dis.h: Likewise.
 306         * arc-ext.c: Likewise.
 307         * arc-ext.h: Likewise.
 308         * arc-opc.c: Likewise.
 309         * arc-fxi.h: New file.
 310         * arc-regs.h: Likewise.
 311         * arc-tbl.h: Likewise.
 312
 313 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 314
 315         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 316         argument insn type to aarch64_insn.  Rename to ...
 317         (aarch64_decode_insn): ... it.
 318         (print_insn_aarch64_word): Caller updated.
 319
 320 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 321
 322         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 323         (print_insn_aarch64_word): Caller updated.
 324
 325 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 326
 327         * s390-mkopc.c (main): Parse htm and vx flag.
 328         * s390-opc.txt: Mark instructions from the hardware transactional
 329         memory and vector facilities with the "htm"/"vx" flag.
 330
 331 2015-09-28  Nick Clifton  <nickc@redhat.com>
 332
 333         * po/de.po: Updated German translation.
 334
 335 2015-09-28  Tom Rix  <tom@bumblecow.com>
 336
 337         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 338
 339 2015-09-23  Nick Clifton  <nickc@redhat.com>
 340
 341         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 342         function.
 343         * tic30-dis.c (print_branch): Likewise.
 344         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 345         value before left shifting.
 346         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 347         * hppa-dis.c (print_insn_hppa): Likewise.
 348         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 349         array.
 350         * msp430-dis.c (msp430_singleoperand): Likewise.
 351         (msp430_doubleoperand): Likewise.
 352         (print_insn_msp430): Likewise.
 353         * nds32-asm.c (parse_operand): Likewise.
 354         * sh-opc.h (MASK): Likewise.
 355         * v850-dis.c (get_operand_value): Likewise.
 356
 357 2015-09-22  Nick Clifton  <nickc@redhat.com>
 358
 359         * rx-decode.opc (bwl): Use RX_Bad_Size.
 360         (sbwl): Likewise.
 361         (ubwl): Likewise.  Rename to ubw.
 362         (uBWL): Rename to uBW.
 363         Replace all references to uBWL with uBW.
 364         * rx-decode.c: Regenerate.
 365         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 366         (opsize_names): Likewise.
 367         (print_insn_rx): Detect and report RX_Bad_Size.
 368
 369 2015-09-22  Anton Blanchard  <anton@samba.org>
 370
 371         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 372
 373 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 374
 375         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 376         %pmcdper.
 377
 378 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 379
 380         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 381
 382 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 383
 384         PR binutils/18257
 385         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 386         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 387         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 388         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 389         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 390         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 391         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 392         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 393         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 394         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 395         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 396         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 397         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 398         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 399         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 400         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 401         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 402         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 403         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 404         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 405         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 406         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 407         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 408         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 409         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 410         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 411         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 412         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 413         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 414         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 415         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 416         (vex_w_table): Replace terminals with MOD_TABLE entries for
 417         most of mask instructions.
 418
 419 2015-08-17  Alan Modra  <amodra@gmail.com>
 420
 421         * cgen.sh: Trim trailing space from cgen output.
 422         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 423         (print_dis_table): Likewise.
 424         * opc2c.c (dump_lines): Likewise.
 425         (orig_filename): Warning fix.
 426         * ia64-asmtab.c: Regenerate.
 427
 428 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 429
 430         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 431         and higher with ARM instruction set will now mark the 26-bit
 432         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 433         (arm_opcodes): Fix for unpredictable nop being recognized as a
 434         teq.
 435
 436 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 437
 438         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 439         based on 'or' is first.
 440         * mips-opc.c (mips_builtin_opcodes): Ditto.
 441
 442 2015-08-11  Nick Clifton  <nickc@redhat.com>
 443
 444         PR 18800
 445         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 446         instruction.
 447
 448 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 449
 450         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 451
 452 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 453
 454         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 455         * i386-init.h: Regenerated.
 456
 457 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 458
 459         PR binutils/13571
 460         * i386-dis.c (MOD_0FC3): New.
 461         (PREFIX_0FC3): Renamed to ...
 462         (PREFIX_MOD_0_0FC3): This.
 463         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 464         (prefix_table): Replace Ma with Ev on movntiS.
 465         (mod_table): Add MOD_0FC3.
 466
 467 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 468
 469         * configure: Regenerated.
 470
 471 2015-07-23  Alan Modra  <amodra@gmail.com>
 472
 473         PR 18708
 474         * i386-dis.c (get64): Avoid signed integer overflow.
 475
 476 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 477
 478         PR binutils/18631
 479         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 480         "EXEvexHalfBcstXmmq" for the second operand.
 481         (EVEX_W_0F79_P_2): Likewise.
 482         (EVEX_W_0F7A_P_2): Likewise.
 483         (EVEX_W_0F7B_P_2): Likewise.
 484
 485 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 486
 487         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 488         float bitfield format.
 489         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 490         quarter float bitfield format.
 491
 492 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 493
 494         * configure: Regenerated.
 495
 496 2015-07-03  Alan Modra  <amodra@gmail.com>
 497
 498         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 499         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 500         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 501
 502 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 503             Cesar Philippidis  <cesar@codesourcery.com>
 504
 505         * nios2-dis.c (nios2_extract_opcode): New.
 506         (nios2_disassembler_state): New.
 507         (nios2_find_opcode_hash): Use mach parameter to select correct
 508         disassembler state.
 509         (nios2_print_insn_arg): Extend to support new R2 argument letters
 510         and formats.
 511         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 512         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 513         (NIOS2_NUM_OPCODES): Rename to...
 514         (NIOS2_NUM_R1_OPCODES): This.
 515         (nios2_r2_opcodes): New.
 516         (NIOS2_NUM_R2_OPCODES): New.
 517         (nios2_num_r2_opcodes): New.
 518         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 519         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 520         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 521         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 522         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 523
 524 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 525
 526         * i386-dis.c (OP_Mwaitx): New.
 527         (rm_table): Add monitorx/mwaitx.
 528         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 529         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 530         (operand_type_init): Add CpuMWAITX.
 531         * i386-opc.h (CpuMWAITX): New.
 532         (i386_cpu_flags): Add cpumwaitx.
 533         * i386-opc.tbl: Add monitorx and mwaitx.
 534         * i386-init.h: Regenerated.
 535         * i386-tbl.h: Likewise.
 536
 537 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 538
 539         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 540         (insert_esync): New function.
 541         (LS, WC): Use insert_ls.
 542         (ESYNC): Use insert_esync.
 543
 544 2015-06-22  Nick Clifton  <nickc@redhat.com>
 545
 546         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 547         requested region lies beyond it.
 548         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 549         looking for 32-bit insns.
 550         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 551         data.
 552         * sh-dis.c (print_insn_sh): Likewise.
 553         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 554         blocks of instructions.
 555         * vax-dis.c (print_insn_vax): Check that the requested address
 556         does not clash with the stop_vma.
 557
 558 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 559
 560         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 561         * ppc-opc.c (FXM4): Add non-zero optional value.
 562         (TBR): Likewise.
 563         (SXL): Likewise.
 564         (insert_fxm): Handle new default operand value.
 565         (extract_fxm): Likewise.
 566         (insert_tbr): Likewise.
 567         (extract_tbr): Likewise.
 568
 569 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 570
 571         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 572
 573 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 574
 575         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 576
 577 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 578
 579         * ppc-opc.c: Add comment accidentally removed by old commit.
 580         (MTMSRD_L): Delete.
 581
 582 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 583
 584         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 585
 586 2015-06-04  Nick Clifton  <nickc@redhat.com>
 587
 588         PR 18474
 589         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 590
 591 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 592
 593         * arm-dis.c (arm_opcodes): Add "setpan".
 594         (thumb_opcodes): Add "setpan".
 595
 596 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 597
 598         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 599         macros.
 600
 601 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 602
 603         * aarch64-tbl.h (aarch64_feature_rdma): New.
 604         (RDMA): New.
 605         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 606         * aarch64-asm-2.c: Regenerate.
 607         * aarch64-dis-2.c: Regenerate.
 608         * aarch64-opc-2.c: Regenerate.
 609
 610 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 611
 612         * aarch64-tbl.h (aarch64_feature_lor): New.
 613         (LOR): New.
 614         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 615         "stllrb", "stllrh".
 616         * aarch64-asm-2.c: Regenerate.
 617         * aarch64-dis-2.c: Regenerate.
 618         * aarch64-opc-2.c: Regenerate.
 619
 620 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 621
 622         * aarch64-opc.c (F_ARCHEXT): New.
 623         (aarch64_sys_regs): Add "pan".
 624         (aarch64_sys_reg_supported_p): New.
 625         (aarch64_pstatefields): Add "pan".
 626         (aarch64_pstatefield_supported_p): New.
 627
 628 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 629
 630         * i386-tbl.h: Regenerate.
 631
 632 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 633
 634         * i386-dis.c (print_insn): Swap rounding mode specifier and
 635         general purpose register in Intel mode.
 636
 637 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 640         * i386-tbl.h: Regenerate.
 641
 642 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 643
 644         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 645         * i386-init.h: Regenerated.
 646
 647 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 648
 649         PR binutis/18386
 650         * i386-dis.c: Add comments for '@'.
 651         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 652         (enum x86_64_isa): New.
 653         (isa64): Likewise.
 654         (print_i386_disassembler_options): Add amd64 and intel64.
 655         (print_insn): Handle amd64 and intel64.
 656         (putop): Handle '@'.
 657         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 658         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 659         * i386-opc.h (AMD64): New.
 660         (CpuIntel64): Likewise.
 661         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 662         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 663         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 664         * i386-init.h: Regenerated.
 665         * i386-tbl.h: Likewise.
 666
 667 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 668
 669         * ppc-opc.c (IH) New define.
 670         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 671         <tlbie>: Add RS operand for POWER7.
 672         <slbia>: Add IH operand for POWER6.
 673
 674 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 675
 676         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 677         direct branch.
 678         (jmp): Likewise.
 679         * i386-tbl.h: Regenerated.
 680
 681 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 682
 683         * configure.ac: Support bfd_iamcu_arch.
 684         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 685         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 686         CPU_IAMCU_COMPAT_FLAGS.
 687         (cpu_flags): Add CpuIAMCU.
 688         * i386-opc.h (CpuIAMCU): New.
 689         (i386_cpu_flags): Add cpuiamcu.
 690         * configure: Regenerated.
 691         * i386-init.h: Likewise.
 692         * i386-tbl.h: Likewise.
 693
 694 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 695
 696         PR binutis/18386
 697         * i386-dis.c (X86_64_E8): New.
 698         (X86_64_E9): Likewise.
 699         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 700         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 701         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 702         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 703         (putop): Handle '^'.
 704         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 705         REX_W.
 706
 707 2015-04-30  DJ Delorie  <dj@redhat.com>
 708
 709         * disassemble.c (disassembler): Choose suitable disassembler based
 710         on E_ABI.
 711         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 712         it to decode mul/div insns.
 713         * rl78-decode.c: Regenerate.
 714         * rl78-dis.c (print_insn_rl78): Rename to...
 715         (print_insn_rl78_common): ...this, take ISA parameter.
 716         (print_insn_rl78): New.
 717         (print_insn_rl78_g10): New.
 718         (print_insn_rl78_g13): New.
 719         (print_insn_rl78_g14): New.
 720         (rl78_get_disassembler): New.
 721
 722 2015-04-29  Nick Clifton  <nickc@redhat.com>
 723
 724         * po/fr.po: Updated French translation.
 725
 726 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 727
 728         * ppc-opc.c (DCBT_EO): New define.
 729         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 730         <lharx>: Likewise.
 731         <stbcx.>: Likewise.
 732         <sthcx.>: Likewise.
 733         <waitrsv>: Do not enable for POWER7 and later.
 734         <waitimpl>: Likewise.
 735         <dcbt>: Default to the two operand form of the instruction for all
 736         "old" cpus.  For "new" cpus, use the operand ordering that matches
 737         whether the cpu is server or embedded.
 738         <dcbtst>: Likewise.
 739
 740 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 741
 742         * s390-opc.c: New instruction type VV0UU2.
 743         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 744         and WFC.
 745
 746 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 749         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 750         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 751         (vfpclasspd, vfpclassps): Add %XZ.
 752
 753 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 754
 755         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 756         (PREFIX_UD_REPZ): Likewise.
 757         (PREFIX_UD_REPNZ): Likewise.
 758         (PREFIX_UD_DATA): Likewise.
 759         (PREFIX_UD_ADDR): Likewise.
 760         (PREFIX_UD_LOCK): Likewise.
 761
 762 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 763
 764         * i386-dis.c (prefix_requirement): Removed.
 765         (print_insn): Don't set prefix_requirement.  Check
 766         dp->prefix_requirement instead of prefix_requirement.
 767
 768 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         PR binutils/17898
 771         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 772         (PREFIX_MOD_0_0FC7_REG_6): This.
 773         (PREFIX_MOD_3_0FC7_REG_6): New.
 774         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 775         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 776         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 777         PREFIX_MOD_3_0FC7_REG_7.
 778         (mod_table): Replace PREFIX_0FC7_REG_6 with
 779         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 780         PREFIX_MOD_3_0FC7_REG_7.
 781
 782 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 785         (PREFIX_MANDATORY_REPNZ): Likewise.
 786         (PREFIX_MANDATORY_DATA): Likewise.
 787         (PREFIX_MANDATORY_ADDR): Likewise.
 788         (PREFIX_MANDATORY_LOCK): Likewise.
 789         (PREFIX_MANDATORY): Likewise.
 790         (PREFIX_UD_SHIFT): Set to 8
 791         (PREFIX_UD_REPZ): Updated.
 792         (PREFIX_UD_REPNZ): Likewise.
 793         (PREFIX_UD_DATA): Likewise.
 794         (PREFIX_UD_ADDR): Likewise.
 795         (PREFIX_UD_LOCK): Likewise.
 796         (PREFIX_IGNORED_SHIFT): New.
 797         (PREFIX_IGNORED_REPZ): Likewise.
 798         (PREFIX_IGNORED_REPNZ): Likewise.
 799         (PREFIX_IGNORED_DATA): Likewise.
 800         (PREFIX_IGNORED_ADDR): Likewise.
 801         (PREFIX_IGNORED_LOCK): Likewise.
 802         (PREFIX_OPCODE): Likewise.
 803         (PREFIX_IGNORED): Likewise.
 804         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 805         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 806         (three_byte_table): Likewise.
 807         (mod_table): Likewise.
 808         (mandatory_prefix): Renamed to ...
 809         (prefix_requirement): This.
 810         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 811         Update PREFIX_90 entry.
 812         (get_valid_dis386): Check prefix_requirement to see if a prefix
 813         should be ignored.
 814         (print_insn): Replace mandatory_prefix with prefix_requirement.
 815
 816 2015-04-15  Renlin Li  <renlin.li@arm.com>
 817
 818         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 819         use it for ssat and ssat16.
 820         (print_insn_thumb32): Add handle case for 'D' control code.
 821
 822 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 823             H.J. Lu  <hongjiu.lu@intel.com>
 824
 825         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 826         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 827         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 828         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 829         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 830         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 831         Fill prefix_requirement field.
 832         (struct dis386): Add prefix_requirement field.
 833         (dis386): Fill prefix_requirement field.
 834         (dis386_twobyte): Ditto.
 835         (twobyte_has_mandatory_prefix_: Remove.
 836         (reg_table): Fill prefix_requirement field.
 837         (prefix_table): Ditto.
 838         (x86_64_table): Ditto.
 839         (three_byte_table): Ditto.
 840         (xop_table): Ditto.
 841         (vex_table): Ditto.
 842         (vex_len_table): Ditto.
 843         (vex_w_table): Ditto.
 844         (mod_table): Ditto.
 845         (bad_opcode): Ditto.
 846         (print_insn): Use prefix_requirement.
 847         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 848         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 849         (float_reg): Ditto.
 850
 851 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 852
 853         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 854
 855 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 856
 857         * Makefile.in: Regenerated.
 858
 859 2015-03-25  Anton Blanchard  <anton@samba.org>
 860
 861         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 862         powerpc_opcd_indices and vle_opcd_indices once.
 863
 864 2015-03-25  Anton Blanchard  <anton@samba.org>
 865
 866         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 867
 868 2015-03-24  Terry Guo  <terry.guo@arm.com>
 869
 870         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 871         (opcode16): Likewise.
 872         (coprocessor_opcodes): Replace bit with feature struct.
 873         (neon_opcodes): Likewise.
 874         (arm_opcodes): Likewise.
 875         (thumb_opcodes): Likewise.
 876         (thumb32_opcodes): Likewise.
 877         (print_insn_coprocessor): Likewise.
 878         (print_insn_arm): Likewise.
 879         (select_arm_features): Follow new feature struct.
 880
 881 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 882
 883         * i386-dis.c (rm_table): Add clzero.
 884         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 885         Add CPU_CLZERO_FLAGS.
 886         (cpu_flags): Add CpuCLZERO.
 887         * i386-opc.h: Add CpuCLZERO.
 888         * i386-opc.tbl: Add clzero.
 889         * i386-init.h: Re-generated.
 890         * i386-tbl.h: Re-generated.
 891
 892 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 893
 894         * mips-opc.c (decode_mips_operand): Fix constraint issues
 895         with u and y operands.
 896
 897 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 898
 899         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 900
 901 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 902
 903         * s390-opc.c: Add new IBM z13 instructions.
 904         * s390-opc.txt: Likewise.
 905
 906 2015-03-10  Renlin Li  <renlin.li@arm.com>
 907
 908         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 909         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 910         related alias.
 911         * aarch64-asm-2.c: Regenerate.
 912         * aarch64-dis-2.c: Likewise.
 913         * aarch64-opc-2.c: Likewise.
 914
 915 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 916
 917         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 918
 919 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 920
 921         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 922         arch_sh_up.
 923         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 924         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 925
 926 2015-02-23  Vinay  <Vinay.G@kpit.com>
 927
 928         * rl78-decode.opc (MOV): Added space between two operands for
 929         'mov' instruction in index addressing mode.
 930         * rl78-decode.c: Regenerate.
 931
 932 2015-02-19  Pedro Alves  <palves@redhat.com>
 933
 934         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 935
 936 2015-02-10  Pedro Alves  <palves@redhat.com>
 937             Tom Tromey  <tromey@redhat.com>
 938
 939         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 940         microblaze_and, microblaze_xor.
 941         * microblaze-opc.h (opcodes): Adjust.
 942
 943 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 944
 945         * Makefile.am: Add FT32 files.
 946         * configure.ac: Handle FT32.
 947         * disassemble.c (disassembler): Call print_insn_ft32.
 948         * ft32-dis.c: New file.
 949         * ft32-opc.c: New file.
 950         * Makefile.in: Regenerate.
 951         * configure: Regenerate.
 952         * po/POTFILES.in: Regenerate.
 953
 954 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 955
 956         * nds32-asm.c (keyword_sr): Add new system registers.
 957
 958 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 959
 960         * s390-dis.c (s390_extract_operand): Support vector register
 961         operands.
 962         (s390_print_insn_with_opcode): Support new operands types and add
 963         new handling of optional operands.
 964         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 965         and include opcode/s390.h instead.
 966         (struct op_struct): New field `flags'.
 967         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 968         (dumpTable): Dump flags.
 969         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 970         string.
 971         * s390-opc.c: Add new operands types, instruction formats, and
 972         instruction masks.
 973         (s390_opformats): Add new formats for .insn.
 974         * s390-opc.txt: Add new instructions.
 975
 976 2015-01-01  Alan Modra  <amodra@gmail.com>
 977
 978         Update year range in copyright notice of all files.
 979
 980 For older changes see ChangeLog-2014
 981 \f
 982 Copyright (C) 2015 Free Software Foundation, Inc.
 983
 984 Copying and distribution of this file, with or without modification,
 985 are permitted in any medium without royalty provided the copyright
 986 notice and this notice are preserved.
 987
 988 Local Variables:
 989 mode: change-log
 990 left-margin: 8
 991 fill-column: 74
 992 version-control: never
 993 End: