1 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
4 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
6 2020-03-13 Jan Beulich <jbeulich@suse.com>
8 * i386-dis.c (X86_64_0D): Rename to ...
11 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
13 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
14 * Makefile.in: Regenerated.
16 2020-03-09 Jan Beulich <jbeulich@suse.com>
18 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
20 * i386-tbl.h: Re-generate.
22 2020-03-09 Jan Beulich <jbeulich@suse.com>
24 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
25 vprot*, vpsha*, and vpshl*.
26 * i386-tbl.h: Re-generate.
28 2020-03-09 Jan Beulich <jbeulich@suse.com>
30 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
31 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
32 * i386-tbl.h: Re-generate.
34 2020-03-09 Jan Beulich <jbeulich@suse.com>
36 * i386-gen.c (set_bitfield): Ignore zero-length field names.
37 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
38 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
39 * i386-tbl.h: Re-generate.
41 2020-03-09 Jan Beulich <jbeulich@suse.com>
43 * i386-gen.c (struct template_arg, struct template_instance,
44 struct template_param, struct template, templates,
45 parse_template, expand_templates): New.
46 (process_i386_opcodes): Various local variables moved to
47 expand_templates. Call parse_template and expand_templates.
48 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
49 * i386-tbl.h: Re-generate.
51 2020-03-06 Jan Beulich <jbeulich@suse.com>
53 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
54 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
55 register and memory source templates. Replace VexW= by VexW*
57 * i386-tbl.h: Re-generate.
59 2020-03-06 Jan Beulich <jbeulich@suse.com>
61 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
62 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
63 * i386-tbl.h: Re-generate.
65 2020-03-06 Jan Beulich <jbeulich@suse.com>
67 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
68 * i386-tbl.h: Re-generate.
70 2020-03-06 Jan Beulich <jbeulich@suse.com>
72 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
73 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
74 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
75 VexW0 on SSE2AVX variants.
76 (vmovq): Drop NoRex64 from XMM/XMM variants.
77 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
78 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
80 * i386-tbl.h: Re-generate.
82 2020-03-06 Jan Beulich <jbeulich@suse.com>
84 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
85 * i386-opc.h (Rex64): Delete.
86 (struct i386_opcode_modifier): Remove rex64 field.
87 * i386-opc.tbl (crc32): Drop Rex64.
88 Replace Rex64 with Size64 everywhere else.
89 * i386-tbl.h: Re-generate.
91 2020-03-06 Jan Beulich <jbeulich@suse.com>
93 * i386-dis.c (OP_E_memory): Exclude recording of used address
94 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
95 addressed memory operands for MPX insns.
97 2020-03-06 Jan Beulich <jbeulich@suse.com>
99 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
100 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
101 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
102 (ptwrite): Split into non-64-bit and 64-bit forms.
103 * i386-tbl.h: Re-generate.
105 2020-03-06 Jan Beulich <jbeulich@suse.com>
107 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
109 * i386-tbl.h: Re-generate.
111 2020-03-04 Jan Beulich <jbeulich@suse.com>
113 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
114 (prefix_table): Move vmmcall here. Add vmgexit.
115 (rm_table): Replace vmmcall entry by prefix_table[] escape.
116 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
117 (cpu_flags): Add CpuSEV_ES entry.
118 * i386-opc.h (CpuSEV_ES): New.
119 (union i386_cpu_flags): Add cpusev_es field.
120 * i386-opc.tbl (vmgexit): New.
121 * i386-init.h, i386-tbl.h: Re-generate.
123 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
125 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
127 * i386-opc.h (IGNORESIZE): New.
128 (DEFAULTSIZE): Likewise.
129 (IgnoreSize): Removed.
130 (DefaultSize): Likewise.
132 (i386_opcode_modifier): Replace ignoresize/defaultsize with
134 * i386-opc.tbl (IgnoreSize): New.
135 (DefaultSize): Likewise.
136 * i386-tbl.h: Regenerated.
138 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
141 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
144 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
147 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
148 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
149 * i386-tbl.h: Regenerated.
151 2020-02-26 Alan Modra <amodra@gmail.com>
153 * aarch64-asm.c: Indent labels correctly.
154 * aarch64-dis.c: Likewise.
155 * aarch64-gen.c: Likewise.
156 * aarch64-opc.c: Likewise.
157 * alpha-dis.c: Likewise.
158 * i386-dis.c: Likewise.
159 * nds32-asm.c: Likewise.
160 * nfp-dis.c: Likewise.
161 * visium-dis.c: Likewise.
163 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
165 * arc-regs.h (int_vector_base): Make it available for all ARC
168 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
170 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
173 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
175 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
176 c.mv/c.li if rs1 is zero.
178 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
180 * i386-gen.c (cpu_flag_init): Replace CpuABM with
181 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
183 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
184 * i386-opc.h (CpuABM): Removed.
186 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
187 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
188 popcnt. Remove CpuABM from lzcnt.
189 * i386-init.h: Regenerated.
190 * i386-tbl.h: Likewise.
192 2020-02-17 Jan Beulich <jbeulich@suse.com>
194 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
195 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
196 VexW1 instead of open-coding them.
197 * i386-tbl.h: Re-generate.
199 2020-02-17 Jan Beulich <jbeulich@suse.com>
201 * i386-opc.tbl (AddrPrefixOpReg): Define.
202 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
203 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
204 templates. Drop NoRex64.
205 * i386-tbl.h: Re-generate.
207 2020-02-17 Jan Beulich <jbeulich@suse.com>
210 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
211 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
212 into Intel syntax instance (with Unpsecified) and AT&T one
214 (vcvtneps2bf16): Likewise, along with folding the two so far
216 * i386-tbl.h: Re-generate.
218 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
220 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
223 2020-02-17 Alan Modra <amodra@gmail.com>
225 * i386-gen.c (cpu_flag_init): Correct last change.
227 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
229 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
232 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
234 * i386-opc.tbl (movsx): Remove Intel syntax comments.
237 2020-02-14 Jan Beulich <jbeulich@suse.com>
240 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
241 destination for Cpu64-only variant.
242 (movzx): Fold patterns.
243 * i386-tbl.h: Re-generate.
245 2020-02-13 Jan Beulich <jbeulich@suse.com>
247 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
248 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
249 CPU_ANY_SSE4_FLAGS entry.
250 * i386-init.h: Re-generate.
252 2020-02-12 Jan Beulich <jbeulich@suse.com>
254 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
255 with Unspecified, making the present one AT&T syntax only.
256 * i386-tbl.h: Re-generate.
258 2020-02-12 Jan Beulich <jbeulich@suse.com>
260 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
261 * i386-tbl.h: Re-generate.
263 2020-02-12 Jan Beulich <jbeulich@suse.com>
266 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
267 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
268 Amd64 and Intel64 templates.
269 (call, jmp): Likewise for far indirect variants. Dro
271 * i386-tbl.h: Re-generate.
273 2020-02-11 Jan Beulich <jbeulich@suse.com>
275 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
276 * i386-opc.h (ShortForm): Delete.
277 (struct i386_opcode_modifier): Remove shortform field.
278 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
279 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
280 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
281 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
283 * i386-tbl.h: Re-generate.
285 2020-02-11 Jan Beulich <jbeulich@suse.com>
287 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
288 fucompi): Drop ShortForm from operand-less templates.
289 * i386-tbl.h: Re-generate.
291 2020-02-11 Alan Modra <amodra@gmail.com>
293 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
294 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
295 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
296 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
297 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
299 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
301 * arm-dis.c (print_insn_cde): Define 'V' parse character.
302 (cde_opcodes): Add VCX* instructions.
304 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
305 Matthew Malcomson <matthew.malcomson@arm.com>
307 * arm-dis.c (struct cdeopcode32): New.
308 (CDE_OPCODE): New macro.
309 (cde_opcodes): New disassembly table.
310 (regnames): New option to table.
311 (cde_coprocs): New global variable.
312 (print_insn_cde): New
313 (print_insn_thumb32): Use print_insn_cde.
314 (parse_arm_disassembler_options): Parse coprocN args.
316 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
319 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
321 * i386-opc.h (AMD64): Removed.
325 (INTEL64ONLY): Likewise.
326 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
327 * i386-opc.tbl (Amd64): New.
329 (Intel64Only): Likewise.
330 Replace AMD64 with Amd64. Update sysenter/sysenter with
331 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
332 * i386-tbl.h: Regenerated.
334 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
337 * z80-dis.c: Add support for GBZ80 opcodes.
339 2020-02-04 Alan Modra <amodra@gmail.com>
341 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
343 2020-02-03 Alan Modra <amodra@gmail.com>
345 * m32c-ibld.c: Regenerate.
347 2020-02-01 Alan Modra <amodra@gmail.com>
349 * frv-ibld.c: Regenerate.
351 2020-01-31 Jan Beulich <jbeulich@suse.com>
353 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
354 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
355 (OP_E_memory): Replace xmm_mdq_mode case label by
356 vex_scalar_w_dq_mode one.
357 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
359 2020-01-31 Jan Beulich <jbeulich@suse.com>
361 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
362 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
363 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
364 (intel_operand_size): Drop vex_w_dq_mode case label.
366 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
368 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
369 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
371 2020-01-30 Alan Modra <amodra@gmail.com>
373 * m32c-ibld.c: Regenerate.
375 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
377 * bpf-opc.c: Regenerate.
379 2020-01-30 Jan Beulich <jbeulich@suse.com>
381 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
382 (dis386): Use them to replace C2/C3 table entries.
383 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
384 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
385 ones. Use Size64 instead of DefaultSize on Intel64 ones.
386 * i386-tbl.h: Re-generate.
388 2020-01-30 Jan Beulich <jbeulich@suse.com>
390 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
392 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
394 * i386-tbl.h: Re-generate.
396 2020-01-30 Alan Modra <amodra@gmail.com>
398 * tic4x-dis.c (tic4x_dp): Make unsigned.
400 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
401 Jan Beulich <jbeulich@suse.com>
404 * i386-dis.c (MOVSXD_Fixup): New function.
405 (movsxd_mode): New enum.
406 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
407 (intel_operand_size): Handle movsxd_mode.
408 (OP_E_register): Likewise.
410 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
411 register on movsxd. Add movsxd with 16-bit destination register
412 for AMD64 and Intel64 ISAs.
413 * i386-tbl.h: Regenerated.
415 2020-01-27 Tamar Christina <tamar.christina@arm.com>
418 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
419 * aarch64-asm-2.c: Regenerate
420 * aarch64-dis-2.c: Likewise.
421 * aarch64-opc-2.c: Likewise.
423 2020-01-21 Jan Beulich <jbeulich@suse.com>
425 * i386-opc.tbl (sysret): Drop DefaultSize.
426 * i386-tbl.h: Re-generate.
428 2020-01-21 Jan Beulich <jbeulich@suse.com>
430 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
432 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
433 * i386-tbl.h: Re-generate.
435 2020-01-20 Nick Clifton <nickc@redhat.com>
437 * po/de.po: Updated German translation.
438 * po/pt_BR.po: Updated Brazilian Portuguese translation.
439 * po/uk.po: Updated Ukranian translation.
441 2020-01-20 Alan Modra <amodra@gmail.com>
443 * hppa-dis.c (fput_const): Remove useless cast.
445 2020-01-20 Alan Modra <amodra@gmail.com>
447 * arm-dis.c (print_insn_arm): Wrap 'T' value.
449 2020-01-18 Nick Clifton <nickc@redhat.com>
451 * configure: Regenerate.
452 * po/opcodes.pot: Regenerate.
454 2020-01-18 Nick Clifton <nickc@redhat.com>
456 Binutils 2.34 branch created.
458 2020-01-17 Christian Biesinger <cbiesinger@google.com>
460 * opintl.h: Fix spelling error (seperate).
462 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
464 * i386-opc.tbl: Add {vex} pseudo prefix.
465 * i386-tbl.h: Regenerated.
467 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
470 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
471 (neon_opcodes): Likewise.
472 (select_arm_features): Make sure we enable MVE bits when selecting
473 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
476 2020-01-16 Jan Beulich <jbeulich@suse.com>
478 * i386-opc.tbl: Drop stale comment from XOP section.
480 2020-01-16 Jan Beulich <jbeulich@suse.com>
482 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
483 (extractps): Add VexWIG to SSE2AVX forms.
484 * i386-tbl.h: Re-generate.
486 2020-01-16 Jan Beulich <jbeulich@suse.com>
488 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
489 Size64 from and use VexW1 on SSE2AVX forms.
490 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
491 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
492 * i386-tbl.h: Re-generate.
494 2020-01-15 Alan Modra <amodra@gmail.com>
496 * tic4x-dis.c (tic4x_version): Make unsigned long.
497 (optab, optab_special, registernames): New file scope vars.
498 (tic4x_print_register): Set up registernames rather than
499 malloc'd registertable.
500 (tic4x_disassemble): Delete optable and optable_special. Use
501 optab and optab_special instead. Throw away old optab,
502 optab_special and registernames when info->mach changes.
504 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
507 * z80-dis.c (suffix): Use .db instruction to generate double
510 2020-01-14 Alan Modra <amodra@gmail.com>
512 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
513 values to unsigned before shifting.
515 2020-01-13 Thomas Troeger <tstroege@gmx.de>
517 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
519 (print_insn_thumb16, print_insn_thumb32): Likewise.
520 (print_insn): Initialize the insn info.
521 * i386-dis.c (print_insn): Initialize the insn info fields, and
524 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
526 * arc-opc.c (C_NE): Make it required.
528 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
530 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
531 reserved register name.
533 2020-01-13 Alan Modra <amodra@gmail.com>
535 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
536 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
538 2020-01-13 Alan Modra <amodra@gmail.com>
540 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
541 result of wasm_read_leb128 in a uint64_t and check that bits
542 are not lost when copying to other locals. Use uint32_t for
543 most locals. Use PRId64 when printing int64_t.
545 2020-01-13 Alan Modra <amodra@gmail.com>
547 * score-dis.c: Formatting.
548 * score7-dis.c: Formatting.
550 2020-01-13 Alan Modra <amodra@gmail.com>
552 * score-dis.c (print_insn_score48): Use unsigned variables for
553 unsigned values. Don't left shift negative values.
554 (print_insn_score32): Likewise.
555 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
557 2020-01-13 Alan Modra <amodra@gmail.com>
559 * tic4x-dis.c (tic4x_print_register): Remove dead code.
561 2020-01-13 Alan Modra <amodra@gmail.com>
563 * fr30-ibld.c: Regenerate.
565 2020-01-13 Alan Modra <amodra@gmail.com>
567 * xgate-dis.c (print_insn): Don't left shift signed value.
568 (ripBits): Formatting, use 1u.
570 2020-01-10 Alan Modra <amodra@gmail.com>
572 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
573 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
575 2020-01-10 Alan Modra <amodra@gmail.com>
577 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
578 and XRREG value earlier to avoid a shift with negative exponent.
579 * m10200-dis.c (disassemble): Similarly.
581 2020-01-09 Nick Clifton <nickc@redhat.com>
584 * z80-dis.c (ld_ii_ii): Use correct cast.
586 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
589 * z80-dis.c (ld_ii_ii): Use character constant when checking
592 2020-01-09 Jan Beulich <jbeulich@suse.com>
594 * i386-dis.c (SEP_Fixup): New.
596 (dis386_twobyte): Use it for sysenter/sysexit.
597 (enum x86_64_isa): Change amd64 enumerator to value 1.
598 (OP_J): Compare isa64 against intel64 instead of amd64.
599 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
601 * i386-tbl.h: Re-generate.
603 2020-01-08 Alan Modra <amodra@gmail.com>
605 * z8k-dis.c: Include libiberty.h
606 (instr_data_s): Make max_fetched unsigned.
607 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
608 Don't exceed byte_info bounds.
609 (output_instr): Make num_bytes unsigned.
610 (unpack_instr): Likewise for nibl_count and loop.
611 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
613 * z8k-opc.h: Regenerate.
615 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
617 * arc-tbl.h (llock): Use 'LLOCK' as class.
619 (scond): Use 'SCOND' as class.
621 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
624 2020-01-06 Alan Modra <amodra@gmail.com>
626 * m32c-ibld.c: Regenerate.
628 2020-01-06 Alan Modra <amodra@gmail.com>
631 * z80-dis.c (suffix): Don't use a local struct buffer copy.
632 Peek at next byte to prevent recursion on repeated prefix bytes.
633 Ensure uninitialised "mybuf" is not accessed.
634 (print_insn_z80): Don't zero n_fetch and n_used here,..
635 (print_insn_z80_buf): ..do it here instead.
637 2020-01-04 Alan Modra <amodra@gmail.com>
639 * m32r-ibld.c: Regenerate.
641 2020-01-04 Alan Modra <amodra@gmail.com>
643 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
645 2020-01-04 Alan Modra <amodra@gmail.com>
647 * crx-dis.c (match_opcode): Avoid shift left of signed value.
649 2020-01-04 Alan Modra <amodra@gmail.com>
651 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
653 2020-01-03 Jan Beulich <jbeulich@suse.com>
655 * aarch64-tbl.h (aarch64_opcode_table): Use
656 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
658 2020-01-03 Jan Beulich <jbeulich@suse.com>
660 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
661 forms of SUDOT and USDOT.
663 2020-01-03 Jan Beulich <jbeulich@suse.com>
665 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
667 * opcodes/aarch64-dis-2.c: Re-generate.
669 2020-01-03 Jan Beulich <jbeulich@suse.com>
671 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
673 * opcodes/aarch64-dis-2.c: Re-generate.
675 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
677 * z80-dis.c: Add support for eZ80 and Z80 instructions.
679 2020-01-01 Alan Modra <amodra@gmail.com>
681 Update year range in copyright notice of all files.
683 For older changes see ChangeLog-2019
685 Copyright (C) 2020 Free Software Foundation, Inc.
687 Copying and distribution of this file, with or without modification,
688 are permitted in any medium without royalty provided the copyright
689 notice and this notice are preserved.
695 version-control: never