opcodes/ChangeLog

   1 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/20154
   4         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
   5         (opcode_modifiers): Add AMD64 and Intel64.
   6         (main): Properly verify CpuMax.
   7         * i386-opc.h (CpuAMD64): Removed.
   8         (CpuIntel64): Likewise.
   9         (CpuMax): Set to CpuNo64.
  10         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
  11         (AMD64): New.
  12         (Intel64): Likewise.
  13         (i386_opcode_modifier): Add amd64 and intel64.
  14         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
  15         on call and jmp.
  16         * i386-init.h: Regenerated.
  17         * i386-tbl.h: Likewise.
  18
  19 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  20
  21         PR gas/20154
  22         * i386-gen.c (main): Fail if CpuMax is incorrect.
  23         * i386-opc.h (CpuMax): Set to CpuIntel64.
  24         * i386-tbl.h: Regenerated.
  25
  26 2016-05-27  Nick Clifton  <nickc@redhat.com>
  27
  28         PR target/20150
  29         * msp430-dis.c (msp430dis_read_two_bytes): New function.
  30         (msp430dis_opcode_unsigned): New function.
  31         (msp430dis_opcode_signed): New function.
  32         (msp430_singleoperand): Use the new opcode reading functions.
  33         Only disassenmble bytes if they were successfully read.
  34         (msp430_doubleoperand): Likewise.
  35         (msp430_branchinstr): Likewise.
  36         (msp430x_callx_instr): Likewise.
  37         (print_insn_msp430): Check that it is safe to read bytes before
  38         attempting disassembly.  Use the new opcode reading functions.
  39
  40 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
  41
  42         * ppc-opc.c (CY): New define.  Document it.
  43         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
  44
  45 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
  46
  47         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
  48         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
  49         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
  50         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
  51         CPU_ANY_AVX_FLAGS.
  52         * i386-init.h: Regenerated.
  53
  54 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
  55
  56         PR gas/20141
  57         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
  58         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
  59         * i386-init.h: Regenerated.
  60
  61 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
  62
  63         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
  64         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
  65         * i386-init.h: Regenerated.
  66
  67 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
  68
  69         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
  70         information.
  71         (print_insn_arc): Set insn_type information.
  72         * arc-opc.c (C_CC): Add F_CLASS_COND.
  73         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
  74         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
  75         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
  76         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
  77         (brne, brne_s, jeq_s, jne_s): Likewise.
  78
  79 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
  80
  81         * arc-tbl.h (neg): New instruction variant.
  82
  83 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
  84
  85         * arc-dis.c (find_format, find_format, get_auxreg)
  86         (print_insn_arc): Changed.
  87         * arc-ext.h (INSERT_XOP): Likewise.
  88
  89 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  90
  91         * tic54x-dis.c (sprint_mmr): Adjust.
  92         * tic54x-opc.c: Likewise.
  93
  94 2016-05-19  Alan Modra  <amodra@gmail.com>
  95
  96         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
  97
  98 2016-05-19  Alan Modra  <amodra@gmail.com>
  99
 100         * ppc-opc.c: Formatting.
 101         (NSISIGNOPT): Define.
 102         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 103
 104 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 105
 106         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 107         replacing references to `micromips_ase' throughout.
 108         (_print_insn_mips): Don't use file-level microMIPS annotation to
 109         determine the disassembly mode with the symbol table.
 110
 111 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 112
 113         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 114
 115 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 116
 117         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 118         mips64r6.
 119         * mips-opc.c (D34): New macro.
 120         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 121
 122 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 123
 124         * i386-dis.c (prefix_table): Add RDPID instruction.
 125         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 126         (cpu_flags): Add RDPID bitfield.
 127         * i386-opc.h (enum): Add RDPID element.
 128         (i386_cpu_flags): Add RDPID field.
 129         * i386-opc.tbl: Add RDPID instruction.
 130         * i386-init.h: Regenerate.
 131         * i386-tbl.h: Regenerate.
 132
 133 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 134
 135         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 136         branch type of a symbol.
 137         (print_insn): Likewise.
 138
 139 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 140
 141         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 142         Mainline Security Extensions instructions.
 143         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 144         Extensions instructions.
 145         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 146         instructions.
 147         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 148         special registers.
 149
 150 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 151
 152         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 153
 154 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 155
 156         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 157         (arcExtMap_genOpcode): Likewise.
 158         * arc-opc.c (arg_32bit_rc): Define new variable.
 159         (arg_32bit_u6): Likewise.
 160         (arg_32bit_limm): Likewise.
 161
 162 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 163
 164         * aarch64-gen.c (VERIFIER): Define.
 165         * aarch64-opc.c (VERIFIER): Define.
 166         (verify_ldpsw): Use static linkage.
 167         * aarch64-opc.h (verify_ldpsw): Remove.
 168         * aarch64-tbl.h: Use VERIFIER for verifiers.
 169
 170 2016-04-28  Nick Clifton  <nickc@redhat.com>
 171
 172         PR target/19722
 173         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 174         * aarch64-opc.c (verify_ldpsw): New function.
 175         * aarch64-opc.h (verify_ldpsw): New prototype.
 176         * aarch64-tbl.h: Add initialiser for verifier field.
 177         (LDPSW): Set verifier to verify_ldpsw.
 178
 179 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 180
 181         PR binutils/19983
 182         PR binutils/19984
 183         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 184         smaller than address size.
 185
 186 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 187
 188         * alpha-dis.c: Regenerate.
 189         * crx-dis.c: Likewise.
 190         * disassemble.c: Likewise.
 191         * epiphany-opc.c: Likewise.
 192         * fr30-opc.c: Likewise.
 193         * frv-opc.c: Likewise.
 194         * ip2k-opc.c: Likewise.
 195         * iq2000-opc.c: Likewise.
 196         * lm32-opc.c: Likewise.
 197         * lm32-opinst.c: Likewise.
 198         * m32c-opc.c: Likewise.
 199         * m32r-opc.c: Likewise.
 200         * m32r-opinst.c: Likewise.
 201         * mep-opc.c: Likewise.
 202         * mt-opc.c: Likewise.
 203         * or1k-opc.c: Likewise.
 204         * or1k-opinst.c: Likewise.
 205         * tic80-opc.c: Likewise.
 206         * xc16x-opc.c: Likewise.
 207         * xstormy16-opc.c: Likewise.
 208
 209 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 210
 211         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 212         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 213         calcsd, and calcxd instructions.
 214         * arc-opc.c (insert_nps_bitop_size): Delete.
 215         (extract_nps_bitop_size): Delete.
 216         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 217         (extract_nps_qcmp_m3): Define.
 218         (extract_nps_qcmp_m2): Define.
 219         (extract_nps_qcmp_m1): Define.
 220         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 221         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 222         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 223         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 224         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 225         NPS_QCMP_M3.
 226
 227 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 228
 229         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 230
 231 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         * Makefile.in: Regenerated with automake 1.11.6.
 234         * aclocal.m4: Likewise.
 235
 236 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 237
 238         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 239         instructions.
 240         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 241         (extract_nps_cmem_uimm16): New function.
 242         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 243
 244 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 245
 246         * arc-dis.c (arc_insn_length): New function.
 247         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 248         (find_format): Change insnLen parameter to unsigned.
 249
 250 2016-04-13  Nick Clifton  <nickc@redhat.com>
 251
 252         PR target/19937
 253         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 254         the LD.B and LD.BU instructions.
 255
 256 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 257
 258         * arc-dis.c (find_format): Check for extension flags.
 259         (print_flags): New function.
 260         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 261         .extAuxRegister.
 262         * arc-ext.c (arcExtMap_coreRegName): Use
 263         LAST_EXTENSION_CORE_REGISTER.
 264         (arcExtMap_coreReadWrite): Likewise.
 265         (dump_ARC_extmap): Update printing.
 266         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 267         (arc_aux_regs): Add cpu field.
 268         * arc-regs.h: Add cpu field, lower case name aux registers.
 269
 270 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 271
 272         * arc-tbl.h: Add rtsc, sleep with no arguments.
 273
 274 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 275
 276         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 277         Initialize.
 278         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 279         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 280         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 281         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 282         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 283         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 284         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 285         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 286         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 287         (arc_opcode arc_opcodes): Null terminate the array.
 288         (arc_num_opcodes): Remove.
 289         * arc-ext.h (INSERT_XOP): Define.
 290         (extInstruction_t): Likewise.
 291         (arcExtMap_instName): Delete.
 292         (arcExtMap_insn): New function.
 293         (arcExtMap_genOpcode): Likewise.
 294         * arc-ext.c (ExtInstruction): Remove.
 295         (create_map): Zero initialize instruction fields.
 296         (arcExtMap_instName): Remove.
 297         (arcExtMap_insn): New function.
 298         (dump_ARC_extmap): More info while debuging.
 299         (arcExtMap_genOpcode): New function.
 300         * arc-dis.c (find_format): New function.
 301         (print_insn_arc): Use find_format.
 302         (arc_get_disassembler): Enable dump_ARC_extmap only when
 303         debugging.
 304
 305 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 306
 307         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 308         instruction bits out.
 309
 310 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 311
 312         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 313         * arc-opc.c (arc_flag_operands): Add new flags.
 314         (arc_flag_classes): Add new classes.
 315
 316 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 317
 318         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 319
 320 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 321
 322         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 323         encode1, rflt, crc16, and crc32 instructions.
 324         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 325         (arc_flag_classes): Add C_NPS_R.
 326         (insert_nps_bitop_size_2b): New function.
 327         (extract_nps_bitop_size_2b): Likewise.
 328         (insert_nps_bitop_uimm8): Likewise.
 329         (extract_nps_bitop_uimm8): Likewise.
 330         (arc_operands): Add new operand entries.
 331
 332 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 333
 334         * arc-regs.h: Add a new subclass field.  Add double assist
 335         accumulator register values.
 336         * arc-tbl.h: Use DPA subclass to mark the double assist
 337         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 338         * arc-opc.c (RSP): Define instead of SP.
 339         (arc_aux_regs): Add the subclass field.
 340
 341 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 342
 343         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 344
 345 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 346
 347         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 348         NPS_R_SRC1.
 349
 350 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 351
 352         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 353         issues.  No functional changes.
 354
 355 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 356
 357         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 358         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 359         (RTT): Remove duplicate.
 360         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 361         (PCT_CONFIG*): Remove.
 362         (D1L, D1H, D2H, D2L): Define.
 363
 364 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 365
 366         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 367
 368 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 369
 370         * arc-tbl.h (invld07): Remove.
 371         * arc-ext-tbl.h: New file.
 372         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 373         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 374
 375 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 376
 377         Fix -Wstack-usage warnings.
 378         * aarch64-dis.c (print_operands): Substitute size.
 379         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 380
 381 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 382
 383         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 384         to get a proper diagnostic when an invalid ASR register is used.
 385
 386 2016-03-22  Nick Clifton  <nickc@redhat.com>
 387
 388         * configure: Regenerate.
 389
 390 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 391
 392         * arc-nps400-tbl.h: New file.
 393         * arc-opc.c: Add top level comment.
 394         (insert_nps_3bit_dst): New function.
 395         (extract_nps_3bit_dst): New function.
 396         (insert_nps_3bit_src2): New function.
 397         (extract_nps_3bit_src2): New function.
 398         (insert_nps_bitop_size): New function.
 399         (extract_nps_bitop_size): New function.
 400         (arc_flag_operands): Add nps400 entries.
 401         (arc_flag_classes): Add nps400 entries.
 402         (arc_operands): Add nps400 entries.
 403         (arc_opcodes): Add nps400 include.
 404
 405 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 406
 407         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 408         the new class enum values.
 409
 410 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 411
 412         * arc-dis.c (print_insn_arc): Handle nps400.
 413
 414 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 415
 416         * arc-opc.c (BASE): Delete.
 417
 418 2016-03-18  Nick Clifton  <nickc@redhat.com>
 419
 420         PR target/19721
 421         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 422         of MOV insn that aliases an ORR insn.
 423
 424 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 425
 426         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 427
 428 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 429
 430         * mcore-opc.h: Add const qualifiers.
 431         * microblaze-opc.h (struct op_code_struct): Likewise.
 432         * sh-opc.h: Likewise.
 433         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 434         (tic4x_print_op): Likewise.
 435
 436 2016-03-02  Alan Modra  <amodra@gmail.com>
 437
 438         * or1k-desc.h: Regenerate.
 439         * fr30-ibld.c: Regenerate.
 440         * rl78-decode.c: Regenerate.
 441
 442 2016-03-01  Nick Clifton  <nickc@redhat.com>
 443
 444         PR target/19747
 445         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 446
 447 2016-02-24  Renlin Li  <renlin.li@arm.com>
 448
 449         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 450         (print_insn_coprocessor): Support fp16 instructions.
 451
 452 2016-02-24  Renlin Li  <renlin.li@arm.com>
 453
 454         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 455         vminnm, vrint(mpna).
 456
 457 2016-02-24  Renlin Li  <renlin.li@arm.com>
 458
 459         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 460         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 461
 462 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 463
 464         * i386-dis.c (print_insn): Parenthesize expression to prevent
 465         truncated addresses.
 466         (OP_J): Likewise.
 467
 468 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 469             Janek van Oirschot  <jvanoirs@synopsys.com>
 470
 471         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 472         variable.
 473
 474 2016-02-04  Nick Clifton  <nickc@redhat.com>
 475
 476         PR target/19561
 477         * msp430-dis.c (print_insn_msp430): Add a special case for
 478         decoding an RRC instruction with the ZC bit set in the extension
 479         word.
 480
 481 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 482
 483         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 484         * epiphany-ibld.c: Regenerate.
 485         * fr30-ibld.c: Regenerate.
 486         * frv-ibld.c: Regenerate.
 487         * ip2k-ibld.c: Regenerate.
 488         * iq2000-ibld.c: Regenerate.
 489         * lm32-ibld.c: Regenerate.
 490         * m32c-ibld.c: Regenerate.
 491         * m32r-ibld.c: Regenerate.
 492         * mep-ibld.c: Regenerate.
 493         * mt-ibld.c: Regenerate.
 494         * or1k-ibld.c: Regenerate.
 495         * xc16x-ibld.c: Regenerate.
 496         * xstormy16-ibld.c: Regenerate.
 497
 498 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 499
 500         * epiphany-dis.c: Regenerated from latest cpu files.
 501
 502 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 503
 504         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 505         test bit.
 506
 507 2016-01-25  Renlin Li  <renlin.li@arm.com>
 508
 509         * arm-dis.c (mapping_symbol_for_insn): New function.
 510         (find_ifthen_state): Call mapping_symbol_for_insn().
 511
 512 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 513
 514         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 515         of MSR UAO immediate operand.
 516
 517 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 518
 519         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 520         instruction support.
 521
 522 2016-01-17  Alan Modra  <amodra@gmail.com>
 523
 524         * configure: Regenerate.
 525
 526 2016-01-14  Nick Clifton  <nickc@redhat.com>
 527
 528         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 529         instructions that can support stack pointer operations.
 530         * rl78-decode.c: Regenerate.
 531         * rl78-dis.c: Fix display of stack pointer in MOVW based
 532         instructions.
 533
 534 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 535
 536         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 537         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 538         erxtatus_el1 and erxaddr_el1.
 539
 540 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 541
 542         * arm-dis.c (arm_opcodes): Add "esb".
 543         (thumb_opcodes): Likewise.
 544
 545 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 546
 547         * ppc-opc.c <xscmpnedp>: Delete.
 548         <xvcmpnedp>: Likewise.
 549         <xvcmpnedp.>: Likewise.
 550         <xvcmpnesp>: Likewise.
 551         <xvcmpnesp.>: Likewise.
 552
 553 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 554
 555         PR gas/13050
 556         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 557         addition to ISA_A.
 558
 559 2016-01-01  Alan Modra  <amodra@gmail.com>
 560
 561         Update year range in copyright notice of all files.
 562
 563 For older changes see ChangeLog-2015
 564 \f
 565 Copyright (C) 2016 Free Software Foundation, Inc.
 566
 567 Copying and distribution of this file, with or without modification,
 568 are permitted in any medium without royalty provided the copyright
 569 notice and this notice are preserved.
 570
 571 Local Variables:
 572 mode: change-log
 573 left-margin: 8
 574 fill-column: 74
 575 version-control: never
 576 End: